1/*
2 * Copyright (c) 2014, 2017 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Andreas Sandberg
38 */
39
40#include "dev/virtio/pci.hh"
41
42#include "base/bitfield.hh"
43#include "debug/VIOIface.hh"
44#include "mem/packet_access.hh"
45#include "params/PciVirtIO.hh"
46
47PciVirtIO::PciVirtIO(const Params *params)
48    : PciDevice(params), queueNotify(0), interruptDeliveryPending(false),
49      vio(*params->vio), callbackKick(this)
50{
51    // Override the subsystem ID with the device ID from VirtIO
52    config.subsystemID = htole(vio.deviceId);
53
54    // The kernel driver expects the BAR size to be an exact power of
55    // two. Nothing else is supported. Therefore, we need to force
56    // that alignment here. We do not touch vio.configSize as this is
57    // used to check accesses later on.
58    BARSize[0] = alignToPowerOfTwo(BAR0_SIZE_BASE + vio.configSize);
59
60    vio.registerKickCallback(&callbackKick);
61}
62
63PciVirtIO::~PciVirtIO()
64{
65}
66
67Tick
68PciVirtIO::read(PacketPtr pkt)
69{
70    const unsigned M5_VAR_USED size(pkt->getSize());
71    int bar;
72    Addr offset;
73    if (!getBAR(pkt->getAddr(), bar, offset))
74        panic("Invalid PCI memory access to unmapped memory.\n");
75    assert(bar == 0);
76
77    DPRINTF(VIOIface, "Reading offset 0x%x [len: %i]\n", offset, size);
78
79    // Forward device configuration writes to the device VirtIO model
80    if (offset >= OFF_VIO_DEVICE) {
81        vio.readConfig(pkt, offset - OFF_VIO_DEVICE);
82        return 0;
83    }
84
85    pkt->makeResponse();
86
87    switch(offset) {
88      case OFF_DEVICE_FEATURES:
89        DPRINTF(VIOIface, "   DEVICE_FEATURES request\n");
90        assert(size == sizeof(uint32_t));
91        pkt->setLE<uint32_t>(vio.deviceFeatures);
92        break;
93
94      case OFF_GUEST_FEATURES:
95        DPRINTF(VIOIface, "   GUEST_FEATURES request\n");
96        assert(size == sizeof(uint32_t));
97        pkt->setLE<uint32_t>(vio.getGuestFeatures());
98        break;
99
100      case OFF_QUEUE_ADDRESS:
101        DPRINTF(VIOIface, "   QUEUE_ADDRESS request\n");
102        assert(size == sizeof(uint32_t));
103        pkt->setLE<uint32_t>(vio.getQueueAddress());
104        break;
105
106      case OFF_QUEUE_SIZE:
107        DPRINTF(VIOIface, "   QUEUE_SIZE request\n");
108        assert(size == sizeof(uint16_t));
109        pkt->setLE<uint16_t>(vio.getQueueSize());
110        break;
111
112      case OFF_QUEUE_SELECT:
113        DPRINTF(VIOIface, "   QUEUE_SELECT\n");
114        assert(size == sizeof(uint16_t));
115        pkt->setLE<uint16_t>(vio.getQueueSelect());
116        break;
117
118      case OFF_QUEUE_NOTIFY:
119        DPRINTF(VIOIface, "   QUEUE_NOTIFY request\n");
120        assert(size == sizeof(uint16_t));
121        pkt->setLE<uint16_t>(queueNotify);
122        break;
123
124      case OFF_DEVICE_STATUS:
125        DPRINTF(VIOIface, "   DEVICE_STATUS request\n");
126        assert(size == sizeof(uint8_t));
127        pkt->setLE<uint8_t>(vio.getDeviceStatus());
128        break;
129
130      case OFF_ISR_STATUS: {
131          DPRINTF(VIOIface, "   ISR_STATUS\n");
132          assert(size == sizeof(uint8_t));
133          const uint8_t isr_status(interruptDeliveryPending ? 1 : 0);
134          if (interruptDeliveryPending) {
135              interruptDeliveryPending = false;
136              intrClear();
137          }
138          pkt->setLE<uint8_t>(isr_status);
139      } break;
140
141      default:
142        panic("Unhandled read offset (0x%x)\n", offset);
143    }
144
145    return 0;
146}
147
148Tick
149PciVirtIO::write(PacketPtr pkt)
150{
151    const unsigned M5_VAR_USED size(pkt->getSize());
152    int bar;
153    Addr offset;
154    if (!getBAR(pkt->getAddr(), bar, offset))
155        panic("Invalid PCI memory access to unmapped memory.\n");
156    assert(bar == 0);
157
158    DPRINTF(VIOIface, "Writing offset 0x%x [len: %i]\n", offset, size);
159
160    // Forward device configuration writes to the device VirtIO model
161    if (offset >= OFF_VIO_DEVICE) {
162        vio.writeConfig(pkt, offset - OFF_VIO_DEVICE);
163        return 0;
164    }
165
166    pkt->makeResponse();
167
168    switch(offset) {
169      case OFF_DEVICE_FEATURES:
170        warn("Guest tried to write device features.");
171        break;
172
173      case OFF_GUEST_FEATURES:
174        DPRINTF(VIOIface, "   WRITE GUEST_FEATURES request\n");
175        assert(size == sizeof(uint32_t));
176        vio.setGuestFeatures(pkt->getLE<uint32_t>());
177        break;
178
179      case OFF_QUEUE_ADDRESS:
180        DPRINTF(VIOIface, "   WRITE QUEUE_ADDRESS\n");
181        assert(size == sizeof(uint32_t));
182        vio.setQueueAddress(pkt->getLE<uint32_t>());
183        break;
184
185      case OFF_QUEUE_SIZE:
186        panic("Guest tried to write queue size.");
187        break;
188
189      case OFF_QUEUE_SELECT:
190        DPRINTF(VIOIface, "   WRITE QUEUE_SELECT\n");
191        assert(size == sizeof(uint16_t));
192        vio.setQueueSelect(pkt->getLE<uint16_t>());
193        break;
194
195      case OFF_QUEUE_NOTIFY:
196        DPRINTF(VIOIface, "   WRITE QUEUE_NOTIFY\n");
197        assert(size == sizeof(uint16_t));
198        queueNotify = pkt->getLE<uint16_t>();
199        vio.onNotify(queueNotify);
200        break;
201
202      case OFF_DEVICE_STATUS: {
203          assert(size == sizeof(uint8_t));
204          uint8_t status(pkt->getLE<uint8_t>());
205          DPRINTF(VIOIface, "VirtIO set status: 0x%x\n", status);
206          vio.setDeviceStatus(status);
207      } break;
208
209      case OFF_ISR_STATUS:
210        warn("Guest tried to write ISR status.");
211        break;
212
213      default:
214        panic("Unhandled read offset (0x%x)\n", offset);
215    }
216
217    return 0;
218}
219
220void
221PciVirtIO::kick()
222{
223    DPRINTF(VIOIface, "kick(): Sending interrupt...\n");
224    interruptDeliveryPending = true;
225    intrPost();
226}
227
228PciVirtIO *
229PciVirtIOParams::create()
230{
231    return new PciVirtIO(this);
232}
233