Searched hist:2011 (Results 751 - 775 of 897) sorted by relevance

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/gem5/src/arch/x86/
H A Dtypes.hh8181:f789b9aac5f4 Sat Mar 26 09:23:00 EDT 2011 Korey Sewell <ksewell@umich.edu> mips: cleanup ISA-specific code
***
(1): get rid of expandForMT function
MIPS is the only ISA that cares about having a piece of ISA state integrate
multiple threads so add constants for MIPS and relieve the other ISAs from having
to define this. Also, InOrder was the only core that was actively calling
this function
* * *
(2): get rid of corespecific type
The CoreSpecific type was used as a proxy to pass in HW specific params to
a MIPS CPU, but since MIPS FS hasnt been touched for awhile, it makes sense
to not force every other ISA to use CoreSpecific as well use a special
reset function to set it. That probably should go in a PowerOn reset fault
anyway.
7971:1e9c54ee5fd0 Sun Feb 13 20:45:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Detect branches taking into account instruction size.

The size of the current instruction determines what the npc should be if
there's no branching.
7964:be8762db2561 Sun Feb 13 20:41:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Only reset npc to reflect instruction length once.

When redirecting fetch to handle branches, the npc of the current pc state
needs to be left alone. This change makes the pc state record whether or not
the npc already reflects a real value by making it keep track of the current
instruction size, or if no size has been set.
H A Dutility.cc8768:314eb1e2fa94 Sun Oct 30 03:33:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86: Get rid of more uses of FULL_SYSTEM.
8466:9c754e3022b7 Mon Jul 11 17:52:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> X86: implements copyRegs() function
This patch implements the copyRegs() function for the x86 architecture.
The patch assumes that no side effects other than TLB invalidation need
to be considered while copying the registers. This may not hold true in
future.
7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent.

Ran all the source files through 'perl -pi' with this script:

s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;

Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.
/gem5/src/arch/mips/isa/formats/
H A Dmem.isa8588:ef28ed90449d Tue Sep 27 02:48:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.

By using an underscore, the "." is still available and can unambiguously be
used to refer to members of a structure if an operand is a structure, class,
etc. This change mostly just replaces the appropriate "."s with "_"s, but
there were also a few places where the ISA descriptions where handling the
extensions themselves and had their own regular expressions to update. The
regular expressions in the isa parser were updated as well. It also now
looks for one of the defined type extensions specifically after connecting "_"
where before it would look for any sequence of characters after a "."
following an operand name and try to use it as the extension. This helps to
disambiguate cases where a "_" may legitimately be part of an operand name but
not separate the name from the type suffix.

Because leaving the "_" and suffix on the variable name still leaves a valid
C++ identifier and all extensions need to be consistent in a given context, I
considered leaving them on as a breadcrumb that would show what the intended
type was for that operand. Unfortunately the operands can be referred to in
code templates, the Mem operand in particular, and since the exact type of Mem
can be different for different uses of the same template, that broke things.
8564:f81bcb16fa1b Mon Sep 19 09:14:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> MIPS: Get rid of #if style config checks in the ISA description.
8442:b1f3dfae06f1 Sun Jul 03 01:34:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA: Use readBytes/writeBytes for all instruction level memory operations.
/gem5/src/cpu/checker/
H A Dcpu_impl.hh8793:5f25086326ac Fri Nov 18 04:33:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
/gem5/src/cpu/o3/
H A Dcomm.hh8503:479b186a4652 Sun Aug 14 20:41:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> O3: When squashing, restore the macroop that should be used for fetching.
8137:48371b9fb929 Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> O3: Cleanup the commitInfo comm struct.

Get rid of unused members and use base types rather than derrived values
where possible to limit amount of state.
7851:bb38f0c47ade Tue Jan 18 17:30:00 EST 2011 Matt Horsnell <Matt.Horsnell@arm.com> O3: Fix mispredicts from non control instructions.
The squash inside the fetch unit should not attempt to remove them from the
branch predictor as non-control instructions are not pushed into the predictor.
H A Drename.hh8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
7897:d9e8b1fd1a9f Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> mcpat: Adds McPAT performance counters

Updated patches from Rick Strong's set that modify performance counters for
McPAT
7813:7338bc628489 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Move sched_list.hh and timebuf.hh from src/base to src/cpu.
These files really aren't general enough to belong in src/base.
This patch doesn't reorder include lines, leaving them unsorted
in many cases, but Nate's magic script will fix that up shortly.
H A Drob_impl.hh8794:e2ac2b7164dd Fri Nov 18 05:20:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of includes of config/full_system.hh.
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
7897:d9e8b1fd1a9f Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> mcpat: Adds McPAT performance counters

Updated patches from Rick Strong's set that modify performance counters for
McPAT
H A Dlsq_impl.hh8793:5f25086326ac Fri Nov 18 04:33:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
8545:a3992291e230 Tue Sep 13 00:58:00 EDT 2011 Ali Saidi <saidi@eecs.umich.edu> LSQ: Only trigger a memory violation with a load/load if the value changes.

Only create a memory ordering violation when the value could have changed
between two subsequent loads, instead of just when loads go out-of-order
to the same address. While not very common in the case of Alpha, with
an architecture with a hardware table walker this can happen reasonably
frequently beacuse a translation will miss and start a table walk and
before the CPU re-schedules the faulting instruction another one will
pass it to the same address (or cache block depending on the dendency
checking).

This patch has been tested with a couple of self-checking hand crafted
programs to stress ordering between two cores.

The performance improvement on SPEC benchmarks can be substantial (2-10%).
8346:ce8b9a250021 Fri Jun 10 22:15:00 EDT 2011 Korey Sewell <ksewell@umich.edu> o3: missing newlines on some dprintfs
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
H A Dcpu.hh8794:e2ac2b7164dd Fri Nov 18 05:20:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of includes of config/full_system.hh.
8779:2a590c51adb1 Tue Nov 01 07:01:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Expose the same methods on the CPUs in SE and FS modes.
8777:dd43f1c9fa0a Mon Oct 31 05:58:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make the functions available from the TC consistent between SE and FS.
8627:86358c187837 Thu Dec 01 03:15:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> O3: Add stat that counts how many cycles the O3 cpu was quiesced.
8518:9c87727099ce Fri Aug 19 16:08:00 EDT 2011 Geoffrey Blake <geoffrey.blake@arm.com> Fix bugs due to interaction between SEV instructions and O3 pipeline

SEV instructions were originally implemented to cause asynchronous squashes
via the generateTCSquash() function in the O3 pipeline when updating the
SEV_MAILBOX miscReg. This caused race conditions between CPUs in an MP system
that would lead to a pipeline either going inactive indefinitely or not being
able to commit squashed instructions. Fixed SEV instructions to behave like
interrupts and cause synchronous sqaushes inside the pipeline, eliminating
the race conditions. Also fixed up the semantics of the WFE instruction to
behave as documented in the ARMv7 ISA description to not sleep if SEV_MAILBOX=1
or unmasked interrupts are pending.
8491:606cf2660887 Sun Aug 07 18:41:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> O3: Get rid of the unused addToRemoveList function.
8460:3893d9d2c6c2 Sun Jul 10 01:56:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> O3: Make sure fetch doesn't go off into the weeds during speculation.
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
7897:d9e8b1fd1a9f Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> mcpat: Adds McPAT performance counters

Updated patches from Rick Strong's set that modify performance counters for
McPAT
7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
H A Drename_impl.hh8794:e2ac2b7164dd Fri Nov 18 05:20:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of includes of config/full_system.hh.
8607:5fb918115c07 Mon Oct 31 04:09:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> GCC: Get everything working with gcc 4.6.1.

And by "everything" I mean all the quick regressions.
8471:18e560ba1539 Fri Jul 15 12:53:00 EDT 2011 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> O3: Create a pipeline activity viewer for the O3 CPU model.

Implemented a pipeline activity viewer as a python script (util/o3-pipeview.py)
and modified O3 code base to support an extra trace flag (O3PipeView) for
generating traces to be used as inputs by the tool.
8240:38befb82b2c9 Tue Apr 19 21:45:00 EDT 2011 Nathan Binkert <nate@binkert.org> stats: rename stats so they can be used as python expressions
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
7897:d9e8b1fd1a9f Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> mcpat: Adds McPAT performance counters

Updated patches from Rick Strong's set that modify performance counters for
McPAT
7854:3c6783497976 Tue Jan 18 17:30:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> O3: Don't try to scoreboard misc registers.

I'm not positive this is the correct fix, but it's working right now.
Either we need to do something like this, prevent the misc reg from being renamed at all,
or there something else going on. We need to find the root cause as to why
this is only a problem sometimes.
/gem5/src/python/m5/
H A D__init__.py8239:24406820a7e0 Tue Apr 19 14:13:00 EDT 2011 Nathan Binkert <nate@binkert.org> python: different import for dealing with demandimport
8234:a08c5fb4cd89 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> python: cleanup python code so stuff doesn't automatically happen at startup
this allows things to be overridden at startup (e.g. for tests)
8222:95fe5c720cfa Fri Apr 15 13:37:00 EDT 2011 Nathan Binkert <nate@binkert.org> python: figure out if the m5.internal package exists even with demandimport
/gem5/tests/configs/
H A Dmemtest-ruby.py8436:5648986156db Thu Jun 30 20:49:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com>, Nilay Vaish <nilay@cs.wisc.edu> Ruby: Add support for functional accesses
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.
8322:19949c6de823 Mon May 23 17:29:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> config: tweak ruby configs to clean up hierarchy

Re-enabling implicit parenting (see previous patch) causes current
Ruby config scripts to create some strange hierarchies and generate
several warnings. This patch makes three general changes to address
these issues.

1. The order of object creation in the ruby config files makes the L1
caches children of the sequencer rather than the controller; these
config ciles are rewritten to assign the L1 caches to the
controller first.

2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports
causes the sequencers to be children of system.ruby, generating
warnings because they are already parented to their respective
controllers. Changing this attribute to _cpu_ruby_ports fixes this
because the leading underscore means this is now treated as a plain
Python attribute rather than a child assignment. As a result, the
configuration hierarchy changes such that, e.g.,
system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer.

3. In the topology classes, the routers become children of some random
internal link node rather than direct children of the topology.
The topology classes are rewritten to assign the routers to the
topology object first.
7938:685719afafe6 Tue Feb 08 18:53:00 EST 2011 Brad Beckmann <Brad.Beckmann@amd.com> memtest: due to contention increase, increased deadlock threshold
/gem5/src/arch/mips/
H A Dutility.cc8794:e2ac2b7164dd Fri Nov 18 05:20:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of includes of config/full_system.hh.
8775:1e3ca5d77b53 Sun Oct 30 21:39:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in MIPS.
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/arch/alpha/linux/
H A Dsystem.cc8741:491297d019f3 Fri Sep 30 03:29:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Remove System::platform and Platform::intrFrequency.

In order for a system object to work in SE mode and FS mode, it has to either
always require a platform object even in SE mode, or get rid of the
requirement all together. Making SE mode carry around unnecessary/unused bits
of FS seems less than ideal, so I decided to go with the second option. The
platform pointer in the System class was used for exactly one purpose, a path
for the Alpha Linux system object to get to the real time clock and read its
frequency so that it could short cut the loops_per_jiffy calculation. There
was also a copy and pasted implementation in MIPS, but since it was only there
because it was there in Alpha I still count that as one use.

This change reverses the mechanism that communicates the RTC frequency so that
the Tsunami platform object pushes it up to the AlphaSystem object. This is
slightly less specific than it could be because really only the
AlphaLinuxSystem uses it. Because the intrFrequency function on the Platform
class was no longer necessary (and unimplemented on anything but Alpha) it was
eliminated.

After this change, a platform will need to have a system, but a system won't
have to have a platform.
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/base/loader/
H A Delf_object.cc8350:9fb150de362e Mon Jun 13 02:52:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Loader: Handle bad section names when loading an ELF file.

If there's a problem when reading the section names from a supposed ELF file,
this change makes gem5 print an error message as returned by libelf and die.
Previously these sorts of errors would make gem5 segfault when it tried to
access the section name through a NULL pointer.
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/arch/arm/
H A Dsystem.cc8299:64a938a8b7fc Fri May 13 18:27:00 EDT 2011 Chander Sudanthi <chander.sudanthi@arm.com> ARM: Better RealView/Versatile EB platform support.

Add registers and components to better support the VersatileEB board.
Made the MIDR and SYS_ID register parameters to ArmSystem and RealviewCtrl
respectively.
8286:abc8ab4ddd93 Wed May 04 21:38:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add support for loading the a bootloader and configuring parameters for it
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
H A Dtable_walker.hh8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
7946:7c58c106d28d Fri Feb 11 19:29:00 EST 2011 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> O3: Fix a few bugs in the TableWalker object.

Uncacheable requests were set as such only in atomic mode.
currState->delayed is checked in place of currState->timing for resetting
currState in atomic mode.
7878:d3e6ebcccabf Fri Feb 04 00:47:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.
/gem5/src/
H A DSConscript8614:2fc7787f47a9 Thu Nov 10 00:48:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> GCC: Guard some gcc flags so they're used when available and needed.
8607:5fb918115c07 Mon Oct 31 04:09:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> GCC: Get everything working with gcc 4.6.1.

And by "everything" I mean all the quick regressions.
8596:e6e22fa77883 Thu Oct 20 16:08:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> scons/swig: refactor some of the scons/SWIG code

- Move the random bits of SWIG code generation out of src/SConscript
file and into methods on the objects being wrapped.
- Cleaned up some variable naming and added some comments to make
the process a little clearer.
- Did a little generated file/module renaming:
- vptype_Foo now Foo_vector
- init_Foo is now Foo_init
This makes it easier to see all the Foo-related files in a
sorted directory listing.
- Made cxx_predecls and swig_predecls normal SimObject classmethods.
- Got rid of swig_objdecls hook, even though this breaks the System
objects get/setMemoryMode method exports. Will be fixing this in
a future changeset.
8594:0e77bd34385f Mon Oct 17 20:06:00 EDT 2011 Nathan Binkert <nate@binkert.org> scons: fix building of shared objects
8335:9228e00459d4 Thu Jun 02 20:36:00 EDT 2011 Nathan Binkert <nate@binkert.org> scons: rename TraceFlags to DebugFlags
8334:483e936f44f0 Thu Jun 02 20:36:00 EDT 2011 Nathan Binkert <nate@binkert.org> scons: rename some things from m5 to gem5

The default generated binary is now gem5.<type> instead of m5.<type>.
The latter does still work but gem5.<type> will be generated first and
then m5.<type> will be hard linked to it.
8333:c1a07ecb6619 Thu Jun 02 20:36:00 EDT 2011 Nathan Binkert <nate@binkert.org> copyright: Add code for finding all copyright blocks and create a COPYING file

The end of the COPYING file was generated with:
% python ./util/find_copyrights.py configs src system tests util

Update -C command line option to spit out COPYING file
8242:f52ece27e20d Wed Apr 20 14:14:00 EDT 2011 Brad Danofsky <bradley.danofsky@amd.com> scons: Allow the build directory live under an EXTRAS directory
8235:6381dc8bcfcc Fri Apr 15 13:45:00 EDT 2011 Nathan Binkert <nate@binkert.org> unittest: Make unit tests capable of using swig and python, convert stattest
8233:15b5ea80fd95 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> scons: make a flexible system for guarding source files
This is similar to guards on mercurial queues and they're used for selecting
which files are compiled into some given object. We already do something
similar, but it's mostly hard coded for the m5 binary and the m5 library
and I'd like to make it more flexible to better support the unittests
/gem5/src/arch/x86/isa/microops/
H A Dregop.isa8626:19eed0015983 Thu Dec 01 00:17:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Fix a bad segmentation check for the stack segment.
8588:ef28ed90449d Tue Sep 27 02:48:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.

By using an underscore, the "." is still available and can unambiguously be
used to refer to members of a structure if an operand is a structure, class,
etc. This change mostly just replaces the appropriate "."s with "_"s, but
there were also a few places where the ISA descriptions where handling the
extensions themselves and had their own regular expressions to update. The
regular expressions in the isa parser were updated as well. It also now
looks for one of the defined type extensions specifically after connecting "_"
where before it would look for any sequence of characters after a "."
following an operand name and try to use it as the extension. This helps to
disambiguate cases where a "_" may legitimately be part of an operand name but
not separate the name from the type suffix.

Because leaving the "_" and suffix on the variable name still leaves a valid
C++ identifier and all extensions need to be consistent in a given context, I
considered leaving them on as a breadcrumb that would show what the intended
type was for that operand. Unfortunately the operands can be referred to in
code templates, the Mem operand in particular, and since the exact type of Mem
can be different for different uses of the same template, that broke things.
7969:068f061e57a8 Sun Feb 13 20:45:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Put the result used for flags in an intermediate variable.

Using the destination register directly causes the ISA parser to treat it as a
source even if none of the original bits are used.
7967:b243dc8cec8b Sun Feb 13 20:44:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Don't read in dest regs if all bits are replaced.

In x86, 32 and 64 bit writes to registers in which registers appear to be 32 or
64 bits wide overwrite all bits of the destination register. This change
removes false dependencies in these cases where the previous value of a
register doesn't need to be read to write a new value. New versions of most
microops are created that have a "Big" suffix which simply overwrite their
destination, and the right version to use is selected during microop
allocation based on the selected data size.

This does not change the performance of the O3 CPU model significantly, I
assume because there are other false dependencies from the condition code bits
in the flags register.
7894:48d31b577847 Mon Feb 07 01:14:00 EST 2011 Brad Beckmann <Brad.Beckmann@amd.com> x86: set IsCondControl flag for the appropriate microops
/gem5/src/cpu/
H A Dexetrace.cc8793:5f25086326ac Fri Nov 18 04:33:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
8300:eb279d6e08a2 Fri May 13 18:27:00 EDT 2011 Chander Sudanthi <chander.sudanthi@arm.com> Trace: Allow printing ASIDs and selectively tracing based on user/kernel code.

Debug flags are ExecUser, ExecKernel, and ExecAsid. ExecUser and
ExecKernel are set by default when Exec is specified. Use minus
sign with ExecUser or ExecKernel to remove user or kernel tracing
respectively.
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent.

Ran all the source files through 'perl -pi' with this script:

s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;

Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.
H A Dbase_dyn_inst.hh8794:e2ac2b7164dd Fri Nov 18 05:20:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of includes of config/full_system.hh.
8545:a3992291e230 Tue Sep 13 00:58:00 EDT 2011 Ali Saidi <saidi@eecs.umich.edu> LSQ: Only trigger a memory violation with a load/load if the value changes.

Only create a memory ordering violation when the value could have changed
between two subsequent loads, instead of just when loads go out-of-order
to the same address. While not very common in the case of Alpha, with
an architecture with a hardware table walker this can happen reasonably
frequently beacuse a translation will miss and start a table walk and
before the CPU re-schedules the faulting instruction another one will
pass it to the same address (or cache block depending on the dendency
checking).

This patch has been tested with a couple of self-checking hand crafted
programs to stress ordering between two cores.

The performance improvement on SPEC benchmarks can be substantial (2-10%).
8542:7230ff0738e3 Fri Sep 09 05:40:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> StaticInst: Merge StaticInst and StaticInstBase.

Having two StaticInst classes, one nominally ISA dependent and the other ISA
dependent, has not been historically useful and makes the StaticInst class
more complicated that it needs to be. This change merges StaticInstBase into
StaticInst.
8502:f1fc7102c970 Sun Aug 14 07:08:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> O3: Add a pointer to the macroop for a microop in the dyninst.
8486:c4e77a9563f5 Sun Aug 07 12:21:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Translation: Use a pointer type as the template argument.

This allows regular pointers and reference counted pointers without having to
use any shim structures or other tricks.
8484:3c641509bf3e Tue Aug 02 14:51:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> O3: Get rid of the raw ExtMachInst constructor on DynInsts.

This constructor assumes that the ExtMachInst can be decoded directly into a
StaticInst that's useful to execute. With the advent of microcoded
instructions that's no longer true.
8444:56de1f9320df Sun Jul 03 01:35:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.

readBytes and writeBytes had the word "bytes" in their names because they
accessed blobs of bytes. This distinguished them from the read and write
functions which handled higher level data types. Because those functions don't
exist any more, this change renames readBytes and writeBytes to more general
names, readMem and writeMem, which reflect the fact that they are how you read
and write memory. This also makes their names more consistent with the
register reading/writing functions, although those are still read and set for
some reason.
8443:530ff1bc8d70 Sun Jul 03 01:34:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ExecContext: Get rid of the now unused read/write templated functions.
8201:89221928d131 Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> CPU: Remove references to memory copy operations
8199:3d6c08c877a9 Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> O3: Tighten memory order violation checking to 16 bytes.

The comment in the code suggests that the checking granularity should be 16
bytes, however in reality the shift by 8 is 256 bytes which seems much
larger than required.
H A Dthread_context.hh8777:dd43f1c9fa0a Mon Oct 31 05:58:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make the functions available from the TC consistent between SE and FS.
8767:e575781f71b8 Sun Oct 30 03:33:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make getProcessPtr available in both modes, and get rid of FULL_SYSTEMs.
8764:e4660687c49f Sun Oct 16 08:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Include getMemPort in FS.
8761:20322354b80b Sun Oct 16 08:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build/expose vport in SE mode.
8754:0996451df6de Sun Oct 16 05:59:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> CPU: Make physPort and getPhysPort available in SE mode.
8541:27aaee8ec7cc Fri Sep 09 05:30:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Decode: Pull instruction decoding out of the StaticInst class into its own.

This change pulls the instruction decoding machinery (including caches) out of
the StaticInst class and puts it into its own class. This has a few intrinsic
benefits. First, the StaticInst code, which has gotten to be quite large, gets
simpler. Second, the code that handles decode caching is now separated out
into its own component and can be looked at in isolation, making it easier to
understand. I took the opportunity to restructure the code a bit which will
hopefully also help.

Beyond that, this change also lays some ground work for each ISA to have its
own, potentially stateful decode object. We'd be able to include less
contextualizing information in the ExtMachInst objects since that context
would be applied at the decoder. Also, the decoder could "know" ahead of time
that all the instructions it's going to see are going to be, for instance, 64
bit mode, and it will have one less thing to check when it decodes them.
Because the decode caching mechanism has been separated out, it's now possible
to have multiple caches which correspond to different types of decoding
context. Having one cache for each element of the cross product of different
configurations may become prohibitive, so it may be desirable to clear out the
cache when relatively static state changes and not to have one for each
setting.

Because the decode function is no longer universally accessible as a static
member of the StaticInst class, a new function was added to the ThreadContexts
that returns the applicable decode object.
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/arch/x86/isa/decoder/
H A Dtwo_byte_opcodes.isa8738:66bf413b0d5b Fri Sep 30 03:27:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Use the new FullSystem constant where possible.
8558:a2f497ff53e4 Mon Sep 19 05:53:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86: Don't use "#if FULL_SYSTEM" in the X86 ISA description.

The decoder now checks the value of FULL_SYSTEM in a switch statement to
decide whether to return a real syscall instruction or one that triggers
syscall emulation (or a panic in FS mode). The switch statement should devolve
into an if, and also should be optimized out since it's based on constant
input.
8556:2afd82e84d95 Mon Sep 19 05:40:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts.
8555:6fd8d0432d8d Mon Sep 19 02:26:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Pseudoinst: Add an initParam pseudo inst function.
7914:eee5bb0fb8ea Mon Feb 07 01:14:00 EST 2011 Brad Beckmann <Brad.Beckmann@amd.com> m5: added work completed monitoring support
/gem5/src/cpu/simple/
H A Dtiming.hh8444:56de1f9320df Sun Jul 03 01:35:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.

readBytes and writeBytes had the word "bytes" in their names because they
accessed blobs of bytes. This distinguished them from the read and write
functions which handled higher level data types. Because those functions don't
exist any more, this change renames readBytes and writeBytes to more general
names, readMem and writeMem, which reflect the fact that they are how you read
and write memory. This also makes their names more consistent with the
register reading/writing functions, although those are still read and set for
some reason.
8443:530ff1bc8d70 Sun Jul 03 01:34:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ExecContext: Get rid of the now unused read/write templated functions.
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
7945:32758425de8c Fri Feb 11 19:29:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> SimpleCPU: Fix a case where a DTLB fault redirects fetch and an I-side walk occurs.

This change fixes an issue where a DTLB fault occurs and redirects fetch to
handle the fault and the ITLB requires a walk which delays translation. In this
case the status of the cpu isn't updated appropriately, and an additional
instruction fetch occurs. Eventually this hits an assert as multiple instruction
fetches are occuring in the system and when the second one returns the
processor is in the wrong state.

Some asserts below are removed because it was always true (typo) and the state
after the initiateAcc() the processor could be in any valid state when a
d-side fault occurs.
7944:1daf51f62013 Fri Feb 11 19:29:00 EST 2011 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> O3: Enhance data address translation by supporting hardware page table walkers.

Some ISAs (like ARM) relies on hardware page table walkers. For those ISAs,
when a TLB miss occurs, initiateTranslation() can return with NoFault but with
the translation unfinished.

Instructions experiencing a delayed translation due to a hardware page table
walk are deferred until the translation completes and kept into the IQ. In
order to keep track of them, the IQ has been augmented with a queue of the
outstanding delayed memory instructions. When their translation completes,
instructions are re-executed (only their initiateAccess() was already
executed; their DTB translation is now skipped). The IEW stage has been
modified to support such a 2-pass execution.
/gem5/configs/example/
H A Dse.py8482:353abb676fa2 Tue Aug 02 01:10:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Scons: Drop RUBY as compile time option.
This patch drops RUBY as a compile time option. Instead the PROTOCOL option
is used to figure out whether or not to build Ruby. If the specified protocol
is 'None', then Ruby is not compiled.
8467:82ff928182c5 Mon Jul 11 20:57:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> se.py: Fixes the way ruby's options are added
8436:5648986156db Thu Jun 30 20:49:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com>, Nilay Vaish <nilay@cs.wisc.edu> Ruby: Add support for functional accesses
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.
8322:19949c6de823 Mon May 23 17:29:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> config: tweak ruby configs to clean up hierarchy

Re-enabling implicit parenting (see previous patch) causes current
Ruby config scripts to create some strange hierarchies and generate
several warnings. This patch makes three general changes to address
these issues.

1. The order of object creation in the ruby config files makes the L1
caches children of the sequencer rather than the controller; these
config ciles are rewritten to assign the L1 caches to the
controller first.

2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports
causes the sequencers to be children of system.ruby, generating
warnings because they are already parented to their respective
controllers. Changing this attribute to _cpu_ruby_ports fixes this
because the leading underscore means this is now treated as a plain
Python attribute rather than a child assignment. As a result, the
configuration hierarchy changes such that, e.g.,
system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer.

3. In the topology classes, the routers become children of some random
internal link node rather than direct children of the topology.
The topology classes are rewritten to assign the routers to the
topology object first.
8169:89cd8302abd3 Sun Mar 20 00:13:00 EDT 2011 Lisa Hsu <Lisa.Hsu@amd.com> configs: combine ruby_se.py and se.py to avoid all that code duplication
8168:5cbb0a68dce1 Sun Mar 20 00:13:00 EDT 2011 Lisa Hsu <Lisa.Hsu@amd.com> enable x86 workloads on se.py
8167:f596091c854d Sun Mar 20 00:12:00 EDT 2011 Lisa Hsu <Lisa.Hsu@amd.com> se.py: Modify script to make multiprogramming much easier.
Now, instead of --bench benchname, you can do --bench bench1-bench2-bench3 and it will
set up a simulation that instantiates those three workloads. Only caveat is that now,
for sanity checking, your -n X must match the number of benches in the list.

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