Searched hist:2011 (Results 501 - 525 of 897) sorted by relevance

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/gem5/src/arch/generic/
H A Dmemhelpers.hh8444:56de1f9320df Sun Jul 03 01:35:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.

readBytes and writeBytes had the word "bytes" in their names because they
accessed blobs of bytes. This distinguished them from the read and write
functions which handled higher level data types. Because those functions don't
exist any more, this change renames readBytes and writeBytes to more general
names, readMem and writeMem, which reflect the fact that they are how you read
and write memory. This also makes their names more consistent with the
register reading/writing functions, although those are still read and set for
some reason.
8442:b1f3dfae06f1 Sun Jul 03 01:34:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA: Use readBytes/writeBytes for all instruction level memory operations.
/gem5/src/sim/
H A Dfaults.cc8784:05fb20d7064b Wed Nov 02 05:11:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in sim.
8589:d0772caaeacd Tue Sep 27 03:16:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Faults: Make the generic faults more consistent between SE and FS.

All of the classes will now be available in both modes, and only
GenericPageTableFault will continue to check the mode for conditional
compilation. It uses a process object to handle the fault in SE mode, and
for now those aren't available in FS mode.
8545:a3992291e230 Tue Sep 13 00:58:00 EDT 2011 Ali Saidi <saidi@eecs.umich.edu> LSQ: Only trigger a memory violation with a load/load if the value changes.

Only create a memory ordering violation when the value could have changed
between two subsequent loads, instead of just when loads go out-of-order
to the same address. While not very common in the case of Alpha, with
an architecture with a hardware table walker this can happen reasonably
frequently beacuse a translation will miss and start a table walk and
before the CPU re-schedules the faulting instruction another one will
pass it to the same address (or cache block depending on the dendency
checking).

This patch has been tested with a couple of self-checking hand crafted
programs to stress ordering between two cores.

The performance improvement on SPEC benchmarks can be substantial (2-10%).
8539:7d3ea3c65c66 Fri Sep 09 04:01:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Stack: Tidy up some comments, a warning, and make stack extension consistent.

Do some minor cleanup of some recently added comments, a warning, and change
other instances of stack extension to be like what's now being done for x86.
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/cpu/o3/
H A DO3CPU.py8793:5f25086326ac Fri Nov 18 04:33:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
8631:8c038d4cd210 Thu Dec 01 03:15:00 EST 2011 Chander Sudanthi <chander.sudanthi@arm.com> O3: Remove hardcoded tgts_per_mshr in O3CPU.py.

There are two lines in O3CPU.py that set the dcache and icache
tgts_per_mshr to 20, ignoring any pre-configured value of tgts_per_mshr.
This patch removes these hardcoded lines from O3CPU.py and sets the default
L1 cache mshr targets to 20.
8519:ef35ce2bd73f Fri Aug 19 16:08:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.

This patch improves performance by as much as 10% on some spec benchmarks.
8199:3d6c08c877a9 Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> O3: Tighten memory order violation checking to 16 bytes.

The comment in the code suggests that the checking granularity should be 16
bytes, however in reality the shift by 8 is 256 bytes which seems much
larger than required.
7876:189b9b258779 Thu Feb 03 23:23:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Config: Keep track of uncached and cached ports separately.

This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.
7868:6029008db669 Tue Feb 01 21:28:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Add L1 caches for the TLB walkers.

Small L1 caches are connected to the TLB walkers when caches are used. This
allows them to participate in the coherence protocol properly.
H A Dfetch_impl.hh8793:5f25086326ac Fri Nov 18 04:33:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
8641:4d3ecac1abec Tue Dec 13 14:49:00 EST 2011 Nathan Binkert <nate@binkert.org> gcc: fix unused variable warnings from GCC 4.6.1
8541:27aaee8ec7cc Fri Sep 09 05:30:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Decode: Pull instruction decoding out of the StaticInst class into its own.

This change pulls the instruction decoding machinery (including caches) out of
the StaticInst class and puts it into its own class. This has a few intrinsic
benefits. First, the StaticInst code, which has gotten to be quite large, gets
simpler. Second, the code that handles decode caching is now separated out
into its own component and can be looked at in isolation, making it easier to
understand. I took the opportunity to restructure the code a bit which will
hopefully also help.

Beyond that, this change also lays some ground work for each ISA to have its
own, potentially stateful decode object. We'd be able to include less
contextualizing information in the ExtMachInst objects since that context
would be applied at the decoder. Also, the decoder could "know" ahead of time
that all the instructions it's going to see are going to be, for instance, 64
bit mode, and it will have one less thing to check when it decodes them.
Because the decode caching mechanism has been separated out, it's now possible
to have multiple caches which correspond to different types of decoding
context. Having one cache for each element of the cross product of different
configurations may become prohibitive, so it may be desirable to clear out the
cache when relatively static state changes and not to have one for each
setting.

Because the decode function is no longer universally accessible as a static
member of the StaticInst class, a new function was added to the ThreadContexts
that returns the applicable decode object.
8503:479b186a4652 Sun Aug 14 20:41:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> O3: When squashing, restore the macroop that should be used for fetching.
8502:f1fc7102c970 Sun Aug 14 07:08:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> O3: Add a pointer to the macroop for a microop in the dyninst.
8499:e5f14b00c0ae Sat Aug 13 16:36:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> O3: At the end of an instruction, force fetchAddr to something sensible.

It's possible (though until now very unlikely) for fetchAddr to get out of
sync with the actual PC of the current instruction. This change forcefull
resets fetchAddr at the end of every instruction.
8495:6ee3a2359fcb Tue Aug 09 14:30:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> O3: Stop using the current macroop no matter why you're leaving it.

Until now, the only reason a macroop would be left was because it ended at a
microop marked as the last microop. In O3 with branch prediction, it's
possible for the branch predictor to have entries which originally came from
different instructions which happened to have the same RIP. This could
theoretically happen in many ways, but it was encountered specifically when
different programs in different address spaces ran one after the other in
X86_FS.

What would happen in that case was that the macroop would continue to be
looped over and microops fetched from it until it reached the last microop
even though the macropc had moved out from under it. If things lined up
properly, this could mean that the end bytes of an instruction actually fell
into the instruction sized block of memory after the one in the predecoder.
The fetch loop implicitly assumes that the last instruction sized chunk of
memory processed was the last one needed for the instruction it just finished
executing. It would then tell the predecoder to move to an offset within the
bytes it was given that is larger than those bytes, and that would trip an
assert in the x86 predecoder.

This change fixes this problem by making fetch stop processing the current
macroop if the address it should be fetching from changed when the PC is
updated. That happens when the last microop was reached because the instruction
handled it properly, and it also catches the case where the branch predictor
makes fetch do a macro level branch when it shouldn't.

The check of isLastMicroop is retained because otherwise, a macroop that
branches back to itself would act like a single, long macroop instead of
multiple instances of the same microop. There may be situations (which may
turn out to be purely hypothetical) where that matters.

This also fixes a relatively minor issue where the curMacroop variable would
be set to NULL immediately after seeing that a microop was the last one before
curMacroop was used to build the dyninst. The traceData structure would have a
NULL pointer to the macroop for that microop.
8479:e68b1ad09c6b Sun Jul 31 02:22:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> O3: Fix corner case squashing into the microcode ROM.

When fetching from the microcode ROM, if the PC is set so that it isn't in the
cache block that's been fetched the CPU will get stuck. The fetch stage
notices that it's in the ROM so it doesn't try to fetch from the current PC.
It then later notices that it's outside of the current cache block so it skips
generating instructions expecting to continue once the right bytes have been
fetched. This change lets the fetch stage attempt to generate instructions,
and only checks if the bytes it's going to use are valid if it's really going
to use them.
8471:18e560ba1539 Fri Jul 15 12:53:00 EDT 2011 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> O3: Create a pipeline activity viewer for the O3 CPU model.

Implemented a pipeline activity viewer as a python script (util/o3-pipeview.py)
and modified O3 code base to support an extra trace flag (O3PipeView) for
generating traces to be used as inputs by the tool.
8462:80492ae5148e Sun Jul 10 01:56:00 EDT 2011 Geoffrey Blake <geoffrey.blake@arm.com O3: Fix up pipelining icache accesses in fetch stage to function properly

Fixed up the patch from Yasuko Watanabe that enabled pipelining of fetch accessess to
icache to work with recent changes to main repository.
Also added in ability for fetch stage to delay issuing the fault carrying
nop when a pipeline fetch causes a fault and no fetch bandwidth is available
until the next cycle.
H A Ddyn_inst.hh8779:2a590c51adb1 Tue Nov 01 07:01:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Expose the same methods on the CPUs in SE and FS modes.
8557:f44572edfba3 Mon Sep 19 05:46:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Syscall: Make the syscall function available in both SE and FS modes.

In FS mode the syscall function will panic, but the interface will be
consistent and code which calls syscall can be compiled in. This will allow,
for instance, instructions that use syscall to be built unconditionally but
then not returned by the decoder.
8502:f1fc7102c970 Sun Aug 14 07:08:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> O3: Add a pointer to the macroop for a microop in the dyninst.
8484:3c641509bf3e Tue Aug 02 14:51:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> O3: Get rid of the raw ExtMachInst constructor on DynInsts.

This constructor assumes that the ExtMachInst can be decoded directly into a
StaticInst that's useful to execute. With the advent of microcoded
instructions that's no longer true.
8471:18e560ba1539 Fri Jul 15 12:53:00 EDT 2011 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> O3: Create a pipeline activity viewer for the O3 CPU model.

Implemented a pipeline activity viewer as a python script (util/o3-pipeview.py)
and modified O3 code base to support an extra trace flag (O3PipeView) for
generating traces to be used as inputs by the tool.
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
7848:cc5e64f8423f Tue Jan 18 17:30:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add support for moving predicated false dest operands from sources.
H A Dcommit_impl.hh8793:5f25086326ac Fri Nov 18 04:33:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
8581:56f97760eadd Thu Sep 22 21:59:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> event: minor cleanup
Initialize flags via the Event constructor instead of calling
setFlags() in the body of the derived class's constructor. I
forget exactly why, but this made life easier when implementing
multi-queue support.

Also rename Event::getFlags() to isFlagSet() to better match
common usage, and get rid of some unused Event methods.
8518:9c87727099ce Fri Aug 19 16:08:00 EDT 2011 Geoffrey Blake <geoffrey.blake@arm.com> Fix bugs due to interaction between SEV instructions and O3 pipeline

SEV instructions were originally implemented to cause asynchronous squashes
via the generateTCSquash() function in the O3 pipeline when updating the
SEV_MAILBOX miscReg. This caused race conditions between CPUs in an MP system
that would lead to a pipeline either going inactive indefinitely or not being
able to commit squashed instructions. Fixed SEV instructions to behave like
interrupts and cause synchronous sqaushes inside the pipeline, eliminating
the race conditions. Also fixed up the semantics of the WFE instruction to
behave as documented in the ARMv7 ISA description to not sleep if SEV_MAILBOX=1
or unmasked interrupts are pending.
8516:a9c0d2ab490a Fri Aug 19 16:08:00 EDT 2011 Mrinmoy Ghosh <Mrinmoy.Ghosh@arm.com> LSQ: Add some better dprintfs for storeset predictor.
8493:0eca041a8c06 Tue Aug 09 06:37:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> O3: When waiting to handle an interrupt, let everything drain out.

Before this change, the commit stage would wait until the ROB and store queue
were empty before recognizing an interrupt. The fetch stage would stop
generating instructions at an appropriate point, so commit would then wait
until a valid time to interrupt the instruction stream. Instructions might be
in flight after fetch but not the in the ROB or store queue (in rename, for
instance), so this change makes commit wait until all in flight instructions
are finished.
8471:18e560ba1539 Fri Jul 15 12:53:00 EDT 2011 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> O3: Create a pipeline activity viewer for the O3 CPU model.

Implemented a pipeline activity viewer as a python script (util/o3-pipeview.py)
and modified O3 code base to support an extra trace flag (O3PipeView) for
generating traces to be used as inputs by the tool.
8346:ce8b9a250021 Fri Jun 10 22:15:00 EDT 2011 Korey Sewell <ksewell@umich.edu> o3: missing newlines on some dprintfs
8240:38befb82b2c9 Tue Apr 19 21:45:00 EDT 2011 Nathan Binkert <nate@binkert.org> stats: rename stats so they can be used as python expressions
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8230:845c8eb5ac49 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: fix up code after sorting
/gem5/src/cpu/
H A Dbase_dyn_inst_impl.hh8545:a3992291e230 Tue Sep 13 00:58:00 EDT 2011 Ali Saidi <saidi@eecs.umich.edu> LSQ: Only trigger a memory violation with a load/load if the value changes.

Only create a memory ordering violation when the value could have changed
between two subsequent loads, instead of just when loads go out-of-order
to the same address. While not very common in the case of Alpha, with
an architecture with a hardware table walker this can happen reasonably
frequently beacuse a translation will miss and start a table walk and
before the CPU re-schedules the faulting instruction another one will
pass it to the same address (or cache block depending on the dendency
checking).

This patch has been tested with a couple of self-checking hand crafted
programs to stress ordering between two cores.

The performance improvement on SPEC benchmarks can be substantial (2-10%).
8502:f1fc7102c970 Sun Aug 14 07:08:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> O3: Add a pointer to the macroop for a microop in the dyninst.
8484:3c641509bf3e Tue Aug 02 14:51:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> O3: Get rid of the raw ExtMachInst constructor on DynInsts.

This constructor assumes that the ExtMachInst can be decoded directly into a
StaticInst that's useful to execute. With the advent of microcoded
instructions that's no longer true.
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
7944:1daf51f62013 Fri Feb 11 19:29:00 EST 2011 Giacomo Gabrielli <Giacomo.Gabrielli@arm.com> O3: Enhance data address translation by supporting hardware page table walkers.

Some ISAs (like ARM) relies on hardware page table walkers. For those ISAs,
when a TLB miss occurs, initiateTranslation() can return with NoFault but with
the translation unfinished.

Instructions experiencing a delayed translation due to a hardware page table
walk are deferred until the translation completes and kept into the IQ. In
order to keep track of them, the IQ has been augmented with a queue of the
outstanding delayed memory instructions. When their translation completes,
instructions are re-executed (only their initiateAccess() was already
executed; their DTB translation is now skipped). The IEW stage has been
modified to support such a 2-pass execution.
H A Dthread_state.cc8793:5f25086326ac Fri Nov 18 04:33:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
8777:dd43f1c9fa0a Mon Oct 31 05:58:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Make the functions available from the TC consistent between SE and FS.
8766:b0773af78423 Sun Oct 30 03:32:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build the base process class in FS.
8764:e4660687c49f Sun Oct 16 08:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Include getMemPort in FS.
8761:20322354b80b Sun Oct 16 08:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build/expose vport in SE mode.
8754:0996451df6de Sun Oct 16 05:59:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> CPU: Make physPort and getPhysPort available in SE mode.
H A DBaseCPU.py8793:5f25086326ac Fri Nov 18 04:33:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in the CPU directory.
8784:05fb20d7064b Wed Nov 02 05:11:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of FULL_SYSTEM in sim.
8756:cce8cf3906ca Sun Oct 16 08:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ARM: Turn on the page table walker on ARM in SE mode.
8752:28e899b7dee3 Thu Oct 13 05:22:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86: Turn on the page table walker in SE mode.
8745:575cab0db076 Sun Oct 09 03:15:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build the Interrupt objects in SE mode.
8629:e3cb8e20a9b4 Thu Dec 01 03:15:00 EST 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add support for having a TLB cache.
8181:f789b9aac5f4 Sat Mar 26 09:23:00 EDT 2011 Korey Sewell <ksewell@umich.edu> mips: cleanup ISA-specific code
***
(1): get rid of expandForMT function
MIPS is the only ISA that cares about having a piece of ISA state integrate
multiple threads so add constants for MIPS and relieve the other ISAs from having
to define this. Also, InOrder was the only core that was actively calling
this function
* * *
(2): get rid of corespecific type
The CoreSpecific type was used as a proxy to pass in HW specific params to
a MIPS CPU, but since MIPS FS hasnt been touched for awhile, it makes sense
to not force every other ISA to use CoreSpecific as well use a special
reset function to set it. That probably should go in a PowerOn reset fault
anyway.
7897:d9e8b1fd1a9f Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> mcpat: Adds McPAT performance counters

Updated patches from Rick Strong's set that modify performance counters for
McPAT
7876:189b9b258779 Thu Feb 03 23:23:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Config: Keep track of uncached and cached ports separately.

This makes sure that the address ranges requested for caches and uncached ports
don't conflict with each other, and that accesses which are always uncached
(message signaled interrupts for instance) don't waste time passing through
caches.
7868:6029008db669 Tue Feb 01 21:28:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> X86: Add L1 caches for the TLB walkers.

Small L1 caches are connected to the TLB walkers when caches are used. This
allows them to participate in the coherence protocol properly.
/gem5/src/mem/ruby/profiler/
H A DProfiler.cc8485:7a9a7f2a3d46 Wed Aug 03 19:25:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Remove files and includes not in use
8436:5648986156db Thu Jun 30 20:49:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com>, Nilay Vaish <nilay@cs.wisc.edu> Ruby: Add support for functional accesses
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
8174:e21f6e70169e Tue Mar 22 07:41:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Remove CacheMsg class from SLICC
The goal of the patch is to do away with the CacheMsg class currently in use
in coherence protocols. In place of CacheMsg, the RubyRequest class will used.
This class is already present in slicc_interface/RubyRequest.hh. In fact,
objects of class CacheMsg are generated by copying values from a RubyRequest
object.
8165:5955406f7ed0 Sat Mar 19 19:34:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Convert CacheRequestType to RubyRequestType
This patch converts CacheRequestType to RubyRequestType so that both the
protocol dependent and independent code makes use of the same request type.
7832:de7601e6e19d Mon Jan 10 14:11:00 EST 2011 Nathan Binkert <nate@binkert.org> ruby: get rid of ruby's Debug.hh

Get rid of the Debug class
Get rid of ASSERT and use assert
Use DPRINTFR for ProtocolTrace
/gem5/src/mem/slicc/symbols/
H A DType.py8608:02d7ac5fb855 Thu Nov 03 23:46:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Remove some unused typedefs
This patch removes some of the unused typedefs. It also moves
some of the typedefs from Global.hh to TypeDefines.hh. The patch
also eliminates the file NodeID.hh.
8602:836f8fad4a4c Fri Oct 28 14:00:00 EDT 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Reorganize mapping of components
In RubySlicc_ComponentMapping.hh, certain '#define's have been used for
mapping MachineType to GenericMachineType. These '#define's are being
eliminated and the code will now be generated by SLICC instead. Also
are being eliminated some of the unused functions from
RubySlicc_ComponentMapping.sm.
8266:66a3187a6714 Mon May 02 00:16:00 EDT 2011 Korey Sewell <ksewell@umich.edu> ruby: dbg: use system ticks instead of cycles
8188:20dbef14192d Thu Mar 31 20:17:00 EDT 2011 Lisa Hsu <Lisa.Hsu@amd.com> Ruby: pass Packet->Req->contextId() to Ruby.
It is useful for Ruby to understand from whence request packets came.
This has all request packets going into Ruby pass the contextId value, if
it exists. This supplants the old libruby proc_id value passed around in
all the Messages, so I've also removed the unused unsigned proc_id; member
generated by SLICC for all Message types.
8086:bf0335d98250 Wed Feb 23 19:41:00 EST 2011 Brad Beckmann <Brad.Beckmann@amd.com> ruby: automate permission setting

This patch integrates permissions with cache and memory states, and then
automates the setting of permissions within the generated code. No longer
does one need to manually set the permissions within the setState funciton.
This patch will faciliate easier functional access support by always correctly
setting permissions for both cache and memory states.
7832:de7601e6e19d Mon Jan 10 14:11:00 EST 2011 Nathan Binkert <nate@binkert.org> ruby: get rid of ruby's Debug.hh

Get rid of the Debug class
Get rid of ASSERT and use assert
Use DPRINTFR for ProtocolTrace
/gem5/src/arch/mips/isa/
H A Ddecoder.isa8738:66bf413b0d5b Fri Sep 30 03:27:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Use the new FullSystem constant where possible.
8607:5fb918115c07 Mon Oct 31 04:09:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> GCC: Get everything working with gcc 4.6.1.

And by "everything" I mean all the quick regressions.
8588:ef28ed90449d Tue Sep 27 02:48:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.

By using an underscore, the "." is still available and can unambiguously be
used to refer to members of a structure if an operand is a structure, class,
etc. This change mostly just replaces the appropriate "."s with "_"s, but
there were also a few places where the ISA descriptions where handling the
extensions themselves and had their own regular expressions to update. The
regular expressions in the isa parser were updated as well. It also now
looks for one of the defined type extensions specifically after connecting "_"
where before it would look for any sequence of characters after a "."
following an operand name and try to use it as the extension. This helps to
disambiguate cases where a "_" may legitimately be part of an operand name but
not separate the name from the type suffix.

Because leaving the "_" and suffix on the variable name still leaves a valid
C++ identifier and all extensions need to be consistent in a given context, I
considered leaving them on as a breadcrumb that would show what the intended
type was for that operand. Unfortunately the operands can be referred to in
code templates, the Mem operand in particular, and since the exact type of Mem
can be different for different uses of the same template, that broke things.
8568:83f728db3332 Mon Sep 19 09:17:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> MIPS: Get rid of cruft in the fault classes.

Get rid of Fault classes left over from when this file was copied from Alpha,
and rename ArithmeticOverflowFault to be IntegerOverflowFault and get rid of
the old IntegerOverflowFault stub. The Integer version is what's actually in
the manual, but the Arithmetic version had the implementation.
8564:f81bcb16fa1b Mon Sep 19 09:14:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> MIPS: Get rid of #if style config checks in the ISA description.
8433:c6ebf7c6dcac Wed Jun 22 23:35:00 EDT 2011 Deyaun Guo <guodeyuan@tsinghua.org.cn> mips: fix nmsub and nmadd definitions
the -/+ signs were flipped for nmsub_s, nmsub_d, and nmadd_d
7952:896a68fc68dc Sat Feb 12 10:14:00 EST 2011 Korey Sewell <ksewell@umich.edu> inorder: remove unused isa ops
pass/fail ops were used for testing but arent part of isa
/gem5/src/mem/ruby/system/
H A DRubyPort.hh8615:e66a566f2cfa Mon Nov 14 18:44:00 EST 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Process packet instead of RubyRequest in Sequencer
This patch changes the implementation of Ruby's recvTiming() function so
that it pushes a packet in to the Sequencer instead of a RubyRequest. This
requires changes in the Sequencer's makeRequest() and issueRequest()
functions, as they also need to operate on a Packet instead of RubyRequest.
8436:5648986156db Thu Jun 30 20:49:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com>, Nilay Vaish <nilay@cs.wisc.edu> Ruby: Add support for functional accesses
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
8092:6782b51ae8a8 Fri Feb 25 18:54:00 EST 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Remove libruby
This patch removes libruby_internal.hh, libruby.hh and libruby.cc. It moves
the contents to libruby.hh to RubyRequest.hh and RubyRequest.cc files.
7915:bc39c93a5519 Mon Feb 07 01:14:00 EST 2011 Brad Beckmann <Brad.Beckmann@amd.com> mem: Added support for Null data packet

The packet now identifies whether static or dynamic data has been allocated and
is used by Ruby to determine whehter to copy the data pointer into the ruby
request. Subsequently, Ruby can be told not to update phys memory when
receiving packets.
7910:8a92b39be50e Mon Feb 07 01:14:00 EST 2011 Brad Beckmann <Brad.Beckmann@amd.com> ruby: Fix RubyPort to properly handle retrys
7909:eee578ed2130 Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> Ruby: Fix to return cache block size to CPU for split data transfers
/gem5/src/mem/
H A DSConscript8763:509e9bb84dfa Sun Oct 16 08:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Turn on the page table class in FS.
8762:c77d9ef26d2b Sun Oct 16 08:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build in the tport in FS mode.
8761:20322354b80b Sun Oct 16 08:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build/expose vport in SE mode.
8615:e66a566f2cfa Mon Nov 14 18:44:00 EST 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Process packet instead of RubyRequest in Sequencer
This patch changes the implementation of Ruby's recvTiming() function so
that it pushes a packet in to the Sequencer instead of a RubyRequest. This
requires changes in the Sequencer's makeRequest() and issueRequest()
functions, as they also need to operate on a Packet instead of RubyRequest.
8335:9228e00459d4 Thu Jun 02 20:36:00 EDT 2011 Nathan Binkert <nate@binkert.org> scons: rename TraceFlags to DebugFlags
8161:ebb373fcb206 Sat Mar 19 17:17:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> RubyPort: minor fixes to trace flag and dprintfs
7832:de7601e6e19d Mon Jan 10 14:11:00 EST 2011 Nathan Binkert <nate@binkert.org> ruby: get rid of ruby's Debug.hh

Get rid of the Debug class
Get rid of ASSERT and use assert
Use DPRINTFR for ProtocolTrace
/gem5/src/arch/arm/
H A Disa.cc8549:7cff2156c998 Tue Sep 13 01:06:00 EDT 2011 Daniel Johnson <daniel.johnson@arm.com> ARM: Implement numcpus bits in L2CTLR register.
8527:6bac5b04d588 Fri Aug 19 16:08:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Mark some variables uncacheable until boot all CPUs are enabled.

There are a set of locations is the linux kernel that are managed via
cache maintence instructions until all processors enable their MMUs & TLBs.
Writes to these locations are manually flushed from the cache to main
memory when the occur so that cores operating without their MMU enabled
and only issuing uncached accesses can receive the correct data. Unfortuantely,
gem5 doesn't support any kind of software directed maintence of the cache.
Until such time as that support exists this patch marks the specific cache blocks
that need to be coherent as non-cacheable until all CPUs enable their MMU and
thus allows gem5 to boot MP systems with caches enabled (a requirement for
booting an O3 cpu and thus an O3 CPU regression).
8520:f9a495adafd9 Fri Aug 19 16:08:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add support for DIV/SDIV instructions.
8468:5e9530779f60 Fri Jul 15 12:53:00 EDT 2011 Wade Walker <wade.walker@arm.com> ARM: Add two unimplemented miscellaneous registers.

Adds MISCREG_ID_MMFR2 and removes break on access to MISCREG_CLIDR. Both
registers now return values that are consistent with current ARM
implementations.
8302:9f23d01421de Fri May 13 18:27:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Remove the saturating (Q) condition code from the renamed register.

Move the saturating bit (which is also saturating) from the renamed register
that holds the flags to the CPSR miscreg and adds a allows setting it in a
similar way to the FP saturating registers. This removes a dependency in
instructions that don't write, but need to preserve the Q bit.
8299:64a938a8b7fc Fri May 13 18:27:00 EDT 2011 Chander Sudanthi <chander.sudanthi@arm.com> ARM: Better RealView/Versatile EB platform support.

Add registers and components to better support the VersatileEB board.
Made the MIDR and SYS_ID register parameters to ArmSystem and RealviewCtrl
respectively.
8284:2fcad6253525 Wed May 04 21:38:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add support for MP misc regs and broadcast flushes.
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8208:45331a355c38 Mon Apr 04 12:42:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Fix checkpoint restoration into O3 CPU and the way O3 switchCpu works.

This change fixes a small bug in the arm copyRegs() code where some registers
wouldn't be copied if the processor was in a mode other than MODE_USER.
Additionally, this change simplifies the way the O3 switchCpu code works by
utilizing TheISA::copyRegs() to copy the required context information
rather than the adhoc copying that goes on in the CPU model. The current code
makes assumptions about the visibility of int and float registers that aren't
true for all architectures in FS mode.
8206:c3090dc00ddf Mon Apr 04 12:42:00 EDT 2011 William Wang <William.Wang@arm.com> ARM: Cleanup and small fixes to some NEON ops to match the spec.

Only certain bits of the cpacr can be written, some must be equal.
Mult instructions that write the same register should do something sane
/gem5/src/arch/alpha/isa/
H A Ddecoder.isa8780:89e0822462a1 Tue Nov 01 07:01:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of uses of FULL_SYSTEM in Alpha.
8738:66bf413b0d5b Fri Sep 30 03:27:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Use the new FullSystem constant where possible.
8588:ef28ed90449d Tue Sep 27 02:48:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA parser: Use '_' instead of '.' to delimit type modifiers on operands.

By using an underscore, the "." is still available and can unambiguously be
used to refer to members of a structure if an operand is a structure, class,
etc. This change mostly just replaces the appropriate "."s with "_"s, but
there were also a few places where the ISA descriptions where handling the
extensions themselves and had their own regular expressions to update. The
regular expressions in the isa parser were updated as well. It also now
looks for one of the defined type extensions specifically after connecting "_"
where before it would look for any sequence of characters after a "."
following an operand name and try to use it as the extension. This helps to
disambiguate cases where a "_" may legitimately be part of an operand name but
not separate the name from the type suffix.

Because leaving the "_" and suffix on the variable name still leaves a valid
C++ identifier and all extensions need to be consistent in a given context, I
considered leaving them on as a breadcrumb that would show what the intended
type was for that operand. Unfortunately the operands can be referred to in
code templates, the Mem operand in particular, and since the exact type of Mem
can be different for different uses of the same template, that broke things.
8560:5c4bac827934 Mon Sep 19 06:40:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Alpha: Get rid of some #if FULL_SYSTEMs in the Alpha ISA description.

The remaining ones are more complicated and may require adjustments in other
parts of the simulator.
8556:2afd82e84d95 Mon Sep 19 05:40:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts.
8555:6fd8d0432d8d Mon Sep 19 02:26:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Pseudoinst: Add an initParam pseudo inst function.
8457:7907b19fbe80 Thu Jul 07 21:32:00 EDT 2011 Korey Sewell <ksewell@umich.edu> alpha:hwrei:rollback for o3
change hwrei back to being a non-control instruction so O3-FS mode will work
add squash in inorder that will catch a hwrei (or any other genric instruction)
that isnt a control inst but changes the PC. Additional testing still needs to be done
for inorder-FS mode but this change will free O3 development back up in the interim
8398:d389b6ec0e2d Sun Jun 19 21:43:00 EDT 2011 Korey Sewell <ksewell@umich.edu> alpha: make hwrei a control inst
this always changes the PC and is basically an impromptu branch instruction. why
not speculate on this instead of always be forced to mispredict/squash after the
hwrei gets resolved?

The InOrder model needs this marked as "isControl" so it knows to update the PC
after the ALU executes it. If this isnt marked as control, then it's going to
force the model to check the PC of every instruction at commit (what O3 does?),
and that would be a wasteful check for a very high percentage of instructions.
7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
/gem5/configs/ruby/
H A DRuby.py8638:e8a093d1e131 Thu Dec 01 13:08:00 EST 2011 gloh config: command line option to specify ruby output file
8612:df3b7a1e883f Fri Nov 04 18:40:00 EDT 2011 Tushar Krishna <tushar@csail.mit.edu> GARNET: adding a fault model for resilient on-chip network research.

This patch adds a fault model, which provides the probability of a number of
architectural faults in the interconnection network (e.g., data corruption,
misrouting). These probabilities can be used to realistically inject faults
in GARNET and faithfully evaluate the effectiveness of novel resilient NoC
architectures.
8436:5648986156db Thu Jun 30 20:49:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com>, Nilay Vaish <nilay@cs.wisc.edu> Ruby: Add support for functional accesses
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.
8322:19949c6de823 Mon May 23 17:29:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> config: tweak ruby configs to clean up hierarchy

Re-enabling implicit parenting (see previous patch) causes current
Ruby config scripts to create some strange hierarchies and generate
several warnings. This patch makes three general changes to address
these issues.

1. The order of object creation in the ruby config files makes the L1
caches children of the sequencer rather than the controller; these
config ciles are rewritten to assign the L1 caches to the
controller first.

2. The assignment of the sequencer list to system.ruby.cpu_ruby_ports
causes the sequencers to be children of system.ruby, generating
warnings because they are already parented to their respective
controllers. Changing this attribute to _cpu_ruby_ports fixes this
because the leading underscore means this is now treated as a plain
Python attribute rather than a child assignment. As a result, the
configuration hierarchy changes such that, e.g.,
system.ruby.cpu_ruby_ports0 becomes system.l1_cntrl0.sequencer.

3. In the topology classes, the routers become children of some random
internal link node rather than direct children of the topology.
The topology classes are rewritten to assign the routers to the
topology object first.
8258:7c377f5162f8 Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: basic link bw for garnet and simple networks

This patch ensures that both Garnet and the simple networks use the bw value
specified in the topology. To do so, the patch generalizes the specification
of bw for basic links. This value is then translated to the specific value
used by the simple and Garnet networks. Since Garent does not support
non-uniformed link bandwidth, the patch also adds a check to ensure all bws are
equal.
8257:7226aebb77b4 Thu Apr 28 20:18:00 EDT 2011 Brad Beckmann <Brad.Beckmann@amd.com> network: convert links & switches to first class C++ SimObjects

This patch converts links and switches from second class simobjects that were
virtually ignored by the networks (both simple and Garnet) to first class
simobjects that directly correspond to c++ ojbects manipulated by the
topology and network classes. This is especially true for Garnet, where the
links and switches directly correspond to specific C++ objects.

By making this change, many aspects of the Topology class were simplified.
7917:d9afb18a5008 Mon Feb 07 01:14:00 EST 2011 Brad Beckmann <Brad.Beckmann@amd.com> ruby: numa bit fix for sparse memory
7832:de7601e6e19d Mon Jan 10 14:11:00 EST 2011 Nathan Binkert <nate@binkert.org> ruby: get rid of ruby's Debug.hh

Get rid of the Debug class
Get rid of ASSERT and use assert
Use DPRINTFR for ProtocolTrace
7809:9d94b886c61b Mon Jan 03 01:40:00 EST 2011 Nilay Vaish<nilay@cs.wisc.edu> Ruby: Add option for random seed to Ruby.py
This patch adds an option to the script Ruby.py for setting the parameter
m_random_seed used for randomizing delays in the memory system. The option
can be specified as "--random_seed <seed value>".
/gem5/src/dev/
H A Dio_device.cc8743:0f5ced6ff69e Sun Oct 09 02:24:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Ports: Print the port name when a port is used but not attached to anything.
8742:9df38d259935 Tue Oct 04 05:26:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Put platform pointers in fewer objects.

Not all objects need a platform pointer, and having one creates a dependence
on their being a platform object. This change removes the platform pointer to
from the base device object and moves it into subclasses that actually need
it.
8642:549b72de8f72 Thu Dec 15 00:09:00 EST 2011 Ali Saidi <saidi@eecs.umich.edu> IO: Fix bug in DMA Device where receiving a snoop on DMA port would cause a panic.
8630:05580a8506c7 Thu Dec 01 03:15:00 EST 2011 Mitchell Hayenga <Mitchell.Hayenga@ARM.com> Device: Make changes necessary to support a coherent page walker cache.

Adds the flag 'recvSnoops' which enables pagewalkers using DmaPorts,
to properly configure snoops.
8598:c7fec2cb91cb Thu Oct 20 16:11:00 EDT 2011 Steve Reinhardt <steve.reinhardt@amd.com> dev: clean up PioDevice and DmaDevive getPort() methods.

Make DmaDevice::getPort() call PioDevice::getPort() instead
of just copying and pasting the code.

Also move definitions from .hh to .cc file.
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
8134:b01a51ff05fa Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> Mem: Fix issue with dirty block being lost when entire block transferred to non-cache.

This change fixes the problem for all the cases we actively use. If you want to try
more creative I/O device attachments (E.g. sharing an L2), this won't work. You
would need another level of caching between the I/O device and the cache
(which you actually need anyway with our current code to make sure writes
propagate). This is required so that you can mark the cache in between as
top level and it won't try to send ownership of a block to the I/O device.
Asserts have been added that should catch any issues.
7823:dac01f14f20f Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Replace curTick global variable with accessor functions.
This step makes it easy to replace the accessor functions
(which still access a global variable) with ones that access
per-thread curTick values.
/gem5/src/arch/sparc/
H A DSConscript8778:fbaf6af0be93 Mon Oct 31 05:58:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Remove the last uses of FULL_SYSTEM from SPARC.
8760:df5f2151161d Sun Oct 16 08:06:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SPARC: Build vtophys into SE mode.
8747:017e5bbbb4e2 Mon Oct 10 02:48:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> [mq]: sefssparcregfile.patch
8745:575cab0db076 Sun Oct 09 03:15:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Build the Interrupt objects in SE mode.
8335:9228e00459d4 Thu Jun 02 20:36:00 EDT 2011 Nathan Binkert <nate@binkert.org> scons: rename TraceFlags to DebugFlags
H A Dfaults.hh8794:e2ac2b7164dd Fri Nov 18 05:20:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of includes of config/full_system.hh.
8750:6f63141531c8 Thu Oct 13 04:11:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SPARC: Narrow the scope of #if FULL_SYSTEM in SPARC's faults.
8591:8f23aeaf6a91 Tue Sep 27 03:24:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Faults: Replace calls to genMachineCheckFault with M5PanicFault.
8569:498d3aacd292 Mon Sep 19 09:17:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Faults: Get rid of the unused isAlignmentFault and isMachineCheckFault.

These functions aren't called anywhere and are probably only theoretically
useful.
7811:a8fc35183c10 Mon Jan 03 17:35:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> Make commenting on close namespace brackets consistent.

Ran all the source files through 'perl -pi' with this script:

s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|;
s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|;
s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;

Also did a little manual editing on some of the arch/*/isa_traits.hh files
and src/SConscript.
/gem5/src/arch/sparc/isa/
H A Dincludes.isa8738:66bf413b0d5b Fri Sep 30 03:27:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Use the new FullSystem constant where possible.
8556:2afd82e84d95 Mon Sep 19 05:40:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts.
8442:b1f3dfae06f1 Sun Jul 03 01:34:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> ISA: Use readBytes/writeBytes for all instruction level memory operations.
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/arch/arm/linux/
H A Dsystem.cc8527:6bac5b04d588 Fri Aug 19 16:08:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Mark some variables uncacheable until boot all CPUs are enabled.

There are a set of locations is the linux kernel that are managed via
cache maintence instructions until all processors enable their MMUs & TLBs.
Writes to these locations are manually flushed from the cache to main
memory when the occur so that cores operating without their MMU enabled
and only issuing uncached accesses can receive the correct data. Unfortuantely,
gem5 doesn't support any kind of software directed maintence of the cache.
Until such time as that support exists this patch marks the specific cache blocks
that need to be coherent as non-cacheable until all CPUs enable their MMU and
thus allows gem5 to boot MP systems with caches enabled (a requirement for
booting an O3 cpu and thus an O3 CPU regression).
8286:abc8ab4ddd93 Wed May 04 21:38:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Add support for loading the a bootloader and configuring parameters for it
8245:a9d06c894afe Wed Apr 20 21:45:00 EDT 2011 Nathan Binkert <nate@binkert.org> fix some build problems from prior changesets
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
8143:b0b94a7b7c1f Thu Mar 17 20:20:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> ARM: Detect and skip udelay() functions in linux kernel.

This change speeds up booting, especially in MP cases, by not executing
udelay() on the core but instead skipping ahead tha amount of time that is being
delayed.
/gem5/src/arch/alpha/
H A Dremote_gdb.cc8780:89e0822462a1 Tue Nov 01 07:01:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SE/FS: Get rid of uses of FULL_SYSTEM in Alpha.
8541:27aaee8ec7cc Fri Sep 09 05:30:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> Decode: Pull instruction decoding out of the StaticInst class into its own.

This change pulls the instruction decoding machinery (including caches) out of
the StaticInst class and puts it into its own class. This has a few intrinsic
benefits. First, the StaticInst code, which has gotten to be quite large, gets
simpler. Second, the code that handles decode caching is now separated out
into its own component and can be looked at in isolation, making it easier to
understand. I took the opportunity to restructure the code a bit which will
hopefully also help.

Beyond that, this change also lays some ground work for each ISA to have its
own, potentially stateful decode object. We'd be able to include less
contextualizing information in the ExtMachInst objects since that context
would be applied at the decoder. Also, the decoder could "know" ahead of time
that all the instructions it's going to see are going to be, for instance, 64
bit mode, and it will have one less thing to check when it decodes them.
Because the decode caching mechanism has been separated out, it's now possible
to have multiple caches which correspond to different types of decoding
context. Having one cache for each element of the cross product of different
configurations may become prohibitive, so it may be desirable to clear out the
cache when relatively static state changes and not to have one for each
setting.

Because the decode function is no longer universally accessible as a static
member of the StaticInst class, a new function was added to the ThreadContexts
that returns the applicable decode object.
8332:23711432221f Thu Jun 02 17:36:00 EDT 2011 Nathan Binkert <nate@binkert.org> copyright: clean up copyright blocks
8232:b28d06a175be Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
/gem5/src/arch/x86/
H A Dtlb.hh8768:314eb1e2fa94 Sun Oct 30 03:33:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86: Get rid of more uses of FULL_SYSTEM.
8752:28e899b7dee3 Thu Oct 13 05:22:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> X86: Turn on the page table walker in SE mode.
8229:78bf55f23338 Fri Apr 15 13:44:00 EDT 2011 Nathan Binkert <nate@binkert.org> includes: sort all includes
7912:a9f05ab40763 Mon Feb 07 01:14:00 EST 2011 Joel Hestness <hestness@cs.utexas.edu> x86: Timing support for pagetable walker

Move page table walker state to its own object type, and make the
walker instantiate state for each outstanding walk. By storing the
states in a queue, the walker is able to handle multiple outstanding
timing requests. Note that functional walks use separate state
elements.
7878:d3e6ebcccabf Fri Feb 04 00:47:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Fault: Rename sim/fault.hh to fault_fwd.hh to distinguish it from faults.hh.
/gem5/src/arch/
H A DSConscript8585:e21224136182 Sat Sep 24 20:03:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SCons: Add a comment I forgot to add in earlier.

This comment was supposed to be added to an earlier change as part of review
feedback, but I accidentally left it out when I pushed. Add it in now.
8584:26ece1659229 Sat Sep 24 19:59:00 EDT 2011 Gabe Black <gblack@eecs.umich.edu> SCons: Make the ISA parser a source for its output files like the comments say.

There was a change a while ago that refactored some scons stuff which got rid
of cpu_models.py but also accidentally got rid of the ISA parser as a source
for its target files. That meant that changes which affected the parser
wouldn't cause a rebuild unless they also changed one of the description
files. This change fixes that.
8335:9228e00459d4 Thu Jun 02 20:36:00 EDT 2011 Nathan Binkert <nate@binkert.org> scons: rename TraceFlags to DebugFlags
8105:906864dd0937 Wed Mar 02 02:18:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Spelling: Fix the a spelling error by changing mmaped to mmapped.

There may not be a formally correct spelling for the past tense of mmap, but
mmapped is the spelling Google doesn't try to autocorrect. This makes sense
because it mirrors the past tense of map->mapped and not the past tense of
cape->caped.
7816:b5003ac75977 Sat Jan 08 00:50:00 EST 2011 Steve Reinhardt <steve.reinhardt@amd.com> scons: show sources and targets when building, and colorize output.

I like the brevity of Ali's recent change, but the ambiguity of
sometimes showing the source and sometimes the target is a little
confusing. This patch makes scons typically list all sources and
all targets for each action, with the common path prefix factored
out for brevity. It's a little more verbose now but also more
informative.

Somehow Ali talked me into adding colors too, which is a whole
'nother story.

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