Searched hist:2007 (Results 526 - 550 of 895) sorted by relevance

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/gem5/src/arch/alpha/
H A Dtlb.hh5034:6186ef720dd4 Thu Aug 30 15:16:00 EDT 2007 Miles Kaufmann <milesck@eecs.umich.edu> params: Deprecate old-style constructors; update most SimObject constructors.

SimObjects not yet updated:
- Process and subclasses
- BaseCPU and subclasses

The SimObject(const std::string &name) constructor was removed. Subclasses
that still rely on that behavior must call the parent initializer as
: SimObject(makeParams(name))
5004:7d94cedab264 Sun Aug 26 23:33:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address translation: Make the page table more flexible.
The page table now stores actual page table entries. It is still a templated
class here, but this will be corrected in the near future.
4967:fb9a1d205359 Wed Aug 08 18:38:00 EDT 2007 Vincentius Robby <acolyte@umich.edu> alpha: Quick fix for things related to TLB MRU cache.
simple-timing test for ALPHA_FS breaks.
4960:f0e3c34737d3 Wed Aug 08 00:51:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Alpha: Fix an off by one error with the tlb caching mechanism.
4957:f858d0b8ef99 Sat Aug 04 14:25:00 EDT 2007 Vincentius Robby <acolyte@umich.edu> alpha: Implement a cache for recently used page table entries
H A Dutility.hh4997:e7380529bd2d Sun Aug 26 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
4826:259b996a6da6 Wed Aug 01 16:59:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Arguments: Get rid of duplicate code for the Arguments class in each architecture.
Move the argument files to src/sim and add a utility.cc file with a function
getArguments() that returns the given argument in the architecture specific fashion.
getArguments() was getArg() is the architecture specific Argument class and has had
all magic numbers replaced with meaningful constants. Also add a function to the
Argument class for testing if an argument is NULL.
4240:cde9d7751cce Wed Mar 14 22:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

src/arch/mips/utility.hh:
src/arch/x86/SConscript:
Hand merge
4194:af4f6022394b Fri Mar 09 16:56:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> implement ipi stufff for SPARC

src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/arch/x86/utility.hh:
add hook for system to startup the cpu or not... in the case of FS sparc, only the first cpu would get spunup.. the rest sit in an idle state until they get an ipi
src/arch/sparc/isa/decoder.isa:
handle writable bits of strandstatus register in miscregfile
src/arch/sparc/miscregfile.hh:
some constants for the strand status register
src/arch/sparc/ua2005.cc:
properly implement the strand status register
src/dev/sparc/iob.cc:
implement ipi generation properly
src/sim/system.cc:
call into the ISA to start the CPU (or not)
4182:5b2c0d266107 Wed Mar 14 22:47:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the predecoder an object with it's own switched header file. Start adding predecoding functionality to x86.

src/arch/SConscript:
src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/cpu/base.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/static_inst.hh:
src/arch/alpha/predecoder.hh:
src/arch/mips/predecoder.hh:
src/arch/sparc/predecoder.hh:
Make the predecoder an object with it's own switched header file.
4181:6edaeff44647 Tue Mar 13 12:13:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Replaced makeExtMI with predecode.
Removed the getOpcode function from StaticInst which only made sense for Alpha.
Started implementing the x86 predecoder.
4172:141705d83494 Wed Mar 07 15:04:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
/gem5/src/arch/mips/isa/formats/
H A Dbranch.isa5269:0bdd8bbdc79f Sat Nov 17 00:02:00 EST 2007 Korey Sewell <ksewell@umich.edu> add back in clobbered MIPS fix for g++ 4.2
5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
5202:ff56fa8c2091 Wed Oct 31 21:04:00 EDT 2007 Steve Reinhardt <stever@gmail.com> String constant const-ness changes to placate g++ 4.2.
Also some bug fixes in MIPS ISA uncovered by g++ warnings
(Python string compares don't work in C++!).
4661:44458219add1 Fri Jun 22 19:03:00 EDT 2007 Korey Sewell <ksewell@umich.edu> mips import pt. 1

src/arch/mips/SConscript:
"mips import pt.1".
H A Dint.isa5269:0bdd8bbdc79f Sat Nov 17 00:02:00 EST 2007 Korey Sewell <ksewell@umich.edu> add back in clobbered MIPS fix for g++ 4.2
5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
5202:ff56fa8c2091 Wed Oct 31 21:04:00 EDT 2007 Steve Reinhardt <stever@gmail.com> String constant const-ness changes to placate g++ 4.2.
Also some bug fixes in MIPS ISA uncovered by g++ warnings
(Python string compares don't work in C++!).
4661:44458219add1 Fri Jun 22 19:03:00 EDT 2007 Korey Sewell <ksewell@umich.edu> mips import pt. 1

src/arch/mips/SConscript:
"mips import pt.1".
H A Dmem.isa5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
4675:598d4c33c38d Fri Jun 29 15:13:00 EDT 2007 Korey Sewell <ksewell@umich.edu> fix store instructions, pass fast/quick Atomic/TimingSimpleCPU regressions...

src/arch/mips/isa/decoder.isa:
commment out deret instruction for now...
src/arch/mips/isa/formats/fp.isa:
edit fp format
src/arch/mips/isa/formats/mem.isa:
fix for basic store instructions
4673:833d4a116810 Thu Jun 28 05:30:00 EDT 2007 Korey Sewell <ksewell@umich.edu> o3cpu build for mips
4661:44458219add1 Fri Jun 22 19:03:00 EDT 2007 Korey Sewell <ksewell@umich.edu> mips import pt. 1

src/arch/mips/SConscript:
"mips import pt.1".
4056:f8f1dffc5913 Tue Feb 13 11:09:00 EST 2007 Steve Reinhardt <stever@eecs.umich.edu> Update MIPS ISA description to work with new write result interface
for store conditional.
4055:3b00870359aa Tue Feb 13 10:07:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> fix compiling problems
/gem5/src/mem/
H A Dtport.hh4929:6db35d0c81c6 Sun Jul 29 23:17:00 EDT 2007 Steve Reinhardt <stever@gmail.com> memory system: fix functional access bug.
Make sure not to keep processing functional accesses
after they've been responded to.
Also use checkFunctional() return value instead of checking
packet command field where possible, mostly just for consistency.
4871:02c0ad6e09ee Sat Jun 30 16:34:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Fix up a few statistics problems.
Stats pretty much line up with old code, except:
- bug in old code included L1 latency in L2 miss time, making it too high
- UniCoherence did cache-to-cache transfers even from non-owner caches,
so occasionally the icache would get a block from the dcache not the L2
- L2 can now receive ReadExReq from L1 since L1s have coherence
4666:5d110d024fcf Mon Jun 25 09:47:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of requestCauses. Use timestamped queue to make
sure we don't re-request bus prematurely. Use callback to
avoid calling sendRetry() recursively within recvTiming.
4492:75dabb0392ee Wed May 30 01:23:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> A little more cleanup & refactoring of SimpleTimingPort.
Make it a better base class for cache ports.
4490:f9d3db907eec Mon May 28 11:11:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Restructure SimpleTimingPort a bit:
- factor out checkFunctional() code so it can be
called from derived classes
- use EventWrapper for sendEvent, move event handling
code from event to port where it belongs
- make sendEvent a pointer so derived classes can
override it
- replace std::pair with new class for readability
H A Dpage_table.cc5248:b27aab7165da Wed Nov 14 23:42:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Checkpointing: Name SE page table entries better so that there isn't a problem if multiple workloads are being run at once.
5184:8782de2949e5 Thu Oct 25 22:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> TLB: Fix serialization issues with the tlb entries and make the page table store the process, not the system.
5183:b4decf133fe4 Thu Oct 25 20:13:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> SE: Fix page table and system serialization, don't reinit process if this is a checkpoint restore.
5004:7d94cedab264 Sun Aug 26 23:33:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address translation: Make the page table more flexible.
The page table now stores actual page table entries. It is still a templated
class here, but this will be corrected in the near future.
4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
4521:0236d1cdb330 Tue Jun 05 01:03:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Clean up some of vincent's code and commit it
Makes page table cache scheme actually work

src/mem/page_table.cc:
src/mem/page_table.hh:
fix caching scheme to actually work and improve performance
4183:3d19c1d46946 Wed Mar 07 15:04:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Move the magic m5 PageTableFault into sim/faults.[hh,cc] since it's the same across all architectures.
H A Dphysical.hh5275:5279ced1dd8b Mon Nov 19 18:23:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Memory: Cache the physical memory start and size so we don't need a dynamic cast on every access.
4918:3214e3694fb2 Fri Jul 27 02:15:00 EDT 2007 Nathan Binkert <nate@binkert.org> Merge python and x86 changes with cache branch
4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
4626:ed8aacb19c03 Sun Jun 17 20:27:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> More major reorg of cache. Seems to work for atomic mode now,
timing mode still broken.

configs/example/memtest.py:
Revamp options.
src/cpu/memtest/memtest.cc:
No need for memory initialization.
No need to make atomic response... memory system should do that now.
src/cpu/memtest/memtest.hh:
MemTest really doesn't want to snoop.
src/mem/bridge.cc:
checkFunctional() cleanup.
src/mem/bus.cc:
src/mem/bus.hh:
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.cc:
src/mem/cache/cache.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_builder.cc:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/coherence_protocol.cc:
src/mem/cache/coherence/coherence_protocol.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/miss/SConscript:
src/mem/cache/miss/mshr.cc:
src/mem/cache/miss/mshr.hh:
src/mem/cache/miss/mshr_queue.cc:
src/mem/cache/miss/mshr_queue.hh:
src/mem/cache/prefetch/base_prefetcher.cc:
src/mem/cache/tags/fa_lru.cc:
src/mem/cache/tags/fa_lru.hh:
src/mem/cache/tags/iic.cc:
src/mem/cache/tags/iic.hh:
src/mem/cache/tags/lru.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.cc:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.cc:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.cc:
src/mem/cache/tags/split_lru.hh:
src/mem/packet.cc:
src/mem/packet.hh:
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/tport.cc:
More major reorg. Seems to work for atomic mode now,
timing mode still broken.
4475:fb185cc1c845 Tue May 22 02:36:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Change getDeviceAddressRanges to use bool for snoop arg.
4467:cb5715e021ca Sat May 19 00:24:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> PhysicalMemory has vector of uniform ports instead of one special one.

configs/example/memtest.py:
PhysicalMemory has vector of uniform ports instead of one special one.
Other updates to fix obsolete brokenness.
src/mem/physical.cc:
src/mem/physical.hh:
src/python/m5/objects/PhysicalMemory.py:
Have vector of uniform ports instead of one special one.
src/python/swig/pyobject.cc:
Add comment.
4040:eb894f3fc168 Mon Feb 12 13:06:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> rename store conditional stuff as extra data so it can be used for conditional swaps as well
Add support for a twin 64 bit int load
Add Memory barrier and write barrier flags as appropriate
Make atomic memory ops atomic

src/arch/alpha/isa/mem.isa:
src/arch/alpha/locked_mem.hh:
src/cpu/base_dyn_inst.hh:
src/mem/cache/cache_blk.hh:
src/mem/cache/cache_impl.hh:
rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/arch/alpha/types.hh:
src/arch/mips/types.hh:
src/arch/sparc/types.hh:
add a largest read data type for statically allocating read buffers in atomic simple cpu
src/arch/isa_parser.py:
Add support for a twin 64 bit int load
src/arch/sparc/isa/decoder.isa:
Make atomic memory ops atomic
Add Memory barrier and write barrier flags as appropriate
src/arch/sparc/isa/formats/mem/basicmem.isa:
add post access code block and define a twinload format for twin loads
src/arch/sparc/isa/formats/mem/blockmem.isa:
remove old microcoded twin load coad
src/arch/sparc/isa/formats/mem/mem.isa:
swap.isa replaces the code in loadstore.isa
src/arch/sparc/isa/formats/mem/util.isa:
add a post access code block
src/arch/sparc/isa/includes.isa:
need bigint.hh for Twin64_t
src/arch/sparc/isa/operands.isa:
add a twin 64 int type
src/cpu/simple/atomic.cc:
src/cpu/simple/atomic.hh:
src/cpu/simple/base.hh:
src/cpu/simple/timing.cc:
add support for twinloads
add support for swap and conditional swap instructions
rename store conditional stuff as extra data so it can be used for conditional swaps as well
src/mem/packet.cc:
src/mem/packet.hh:
Add support for atomic swap memory commands
src/mem/packet_access.hh:
Add endian conversion function for Twin64_t type
src/mem/physical.cc:
src/mem/physical.hh:
src/mem/request.hh:
Add support for atomic swap memory commands
Rename sc code to extradata
/gem5/src/dev/
H A DSConscript5192:582e583f8e7e Wed Oct 31 01:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Traceflags: Add SCons function to created a traceflag instead of having one file with them all.
4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
4486:aaeb03a8a6e1 Sun May 27 22:21:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.
4218:f214fc9a4883 Thu Mar 15 15:16:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> add all the registers we'll need to support for the Intel GbE device and support enough functionality make the driver think
the device is there, and in good working order.

src/dev/SConscript:
add intel gbe to the dev SCons file
src/dev/i8254xGBe.cc:
src/dev/i8254xGBe.hh:
src/dev/i8254xGBe_defs.hh:
use new manner of registers and implement all device registers that are touched through boot and ifup
4202:f7a05daec670 Sun Mar 11 03:00:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Rework the way SCons recurses into subdirectories, making it
automatic. The point is that now a subdirectory can be added
to the build process just by creating a SConscript file in it.
The process has two passes. On the first pass, all subdirs
of the root of the tree are searched for SConsopts files.
These files contain any command line options that ought to be
added for a particular subdirectory. On the second pass,
all subdirs of the src directory are searched for SConscript
files. These files describe how to build any given subdirectory.
I have added a Source() function. Any file (relative to the
directory in which the SConscript resides) passed to that
function is added to the build. Clean up everything to take
advantage of Source().
function is added to the list of files to be built.
H A Dplatform.cc5034:6186ef720dd4 Thu Aug 30 15:16:00 EDT 2007 Miles Kaufmann <milesck@eecs.umich.edu> params: Deprecate old-style constructors; update most SimObject constructors.

SimObjects not yet updated:
- Process and subclasses
- BaseCPU and subclasses

The SimObject(const std::string &name) constructor was removed. Subclasses
that still rely on that behavior must call the parent initializer as
: SimObject(makeParams(name))
4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
3918:1f9a98d198e8 Fri Jan 26 18:48:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make our code a little more standards compliant
pretty close to compiling w/ suns compiler

briefly:
add dummy return after panic()/fatal()
split out flags by compiler vendor
include cstring and cmath where appropriate
use std namespace for string ops

SConstruct:
Add code to detect compiler and choose cflags based on detected compiler
Fix zlib check to work with suncc
src/SConscript:
split out flags by compiler vendor
src/arch/sparc/isa/decoder.isa:
use correct namespace for sqrt
src/arch/sparc/isa/formats/basic.isa:
add dummy return around panic
src/arch/sparc/isa/formats/integerop.isa:
use correct namespace for stringops
src/arch/sparc/isa/includes.isa:
include cstring and cmath where appropriate
src/arch/sparc/isa_traits.hh:
remove dangling comma
src/arch/sparc/system.cc:
dummy return to make sun cc front end happy
src/arch/sparc/tlb.cc:
src/base/compression/lzss_compression.cc:
use std namespace for string ops
src/arch/sparc/utility.hh:
no reason to say something is unsigned unsigned int
src/base/compression/null_compression.hh:
dummy returns to for suncc front end
src/base/cprintf.hh:
use standard variadic argument syntax instead of gnuc specefic renaming
src/base/hashmap.hh:
don't need to define hash for suncc
src/base/hostinfo.cc:
need stdio.h for sprintf
src/base/loader/object_file.cc:
munmap is in std namespace not null
src/base/misc.hh:
use M5 generic noreturn macros
use standard variadic macro __VA_ARGS__
src/base/pollevent.cc:
we need file.h for file flags
src/base/random.cc:
mess with include files to make suncc happy
src/base/remote_gdb.cc:
malloc memory for function instead of having a non-constant in an array size
src/base/statistics.hh:
use std namespace for floor
src/base/stats/text.cc:
include math.h for rint (cmath won't work)
src/base/time.cc:
use suncc version of ctime_r
src/base/time.hh:
change macro to work with both gcc and suncc
src/base/timebuf.hh:
include cstring from memset and use std::
src/base/trace.hh:
change variadic macros to be normal format
src/cpu/SConscript:
add dummy returns where appropriate
src/cpu/activity.cc:
include cstring for memset
src/cpu/exetrace.hh:
include cstring fro memcpy
src/cpu/simple/base.hh:
add dummy return for panic
src/dev/baddev.cc:
src/dev/pciconfigall.cc:
src/dev/platform.cc:
src/dev/sparc/t1000.cc:
add dummy return where appropriate
src/dev/ide_atareg.h:
make define work for both gnuc and suncc
src/dev/io_device.hh:
add dummy returns where approirate
src/dev/pcidev.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.hh:
src/mem/dram.cc:
src/mem/packet.cc:
src/mem/port.cc:
include cstring for string ops
src/dev/sparc/mm_disk.cc:
add dummy return where appropriate
include cstring for string ops
src/mem/cache/miss/blocking_buffer.hh:
src/mem/port.hh:
Add dummy return where appropriate
src/mem/cache/tags/iic.cc:
cast hastSets to double for log() call
src/mem/physical.cc:
cast pmemAddr to char* for munmap
src/sim/byteswap.hh:
make define work for suncc and gnuc
/gem5/src/cpu/simple/
H A Dbase.hh5250:42577371ff31 Thu Nov 15 03:10:00 EST 2007 Korey Sewell <ksewell@umich.edu> Get MIPS simple regression working. Take out unecessary functions "setShadowSet", "CacheOp"
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
5169:bfd18d401251 Thu Oct 18 13:15:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> CPU: Use the ThreadContext cpu id instead of the params cpu id in all cases.
4998:51a0f9f59cc5 Sun Aug 26 23:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Simple CPU: Make sure only instructions which complete without faulting are counted.
4997:e7380529bd2d Sun Aug 26 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
4950:f5f19784acf1 Tue Aug 07 18:19:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make a microcode branch microop.
Also some touch up for ruflag.
4870:fcc39d001154 Sat Jun 30 13:16:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of Packet result field. Error responses are
now encoded in cmd field.
4661:44458219add1 Fri Jun 22 19:03:00 EDT 2007 Korey Sewell <ksewell@umich.edu> mips import pt. 1

src/arch/mips/SConscript:
"mips import pt.1".
4564:d1fb13424616 Wed Jun 13 16:09:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Seperate the pc-pc and the pc of the incoming bytes, and get rid of the "moreBytes" which just takes a MachInst.

src/arch/x86/predecoder.cc:
Seperate the pc-pc and the pc of the incoming bytes, and get rid of the "moreBytes" which just takes a MachInst. Also make the "opSize" field describe the number of bytes and not the log of the number of bytes.
4377:ca55a0b1990a Fri May 18 13:42:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Changes to make simple cpu handle pcs appropriately for x86
H A Dtiming.cc5310:4164e6bfcc8a Sun Dec 16 03:48:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> CPU: Update where the simple cpus read their cpu id from the thread context to init() to make sure they read the right value. This fixes a bug with multi-processor full-system configurations.
5221:dba788e614fe Thu Nov 08 10:46:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> TimingSimpleCPU: Add some DPRINTFs when the cpu suspends and resumes.
5177:4307a768e10e Mon Oct 22 17:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> CPU: Add functions to the "ExecContext"s that translate a given address.
5169:bfd18d401251 Thu Oct 18 13:15:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> CPU: Use the ThreadContext cpu id instead of the params cpu id in all cases.
5103:391933804192 Mon Oct 01 02:55:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> CPU: fix sparc_fs booting with SimpleTimingCPU.
5101:8af5a6a6223d Fri Sep 28 13:22:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Update stats for quiesced cycles
5100:7a0180040755 Fri Sep 28 13:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Rename cycles() function to ticks()
5099:8ff1345b3ae4 Fri Sep 28 13:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Update statistics to use cycles properly instead of ticks
5018:21795007349e Mon Aug 27 21:33:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge with head.
5012:c0a28154d002 Mon Aug 27 00:45:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge with head
/gem5/src/arch/
H A Disa_parser.py5250:42577371ff31 Thu Nov 15 03:10:00 EST 2007 Korey Sewell <ksewell@umich.edu> Get MIPS simple regression working. Take out unecessary functions "setShadowSet", "CacheOp"
5249:49d44a466496 Thu Nov 15 00:14:00 EST 2007 Korey Sewell <ksewell@umich.edu> branch merge
5228:b08c9c42907a Thu Nov 08 21:51:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> ISA parser: Make the isa parser generate MaxInstSrcRegs and MaxInstDestRegs.
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
4950:f5f19784acf1 Tue Aug 07 18:19:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make a microcode branch microop.
Also some touch up for ruflag.
4731:7495af50d714 Sat Jul 21 02:12:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fixed line number accounting
4663:449d172ca8ae Fri Jun 22 21:09:00 EDT 2007 Korey Sewell <ksewell@umich.edu> FINISH off merge of mips mt/dsp isa extensions by adding the ControlBitfieldOPerand to ISA Parser. Now, while things do build, we have to fix broken functionality...

src/arch/isa_parser.py:
add back deleted writeback in Control Operand
4662:96fb82f4f3d5 Fri Jun 22 20:09:00 EDT 2007 Korey Sewell <ksewell@umich.edu> add Control Bitfield class
4481:bb7d575f646f Fri May 25 22:29:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem
into doughnut.mwconnections.com:/home/gblack/m5/newmem-x86
4479:61d3ed46e373 Fri May 25 00:54:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Update to ply 2.3

ext/ply/ply/lex.py:
ext/ply/ply/yacc.py:
ext/ply/CHANGES:
ext/ply/README:
ext/ply/TODO:
ext/ply/doc/ply.html:
ext/ply/example/ansic/clex.py:
ext/ply/example/ansic/cparse.py:
ext/ply/example/calc/calc.py:
ext/ply/example/hedit/hedit.py:
ext/ply/example/optcalc/calc.py:
ext/ply/test/README:
ext/ply/test/calclex.py:
ext/ply/test/lex_doc1.exp:
ext/ply/test/lex_doc1.py:
ext/ply/test/lex_dup1.exp:
ext/ply/test/lex_dup1.py:
ext/ply/test/lex_dup2.exp:
ext/ply/test/lex_dup2.py:
ext/ply/test/lex_dup3.exp:
ext/ply/test/lex_dup3.py:
ext/ply/test/lex_empty.py:
ext/ply/test/lex_error1.py:
ext/ply/test/lex_error2.py:
ext/ply/test/lex_error3.exp:
ext/ply/test/lex_error3.py:
ext/ply/test/lex_error4.exp:
ext/ply/test/lex_error4.py:
ext/ply/test/lex_hedit.exp:
ext/ply/test/lex_hedit.py:
ext/ply/test/lex_ignore.exp:
ext/ply/test/lex_ignore.py:
ext/ply/test/lex_re1.exp:
ext/ply/test/lex_re1.py:
ext/ply/test/lex_rule1.py:
ext/ply/test/lex_token1.py:
ext/ply/test/lex_token2.py:
ext/ply/test/lex_token3.py:
ext/ply/test/lex_token4.py:
ext/ply/test/lex_token5.exp:
ext/ply/test/lex_token5.py:
ext/ply/test/yacc_badargs.exp:
ext/ply/test/yacc_badargs.py:
ext/ply/test/yacc_badprec.exp:
ext/ply/test/yacc_badprec.py:
ext/ply/test/yacc_badprec2.exp:
ext/ply/test/yacc_badprec2.py:
ext/ply/test/yacc_badrule.exp:
ext/ply/test/yacc_badrule.py:
ext/ply/test/yacc_badtok.exp:
ext/ply/test/yacc_badtok.py:
ext/ply/test/yacc_dup.exp:
ext/ply/test/yacc_dup.py:
ext/ply/test/yacc_error1.exp:
ext/ply/test/yacc_error1.py:
ext/ply/test/yacc_error2.exp:
ext/ply/test/yacc_error2.py:
ext/ply/test/yacc_error3.exp:
ext/ply/test/yacc_error3.py:
ext/ply/test/yacc_inf.exp:
ext/ply/test/yacc_inf.py:
ext/ply/test/yacc_missing1.exp:
ext/ply/test/yacc_missing1.py:
ext/ply/test/yacc_nodoc.exp:
ext/ply/test/yacc_nodoc.py:
ext/ply/test/yacc_noerror.exp:
ext/ply/test/yacc_noerror.py:
ext/ply/test/yacc_nop.exp:
ext/ply/test/yacc_nop.py:
ext/ply/test/yacc_notfunc.exp:
ext/ply/test/yacc_notfunc.py:
ext/ply/test/yacc_notok.exp:
ext/ply/test/yacc_notok.py:
ext/ply/test/yacc_rr.exp:
ext/ply/test/yacc_rr.py:
ext/ply/test/yacc_simple.exp:
ext/ply/test/yacc_simple.py:
ext/ply/test/yacc_sr.exp:
ext/ply/test/yacc_sr.py:
ext/ply/test/yacc_term1.exp:
ext/ply/test/yacc_term1.py:
ext/ply/test/yacc_unused.exp:
ext/ply/test/yacc_unused.py:
ext/ply/test/yacc_uprec.exp:
ext/ply/test/yacc_uprec.py:
Import patch ply.diff
src/arch/isa_parser.py:
everything is now within the ply package
/gem5/src/arch/sparc/
H A Dfaults.cc5184:8782de2949e5 Thu Oct 25 22:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> TLB: Fix serialization issues with the tlb entries and make the page table store the process, not the system.
4997:e7380529bd2d Sun Aug 26 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
4183:3d19c1d46946 Wed Mar 07 15:04:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Move the magic m5 PageTableFault into sim/faults.[hh,cc] since it's the same across all architectures.
4172:141705d83494 Wed Mar 07 15:04:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
4129:702776ad560a Sat Mar 03 19:03:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
4111:65fffcb4fae9 Wed Feb 28 11:36:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Make trap instructions always generate TrapInstruction Fault objects which call into the Process object to handle system calls. Refactored the Process objects, and move the handler code into it's own file, and add some syscalls which are used in a natively compiled hello world. Software traps with trap number 3 (not syscall number 3) are supposed to cause the register windows to be flushed but are ignored right now. Finally, made uname for SPARC report a 2.6.12 kernel which is what m22-018.pool happens to be running.
4103:785279436bdd Sat Mar 03 17:22:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Implement Niagara I/O interface and rework interrupts

configs/common/FSConfig.py:
Use binaries we've compiled instead of the ones that come with Legion
src/arch/alpha/interrupts.hh:
get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number
src/arch/sparc/asi.cc:
Add AsiIsInterrupt() to AsiIsMmu()
src/arch/sparc/faults.cc:
src/arch/sparc/faults.hh:
Add InterruptVector type
src/arch/sparc/interrupts.hh:
rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared
src/arch/sparc/isa_traits.hh:
Add the "interrupt" trap types to isa traits
src/arch/sparc/miscregfile.cc:
add names for all the misc registers and possible post an interrupt when TL is changed.
src/arch/sparc/miscregfile.hh:
Add a helper function to post an interrupt when pil < some set softint
src/arch/sparc/regfile.cc:
src/arch/sparc/regfile.hh:
InterruptLevel shouldn't really live here, moved to interrupt.hh
src/arch/sparc/tlb.cc:
Add interrupt ASIs to TLB
src/arch/sparc/ua2005.cc:
Add checkSoftInt to check if a softint needs to be posted
Check that a tickCompare isn't scheduled before scheduling one
Post and clear interrupts on queue writes and what not
src/base/bitfield.hh:
Add an helper function to return the msb that is set
src/cpu/base.cc:
src/cpu/base.hh:
get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending
src/cpu/intr_control.cc:
src/cpu/intr_control.hh:
src/dev/alpha/tsunami_cchip.cc:
src/python/m5/objects/IntrControl.py:
Make IntrControl have a system pointer rather than using a cpu pointer to get one
src/dev/sparc/SConscript:
add iob to SConsscrip
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini:
tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out:
update config.ini/out for intrcntrl not having a cpu pointer anymore
3975:10fa2125f19e Wed Jan 24 19:57:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/newmem
3972:2c65c89843c5 Tue Jan 23 01:31:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem
into ewok.(none):/home/gblack/m5/newmemo3

src/sim/byteswap.hh:
Hand Merge
3928:9486450f013f Tue Jan 23 15:50:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> use pstate.am to mask off PC/NPC where it needs to +be
check writability of tlb cache entry before using
update tagaccess in places I forgot to
move the tlb privileged test up since it is higher priority

src/arch/sparc/faults.cc:
save only 32 bits of PC/NPC if Pstate.am is set
src/arch/sparc/isa/decoder.isa:
return only 32 bits of PC/NPC if Pstate.am is set
increment cleanwin correctly
src/arch/sparc/tlb.cc:
check writability of cache entry
update tagaccess in a few more places
move the privileged test up since it is higher priority
src/cpu/exetrace.cc:
mask off upper bits of pc if pstate.am is set before comparing to legion
H A Dutility.hh4826:259b996a6da6 Wed Aug 01 16:59:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Arguments: Get rid of duplicate code for the Arguments class in each architecture.
Move the argument files to src/sim and add a utility.cc file with a function
getArguments() that returns the given argument in the architecture specific fashion.
getArguments() was getArg() is the architecture specific Argument class and has had
all magic numbers replaced with meaningful constants. Also add a function to the
Argument class for testing if an argument is NULL.
4240:cde9d7751cce Wed Mar 14 22:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

src/arch/mips/utility.hh:
src/arch/x86/SConscript:
Hand merge
4194:af4f6022394b Fri Mar 09 16:56:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> implement ipi stufff for SPARC

src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/arch/x86/utility.hh:
add hook for system to startup the cpu or not... in the case of FS sparc, only the first cpu would get spunup.. the rest sit in an idle state until they get an ipi
src/arch/sparc/isa/decoder.isa:
handle writable bits of strandstatus register in miscregfile
src/arch/sparc/miscregfile.hh:
some constants for the strand status register
src/arch/sparc/ua2005.cc:
properly implement the strand status register
src/dev/sparc/iob.cc:
implement ipi generation properly
src/sim/system.cc:
call into the ISA to start the CPU (or not)
4182:5b2c0d266107 Wed Mar 14 22:47:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the predecoder an object with it's own switched header file. Start adding predecoding functionality to x86.

src/arch/SConscript:
src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/cpu/base.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/static_inst.hh:
src/arch/alpha/predecoder.hh:
src/arch/mips/predecoder.hh:
src/arch/sparc/predecoder.hh:
Make the predecoder an object with it's own switched header file.
4181:6edaeff44647 Tue Mar 13 12:13:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Replaced makeExtMI with predecode.
Removed the getOpcode function from StaticInst which only made sense for Alpha.
Started implementing the x86 predecoder.
4172:141705d83494 Wed Mar 07 15:04:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
3918:1f9a98d198e8 Fri Jan 26 18:48:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make our code a little more standards compliant
pretty close to compiling w/ suns compiler

briefly:
add dummy return after panic()/fatal()
split out flags by compiler vendor
include cstring and cmath where appropriate
use std namespace for string ops

SConstruct:
Add code to detect compiler and choose cflags based on detected compiler
Fix zlib check to work with suncc
src/SConscript:
split out flags by compiler vendor
src/arch/sparc/isa/decoder.isa:
use correct namespace for sqrt
src/arch/sparc/isa/formats/basic.isa:
add dummy return around panic
src/arch/sparc/isa/formats/integerop.isa:
use correct namespace for stringops
src/arch/sparc/isa/includes.isa:
include cstring and cmath where appropriate
src/arch/sparc/isa_traits.hh:
remove dangling comma
src/arch/sparc/system.cc:
dummy return to make sun cc front end happy
src/arch/sparc/tlb.cc:
src/base/compression/lzss_compression.cc:
use std namespace for string ops
src/arch/sparc/utility.hh:
no reason to say something is unsigned unsigned int
src/base/compression/null_compression.hh:
dummy returns to for suncc front end
src/base/cprintf.hh:
use standard variadic argument syntax instead of gnuc specefic renaming
src/base/hashmap.hh:
don't need to define hash for suncc
src/base/hostinfo.cc:
need stdio.h for sprintf
src/base/loader/object_file.cc:
munmap is in std namespace not null
src/base/misc.hh:
use M5 generic noreturn macros
use standard variadic macro __VA_ARGS__
src/base/pollevent.cc:
we need file.h for file flags
src/base/random.cc:
mess with include files to make suncc happy
src/base/remote_gdb.cc:
malloc memory for function instead of having a non-constant in an array size
src/base/statistics.hh:
use std namespace for floor
src/base/stats/text.cc:
include math.h for rint (cmath won't work)
src/base/time.cc:
use suncc version of ctime_r
src/base/time.hh:
change macro to work with both gcc and suncc
src/base/timebuf.hh:
include cstring from memset and use std::
src/base/trace.hh:
change variadic macros to be normal format
src/cpu/SConscript:
add dummy returns where appropriate
src/cpu/activity.cc:
include cstring for memset
src/cpu/exetrace.hh:
include cstring fro memcpy
src/cpu/simple/base.hh:
add dummy return for panic
src/dev/baddev.cc:
src/dev/pciconfigall.cc:
src/dev/platform.cc:
src/dev/sparc/t1000.cc:
add dummy return where appropriate
src/dev/ide_atareg.h:
make define work for both gnuc and suncc
src/dev/io_device.hh:
add dummy returns where approirate
src/dev/pcidev.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.hh:
src/mem/dram.cc:
src/mem/packet.cc:
src/mem/port.cc:
include cstring for string ops
src/dev/sparc/mm_disk.cc:
add dummy return where appropriate
include cstring for string ops
src/mem/cache/miss/blocking_buffer.hh:
src/mem/port.hh:
Add dummy return where appropriate
src/mem/cache/tags/iic.cc:
cast hastSets to double for log() call
src/mem/physical.cc:
cast pmemAddr to char* for munmap
src/sim/byteswap.hh:
make define work for suncc and gnuc
/gem5/src/cpu/
H A Dexetrace.hh5034:6186ef720dd4 Thu Aug 30 15:16:00 EDT 2007 Miles Kaufmann <milesck@eecs.umich.edu> params: Deprecate old-style constructors; update most SimObject constructors.

SimObjects not yet updated:
- Process and subclasses
- BaseCPU and subclasses

The SimObject(const std::string &name) constructor was removed. Subclasses
that still rely on that behavior must call the parent initializer as
: SimObject(makeParams(name))
4776:8c8407243a2c Sat Jul 28 23:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Turn the instruction tracing code into pluggable sim objects.
These need to be refined a little still and given parameters.
4178:136238c35e4e Wed Mar 07 12:46:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Add setData functions for the new Twin??_t types.
4074:f2c4afa8cd46 Sat Feb 17 23:32:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Default to tracing being disabled in C++, it will be turned
on in python. Fix the trace start code so it actually starts
when it is suppsed to. Make the Exec tracing stuff obey the
trace enabled flag.
4054:3d617b3be4fa Tue Feb 13 03:59:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Merge all of the execution trace configuration stuff into
the traceflags infrastructure. InstExec is now just Exec
and all of the command line options are now trace options.
4046:ef34b290091e Sat Feb 10 18:14:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Clean up tracing stuff more, get rid of the trace log since
its not all that useful. Fix a few bugs with python/C++
integration.
3918:1f9a98d198e8 Fri Jan 26 18:48:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make our code a little more standards compliant
pretty close to compiling w/ suns compiler

briefly:
add dummy return after panic()/fatal()
split out flags by compiler vendor
include cstring and cmath where appropriate
use std namespace for string ops

SConstruct:
Add code to detect compiler and choose cflags based on detected compiler
Fix zlib check to work with suncc
src/SConscript:
split out flags by compiler vendor
src/arch/sparc/isa/decoder.isa:
use correct namespace for sqrt
src/arch/sparc/isa/formats/basic.isa:
add dummy return around panic
src/arch/sparc/isa/formats/integerop.isa:
use correct namespace for stringops
src/arch/sparc/isa/includes.isa:
include cstring and cmath where appropriate
src/arch/sparc/isa_traits.hh:
remove dangling comma
src/arch/sparc/system.cc:
dummy return to make sun cc front end happy
src/arch/sparc/tlb.cc:
src/base/compression/lzss_compression.cc:
use std namespace for string ops
src/arch/sparc/utility.hh:
no reason to say something is unsigned unsigned int
src/base/compression/null_compression.hh:
dummy returns to for suncc front end
src/base/cprintf.hh:
use standard variadic argument syntax instead of gnuc specefic renaming
src/base/hashmap.hh:
don't need to define hash for suncc
src/base/hostinfo.cc:
need stdio.h for sprintf
src/base/loader/object_file.cc:
munmap is in std namespace not null
src/base/misc.hh:
use M5 generic noreturn macros
use standard variadic macro __VA_ARGS__
src/base/pollevent.cc:
we need file.h for file flags
src/base/random.cc:
mess with include files to make suncc happy
src/base/remote_gdb.cc:
malloc memory for function instead of having a non-constant in an array size
src/base/statistics.hh:
use std namespace for floor
src/base/stats/text.cc:
include math.h for rint (cmath won't work)
src/base/time.cc:
use suncc version of ctime_r
src/base/time.hh:
change macro to work with both gcc and suncc
src/base/timebuf.hh:
include cstring from memset and use std::
src/base/trace.hh:
change variadic macros to be normal format
src/cpu/SConscript:
add dummy returns where appropriate
src/cpu/activity.cc:
include cstring for memset
src/cpu/exetrace.hh:
include cstring fro memcpy
src/cpu/simple/base.hh:
add dummy return for panic
src/dev/baddev.cc:
src/dev/pciconfigall.cc:
src/dev/platform.cc:
src/dev/sparc/t1000.cc:
add dummy return where appropriate
src/dev/ide_atareg.h:
make define work for both gnuc and suncc
src/dev/io_device.hh:
add dummy returns where approirate
src/dev/pcidev.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.hh:
src/mem/dram.cc:
src/mem/packet.cc:
src/mem/port.cc:
include cstring for string ops
src/dev/sparc/mm_disk.cc:
add dummy return where appropriate
include cstring for string ops
src/mem/cache/miss/blocking_buffer.hh:
src/mem/port.hh:
Add dummy return where appropriate
src/mem/cache/tags/iic.cc:
cast hastSets to double for log() call
src/mem/physical.cc:
cast pmemAddr to char* for munmap
src/sim/byteswap.hh:
make define work for suncc and gnuc
H A Dstatic_inst.hh5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
5036:f9174c026b7f Thu Aug 30 15:16:00 EDT 2007 Miles Kaufmann <milesck@eecs.umich.edu> Fix miscellaneous small typos.
4963:ba55203d1bdc Wed Aug 08 14:54:00 EDT 2007 Vincentius Robby <acolyte@umich.edu> Port, StaticInst: Revert unnecessary changes.
4962:4e939f4629c3 Wed Aug 08 14:18:00 EDT 2007 Vincentius Robby <acolyte@umich.edu> alpha: Make the TLB cache to actually work.
Improve MRU checking for StaticInst, Bus, TLB
4956:fc30658d75de Sat Aug 04 14:25:00 EDT 2007 Vincentius Robby <acolyte@umich.edu> StaticInst: Fix decode cache initialization. Cache functionality was negated.
4828:768d4cf6b0dc Tue Jul 31 20:34:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add a flag to indicate an instruction triggers a syscall in SE mode.
4572:5499df089a6c Thu Jun 14 16:52:00 EDT 2007 Vincentius Robby <acolyte@umich.edu> Modified instruction decode method.
Make code compatible with new decode method.

src/arch/alpha/remote_gdb.cc:
src/cpu/base_dyn_inst_impl.hh:
src/cpu/exetrace.cc:
src/cpu/simple/base.cc:
Make code compatible with new decode method.
src/cpu/static_inst.cc:
src/cpu/static_inst.hh:
Modified instruction decode method.
4539:6eeeea62b7c4 Tue Jun 12 12:21:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make microOp vs microop and macroOp vs macroop capitilization consistent.

src/arch/x86/isa/macroop.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code.
src/arch/x86/isa/microops/base.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation.
4182:5b2c0d266107 Wed Mar 14 22:47:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the predecoder an object with it's own switched header file. Start adding predecoding functionality to x86.

src/arch/SConscript:
src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/cpu/base.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/static_inst.hh:
src/arch/alpha/predecoder.hh:
src/arch/mips/predecoder.hh:
src/arch/sparc/predecoder.hh:
Make the predecoder an object with it's own switched header file.
4181:6edaeff44647 Tue Mar 13 12:13:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Replaced makeExtMI with predecode.
Removed the getOpcode function from StaticInst which only made sense for Alpha.
Started implementing the x86 predecoder.
/gem5/src/arch/mips/
H A Dfaults.hh5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
5224:0e354459fb8a Wed Nov 14 06:24:00 EST 2007 Korey Sewell <ksewell@umich.edu> Get MIPS_SE actually working again by actually by fixing TLB stuff and running hello world
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
5004:7d94cedab264 Sun Aug 26 23:33:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address translation: Make the page table more flexible.
The page table now stores actual page table entries. It is still a templated
class here, but this will be corrected in the near future.
4695:a63378aed062 Wed Jul 18 19:09:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make name, isMachineCheckFault, and isAlignmentFault const.
4661:44458219add1 Fri Jun 22 19:03:00 EDT 2007 Korey Sewell <ksewell@umich.edu> mips import pt. 1

src/arch/mips/SConscript:
"mips import pt.1".
4183:3d19c1d46946 Wed Mar 07 15:04:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Move the magic m5 PageTableFault into sim/faults.[hh,cc] since it's the same across all architectures.
H A Dlocked_mem.hh5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
4661:44458219add1 Fri Jun 22 19:03:00 EDT 2007 Korey Sewell <ksewell@umich.edu> mips import pt. 1

src/arch/mips/SConscript:
"mips import pt.1".
/gem5/src/arch/sparc/isa/
H A Dbase.isa5202:ff56fa8c2091 Wed Oct 31 21:04:00 EDT 2007 Steve Reinhardt <stever@gmail.com> String constant const-ness changes to placate g++ 4.2.
Also some bug fixes in MIPS ISA uncovered by g++ warnings
(Python string compares don't work in C++!).
4362:95e5f28ce484 Tue Apr 10 20:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Create a filter and a union to translate the SPARC instruction implementations from using doubles to using concatenated singles.
4172:141705d83494 Wed Mar 07 15:04:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
4004:d551cf1bba0d Tue Jan 30 16:12:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Implemented fbfss and fbpfcc instructions, and cleaned up branch code a little.

src/arch/sparc/isa/base.isa:
Added passesFpCondition function to help with fbfcc and fbpfcc instructions.
src/arch/sparc/isa/decoder.isa:
Added fbfcc and fbpfcc instructions, and cleaned up branch code slightly.
src/arch/sparc/isa/formats/branch.isa:
Minor cleanup.
3980:9bcb2a2e9bb8 Sat Jan 27 01:59:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/newmem

src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/system.cc:
Hand Merge
3978:739bc3a17929 Sat Jan 27 01:47:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Fixed up printReg so that control registers are printed by name. This is possible now becauase Ctrl_Base_DepTag gets added into control register numbers.
3931:de791fa53d04 Fri Jan 26 18:57:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Make Sparc traceflag even more chatty
some fixes to fp instructions to use the single precision registers
if this is an fp op emit fp check code
add fpregs to m5legion struct

src/arch/sparc/floatregfile.cc:
Make Sparc traceflag even more chatty
src/arch/sparc/isa/base.isa:
add code to check if the fpu is enabled
src/arch/sparc/isa/decoder.isa:
some fixes to fp instructions to use the single precision registers
fix smul again
fix subc/subcc/subccc condition code setting
src/arch/sparc/isa/formats/basic.isa:
src/arch/sparc/isa/formats/mem/util.isa:
if this is an fp op emit fp check code
src/cpu/exetrace.cc:
check fp regs as well as int regs
src/cpu/m5legion_interface.h:
add fpregs to m5legion struct
/gem5/src/arch/mips/isa/
H A Ddecoder.isa5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers
5250:42577371ff31 Thu Nov 15 03:10:00 EST 2007 Korey Sewell <ksewell@umich.edu> Get MIPS simple regression working. Take out unecessary functions "setShadowSet", "CacheOp"
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
4828:768d4cf6b0dc Tue Jul 31 20:34:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add a flag to indicate an instruction triggers a syscall in SE mode.
4675:598d4c33c38d Fri Jun 29 15:13:00 EDT 2007 Korey Sewell <ksewell@umich.edu> fix store instructions, pass fast/quick Atomic/TimingSimpleCPU regressions...

src/arch/mips/isa/decoder.isa:
commment out deret instruction for now...
src/arch/mips/isa/formats/fp.isa:
edit fp format
src/arch/mips/isa/formats/mem.isa:
fix for basic store instructions
4661:44458219add1 Fri Jun 22 19:03:00 EDT 2007 Korey Sewell <ksewell@umich.edu> mips import pt. 1

src/arch/mips/SConscript:
"mips import pt.1".
4172:141705d83494 Wed Mar 07 15:04:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> *MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
4056:f8f1dffc5913 Tue Feb 13 11:09:00 EST 2007 Steve Reinhardt <stever@eecs.umich.edu> Update MIPS ISA description to work with new write result interface
for store conditional.
3976:b701138cd125 Thu Jan 25 01:13:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Fixed a warning that was breaking compilation.
/gem5/src/kern/linux/
H A Devents.cc4826:259b996a6da6 Wed Aug 01 16:59:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Arguments: Get rid of duplicate code for the Arguments class in each architecture.
Move the argument files to src/sim and add a utility.cc file with a function
getArguments() that returns the given argument in the architecture specific fashion.
getArguments() was getArg() is the architecture specific Argument class and has had
all magic numbers replaced with meaningful constants. Also add a function to the
Argument class for testing if an argument is NULL.
4429:74351f86f49a Tue May 01 18:14:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> change the way dprintf works so the cache accesses required to fulfill the dprintf aren't show in between the Cycle: name:
printing and the actual formatted string being printed
4424:9034cc0615be Mon Apr 30 22:49:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> always skip the debugprintf function (DebugPrintf traceflag shouldn't matter). Otherwise, when you turn on debugprintf alters the execution
/gem5/src/arch/sparc/linux/
H A Dprocess.hh5154:7e6431213487 Tue Oct 16 21:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the process objects use the Params structs in their constructors, and use a limit to check if access are on the stack.
4188:6a9ac3b35285 Fri Mar 09 17:14:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Split the syscall table, SPARC specific syscall implementations, and the 32 bit syscall table into it's own file. Corrected problems with the stat structure. These should be tested on 64 bit x86 and SPARC machines.
4111:65fffcb4fae9 Wed Feb 28 11:36:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Make trap instructions always generate TrapInstruction Fault objects which call into the Process object to handle system calls. Refactored the Process objects, and move the handler code into it's own file, and add some syscalls which are used in a natively compiled hello world. Software traps with trap number 3 (not syscall number 3) are supposed to cause the register windows to be flushed but are ignored right now. Finally, made uname for SPARC report a 2.6.12 kernel which is what m22-018.pool happens to be running.
/gem5/src/base/
H A Dcompiler.hh4964:7a8a941f4059 Fri Aug 10 16:14:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Bus: Only call end() on an stl object once in a loop
3940:b87f85bb4275 Sat Jan 27 15:38:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> While I'm waiting for legion to run make m5 compile with a few more compilers

SConstruct:
src/SConscript:
Add flags for Intel CC while i'm at it
src/base/compiler.hh:
the _Pragma stuff needst to be called this way unless someone happens to have a cleaner way
src/base/cprintf_formats.hh:
add std:: where appropriate
src/base/statistics.hh:
use this->map since icc was getting confused about std::map vs the locally defined map
src/cpu/static_inst.hh:
Add some more dummy returns where needed
src/mem/packet.hh:
add more dummy returns where needed
src/sim/host.hh:
use limits to come up with max tick
3938:470d8d731f42 Fri Jan 26 19:00:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> forgot to include this file
/gem5/configs/common/
H A DCaches.py4965:ad0e792a5c78 Fri Aug 10 16:14:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> DMA: Add IOCache and fix bus bridge to optionally only send requests one
way so a cache can handle partial block requests for i/o devices.
4876:a18cedc19da5 Sat Jun 30 20:59:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of remaining traces of obsolete CoherenceProtocol object.
4444:0648bdc8d1c9 Thu May 10 18:24:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> remove hit_latency and make latency do the right thing
set the latency parameter in terms of a latency
add caches to tsunami-simple configs

configs/common/Caches.py:
tests/configs/memtest.py:
tests/configs/o3-timing-mp.py:
tests/configs/o3-timing.py:
tests/configs/simple-atomic-mp.py:
tests/configs/simple-timing-mp.py:
tests/configs/simple-timing.py:
set the latency parameter in terms of a latency
configs/common/FSConfig.py:
give the bridge a default latency too
src/mem/cache/cache_builder.cc:
src/python/m5/objects/BaseCache.py:
remove hit_latency and make latency do the right thing
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-atomic.py:
tests/configs/tsunami-simple-timing-dual.py:
tests/configs/tsunami-simple-timing.py:
add caches to tsunami-simple configs

Completed in 287 milliseconds

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