1/*
2 * Copyright (c) 2011, 2016 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2004-2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Nathan Binkert
41 *          Ali Saidi
42 */
43
44#include "kern/linux/events.hh"
45
46#include <sstream>
47
48#include "arch/utility.hh"
49#include "base/output.hh"
50#include "base/trace.hh"
51#include "cpu/base.hh"
52#include "cpu/thread_context.hh"
53#include "debug/DebugPrintf.hh"
54#include "kern/linux/helpers.hh"
55#include "kern/linux/printk.hh"
56#include "kern/system_events.hh"
57#include "sim/arguments.hh"
58#include "sim/pseudo_inst.hh"
59#include "sim/system.hh"
60
61namespace Linux {
62
63void
64DebugPrintkEvent::process(ThreadContext *tc)
65{
66    if (DTRACE(DebugPrintf)) {
67        std::stringstream ss;
68        Arguments args(tc);
69        Printk(ss, args);
70        StringWrap name(tc->getSystemPtr()->name() + ".dprintk");
71        DPRINTFN("%s", ss.str());
72    }
73    SkipFuncEvent::process(tc);
74}
75
76void
77UDelayEvent::process(ThreadContext *tc)
78{
79    int arg_num  = 0;
80
81    // Get the time in native size
82    uint64_t time = TheISA::getArgument(tc, arg_num,  (uint16_t)-1, false);
83
84    // convert parameter to ns
85    if (argDivToNs)
86        time /= argDivToNs;
87
88    time *= argMultToNs;
89
90    SkipFuncEvent::process(tc);
91
92    // Currently, only ARM full-system simulation uses UDelayEvents to skip
93    // __delay and __loop_delay functions. One form involves setting quiesce
94    // time to 0 with the assumption that quiesce will not happen. To avoid
95    // the quiesce handling in this case, only execute the quiesce if time > 0.
96    if (time > 0) {
97        PseudoInst::quiesceNs(tc, time);
98    }
99}
100
101void
102DmesgDumpEvent::process(ThreadContext *tc)
103{
104    StringWrap name(tc->getCpuPtr()->name() + ".dmesg_dump_event");
105
106    inform("Dumping kernel dmesg buffer to %s...\n", fname);
107    OutputStream *os = simout.create(fname);
108    dumpDmesg(tc, *os->stream());
109    simout.close(os);
110
111    warn(descr());
112}
113
114void
115KernelPanicEvent::process(ThreadContext *tc)
116{
117    StringWrap name(tc->getCpuPtr()->name() + ".dmesg_dump_event");
118
119    inform("Dumping kernel dmesg buffer to %s...\n", fname);
120    OutputStream *os = simout.create(fname);
121    dumpDmesg(tc, *os->stream());
122    simout.close(os);
123
124    panic(descr());
125}
126
127} // namespace linux
128