dev: Generalize the x86 int source/sink pins.

Sink pins are now templated based on the underlying device types, and
the pins themselves are based on the new, generalized Port mechanism.

Change-Id: I09c678c56f6eb6b4a167c12f221ae0241fe99c2d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20700
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Include the platform base class even in NULL_ISA builds.

These classes don't have any ISA specific aspects.

Change-Id: Ifefb12d23e4aee8e3fd56f0a1eb3d9ad00e733a0
Reviewed-on: https://gem5-review.googlesource.com/c/13467
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

ps2: Unify constant names

Move ps2.hh to dev/ps2/types.hh and update the device models to
consistently use well-known constants from this header.

Change-Id: Iadfdc774495957beb82f3d341107b1e9232ffd4c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9770
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

dev: Move generic serial devices to src/dev/serial

Change-Id: I104227fc460f8b561e7375b329a541c1fce881b2
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4291
Reviewed-by: Gabe Black <gabeblack@google.com>

dev: Refactor UART->Terminal interface

The UART models currently assume that they are always wired to a
terminal. While true at the moment, this isn't necessarily a valid
assumption. This change introduces the SerialDevice class that defines
the interface for serial devices. Currently, Terminal is the only
class that implements this interface.

Change-Id: I74fefafbbaf5ac1ec0d4ec0b5a0f4b246fdad305
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/4289
Reviewed-by: Gabe Black <gabeblack@google.com>

dev: Include DmaDevice in NULL builds

Builds for the NULL ISA include Device.py, which contains the Python
declaration of DmaDevice, but don't include the actual C++
implementation. Add dma_device.cc to the NULL build to the Python and
C++ worlds consistent again.

Change-Id: I47a57181a1f4d5a7276467678bf16fbc7f161681
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>

dev: Move storage devices to src/dev/storage/

Move the IDE controller and the disk implementations to
src/dev/storage.

dev: Move network devices to src/dev/net/

dev: Move i2c functionality to src/dev/i2c/

dev: Move the CopyEngine class to src/dev/pci

dev: Move existing PCI device functionality to src/dev/pci

Move pcidev.(hh|cc) to src/dev/pci/device.(hh|cc) and update existing
devices to use the new header location. This also renames the PCIDEV
debug flag to have a capitalization that is consistent with the PCI
host and other devices.

dev: Rewrite PCI host functionality

The gem5's current PCI host functionality is very ad hoc. The current
implementations require PCI devices to be hooked up to the
configuration space via a separate configuration port. Devices query
the platform to get their config-space address range. Un-mapped parts
of the config space are intercepted using the XBar's default port
mechanism and a magic catch-all device (PciConfigAll).

This changeset redesigns the PCI host functionality to improve code
reuse and make config-space and interrupt mapping more
transparent. Existing platform code has been updated to use the new
PCI host and configured to stay backwards compatible (i.e., no
guest-side visible changes). The current implementation does not
expose any new functionality, but it can easily be extended with
features such as automatic interrupt mapping.

PCI devices now register themselves with a PCI host controller. The
host controller interface is defined in the abstract base class
PciHost. Registration is done by PciHost::registerDevice() which takes
the device, its bus position (bus/dev/func tuple), and its interrupt
pin (INTA-INTC) as a parameter. The registration interface returns a
PciHost::DeviceInterface that the PCI device can use to query memory
mappings and signal interrupts.

The host device manages the entire PCI configuration space. Accesses
to devices decoded into the devices bus position and then forwarded to
the correct device.

Basic PCI host functionality is implemented in the GenericPciHost base
class. Most platforms can use this class as a basic PCI controller. It
provides the following functionality:

* Configurable configuration space decoding. The number of bits
dedicated to a device is a prameter, making it possible to support
both CAM, ECAM, and legacy mappings.

* Basic interrupt mapping using the interruptLine value from a
device's configuration space. This behavior is the same as in the
old implementation. More advanced controllers can override the
interrupt mapping method to dynamically assign host interrupts to
PCI devices.

* Simple (base + addr) remapping from the PCI bus's address space to
physical addresses for PIO, memory, and DMA.

dev: Implement a simple display timing generator

Timing generator for a pixel-based display. The timing generator is
intended for display processors driving a standard rasterized
display. The simplest possible display processor needs to derive from
this class and override the nextPixel() method to feed the display
with pixel data.

Pixels are ordered relative to the top left corner of the
display. Scan lines appear in the following order:

* Vertical Sync (starting at line 0)
* Vertical back porch
* Visible lines
* Vertical front porch

Pixel order within a scan line:

* Horizontal Sync
* Horizontal Back Porch
* Visible pixels
* Horizontal Front Porch

All events in the timing generator are automatically suspended on a
drain() request and restarted on drainResume(). This is conceptually
equivalent to clock gating when the pixel clock while the system is
draining. By gating the pixel clock, we prevent display controllers
from disturbing a memory system that is about to drain.

dev: add support for multi gem5 runs

Multi gem5 is an extension to gem5 to enable parallel simulation of a
distributed system (e.g. simulation of a pool of machines
connected by Ethernet links). A multi gem5 run consists of seperate gem5
processes running in parallel (potentially on different hosts/slots on
a cluster). Each gem5 process executes the simulation of a component of the
simulated distributed system (e.g. a multi-core board with an Ethernet NIC).

The patch implements the "distributed" Ethernet link device
(dev/src/multi_etherlink.[hh.cc]). This device will send/receive
(simulated) Ethernet packets to/from peer gem5 processes. The interface
to talk to the peer gem5 processes is defined in dev/src/multi_iface.hh and
in tcp_iface.hh.

There is also a central message server process (util/multi/tcp_server.[hh,cc])
which acts like an Ethernet switch and transfers messages among the gem5 peers.

A multi gem5 simulations can be kicked off by the util/multi/gem5-multi.sh
wrapper script.

Checkpoints are supported by multi-gem5. The checkpoint must be
initiated by a single gem5 process. E.g., the gem5 process with rank 0
can take a checkpoint from the bootscript just before it invokes
'mpirun' to launch an MPI test. The message server process will notify
all the other peer gem5 processes and make them take a checkpoint, too
(after completing a global synchronisation to ensure that there are no
inflight messages among gem5).

dev: Add support for i2c devices

This patch adds an I2C bus and base device. I2C is used to connect a
variety of sensors, and this patch serves as a starting point to
enable a range of I2C devices.

dev: Include basic devices in NULL ISA build

This patch enbles use of the basic PIO devices as part of the NULL
build. Although it might seem counter intuitive to have a PIO device
without being able to execute a driver, this change enables us to
break a device class hierarchy into an ISA-agnostic part, and an
ISA-specific part, without requiring multiple-inheritance. The
ISA-agnostic base class is a PIO device, but does not make use of the
port.

arch: Resurrect the NOISA build target and rename it NULL

This patch makes it possible to once again build gem5 without any
ISA. The main purpose is to enable work around the interconnect and
memory system without having to build any CPU models or device models.

The regress script is updated to include the NULL ISA target. Currently
no regressions make use of it, but all the testers could (and perhaps
should) transition to it.

DMA: Split the DMA device and IO device into seperate files

This patch moves the DMA device to its own set of files, splitting it
from the IO device. There are no behavioural changes associated with
this patch.

The patch also grabs the opportunity to do some very minor tidying up,
including some white space removal and pruning some redundant
parameters.

Besides the immediate benefits of the separation-of-concerns, this
patch also makes upcoming changes more streamlined as it split the
devices that are only slaves and the DMA device that also acts as a
master.

SE/FS: Build the devices in SE mode.

scons: rename TraceFlags to DebugFlags

VNC/ARM: Use VNC server and add support to boot into X11

SCons: Support building without an ISA

CopyEngine: Implement a I/OAT-like copy engine.

IGbE: Add support for newer 8257x based Intel NICs

Ethernet: share statistics between all ethernet devices and apply some
of those statistics to the e1000 model.

Rename SimConsole to Terminal since it makes more sense

Dev: Seperate the 8254 timer from tsunami and use it in that and the PC.

Devices: Separate out the MC146818 RTC so both Alpha and X86 can use it.

Traceflags: Add SCons function to created a traceflag instead of having one file with them all.

Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.

Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.

add all the registers we'll need to support for the Intel GbE device and support enough functionality make the driver think
the device is there, and in good working order.

src/dev/SConscript:
add intel gbe to the dev SCons file
src/dev/i8254xGBe.cc:
src/dev/i8254xGBe.hh:
src/dev/i8254xGBe_defs.hh:
use new manner of registers and implement all device registers that are touched through boot and ifup

Rework the way SCons recurses into subdirectories, making it
automatic. The point is that now a subdirectory can be added
to the build process just by creating a SConscript file in it.
The process has two passes. On the first pass, all subdirs
of the root of the tree are searched for SConsopts files.
These files contain any command line options that ought to be
added for a particular subdirectory. On the second pass,
all subdirs of the src directory are searched for SConscript
files. These files describe how to build any given subdirectory.
I have added a Source() function. Any file (relative to the
directory in which the SConscript resides) passed to that
function is added to the build. Clean up everything to take
advantage of Source().
function is added to the list of files to be built.

Get rid of pcifake.cc and tsunami_fake.cc to go with the merged default devices.

Moved the tsunami devices into the dev/alpha directory. Other devices "generic" devices are dependent on some of those files. That will either need to change, or most likely those devices will have to be considered architecture dependent.

Created seperate SConscript for the dev directory. Made subdirectories for Alpha and SPARC and put SConscripts in them.