Searched hist:2007 (Results 376 - 400 of 895) sorted by relevance

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/gem5/src/arch/x86/isa/insts/simd64/integer/data_reordering/
H A Dunpack_and_interleave.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/x87/load_constants/
H A Dload_0_1_or_pi.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
H A Dload_logarithm.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/isa/insts/x87/transcendental_functions/
H A Dtrigonometric_functions.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/linux/
H A Dsystem.hh5299:e61b9f2a9732 Sun Dec 02 02:09:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Move startup code to the system object to initialize a Linux system.
H A Dlinux.hh4866:9adc60769aed Sat Aug 04 23:18:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make the open flags correct.
4822:14be2bcab3b3 Mon Jul 30 18:43:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: __pad0 should be a 4 byte pad, not a 4 long array of 4 byte pads.
4815:137ad0e13d3a Mon Jul 30 16:31:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Fix up the stat structure. This probably still isn't right.
4759:60e820a327db Tue Jul 24 18:42:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Add a tgt_iovec structure to support writev, change the name of X86Linux to X86Linux64, add some syscalls.
4166:ecebe3ac19b4 Tue Mar 06 10:42:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Get X86 to load an elf and start a process for it.

src/arch/x86/SConscript:
Add in process source files.
src/arch/x86/isa_traits.hh:
Replace magic constant numbers with the x86 register names.
src/arch/x86/miscregfile.cc:
Make clear the miscreg file succeed. There aren't any misc regs, so clearing them is very easy.
src/arch/x86/process.hh:
An X86 process class.
src/base/loader/elf_object.cc:
Add in code to recognize x86 as an architecture.
src/base/traceflags.py:
Add an x86 traceflag
src/sim/process.cc:
Add in code to create an x86 process.
src/arch/x86/intregs.hh:
A file which declares names for the integer register indices.
src/arch/x86/linux/linux.cc:
src/arch/x86/linux/linux.hh:
A very simple translation of SPARC's linux.cc and linux.hh. It's probably not correct for x86, but it might not be correct for SPARC either.
src/arch/x86/linux/process.cc:
src/arch/x86/linux/process.hh:
An x86 linux process. The syscall table is split out into it's own file.
src/arch/x86/linux/syscalls.cc:
The x86 Linux syscall table and the uname function.
src/arch/x86/process.cc:
The x86 process base class.
tests/test-progs/hello/bin/x86/linux/hello:
An x86 hello world test binary.
/gem5/src/base/
H A Dfenv.hh4394:dbaff14bb974 Sat Apr 21 17:50:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> create base/fenv.c to standerdize fenv across platforms. It's a c file and not a cpp file because c99
(which defines fenv) doesn't necessarily extend to c++ and it is a problem with solaris. If really
desired this could wrap the ieeefp interface found in bsd* as well, but I see no need at the moment.

src/arch/alpha/isa/fp.isa:
src/arch/sparc/isa/formats/basic.isa:
use m5_fesetround()/m5_fegetround() istead of fenv interface directly
src/arch/sparc/isa/includes.isa:
use base/fenv instead of fenv directly
src/base/SConscript:
add fenv to sconscript
src/base/fenv.hh:
src/base/random.cc:
m5 implementation to standerdize fenv across platforms.
/gem5/tests/test-progs/hello/bin/x86/linux/
H A Dhello4166:ecebe3ac19b4 Tue Mar 06 10:42:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Get X86 to load an elf and start a process for it.

src/arch/x86/SConscript:
Add in process source files.
src/arch/x86/isa_traits.hh:
Replace magic constant numbers with the x86 register names.
src/arch/x86/miscregfile.cc:
Make clear the miscreg file succeed. There aren't any misc regs, so clearing them is very easy.
src/arch/x86/process.hh:
An X86 process class.
src/base/loader/elf_object.cc:
Add in code to recognize x86 as an architecture.
src/base/traceflags.py:
Add an x86 traceflag
src/sim/process.cc:
Add in code to create an x86 process.
src/arch/x86/intregs.hh:
A file which declares names for the integer register indices.
src/arch/x86/linux/linux.cc:
src/arch/x86/linux/linux.hh:
A very simple translation of SPARC's linux.cc and linux.hh. It's probably not correct for x86, but it might not be correct for SPARC either.
src/arch/x86/linux/process.cc:
src/arch/x86/linux/process.hh:
An x86 linux process. The syscall table is split out into it's own file.
src/arch/x86/linux/syscalls.cc:
The x86 Linux syscall table and the uname function.
src/arch/x86/process.cc:
The x86 process base class.
tests/test-progs/hello/bin/x86/linux/hello:
An x86 hello world test binary.
/gem5/src/arch/alpha/
H A Dpagetable.hh5184:8782de2949e5 Thu Oct 25 22:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> TLB: Fix serialization issues with the tlb entries and make the page table store the process, not the system.
5015:6406d713c713 Mon Aug 27 21:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Alpha: Fixes to get alpha to compile again.
5004:7d94cedab264 Sun Aug 26 23:33:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address translation: Make the page table more flexible.
The page table now stores actual page table entries. It is still a templated
class here, but this will be corrected in the near future.
3895:5e8f0e3aeca2 Mon Jan 08 20:50:00 EST 2007 Lisa Hsu <hsul@eecs.umich.edu> pagetable.hh:
small fix so ALPHA_FS will build on macs
interrupts.hh:
small fix for alpha compile

src/arch/alpha/interrupts.hh:
small fix for alpha compile
src/arch/alpha/pagetable.hh:
small fix so ALPHA_FS will build on macs
H A DSConscript5217:bb810bb8ca2d Thu Nov 08 10:46:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> CPU: Add function to explictly compare thread contexts after copying.
5192:582e583f8e7e Wed Oct 31 01:21:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Traceflags: Add SCons function to created a traceflag instead of having one file with them all.
4997:e7380529bd2d Sun Aug 26 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
4826:259b996a6da6 Wed Aug 01 16:59:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Arguments: Get rid of duplicate code for the Arguments class in each architecture.
Move the argument files to src/sim and add a utility.cc file with a function
getArguments() that returns the given argument in the architecture specific fashion.
getArguments() was getArg() is the architecture specific Argument class and has had
all magic numbers replaced with meaningful constants. Also add a function to the
Argument class for testing if an argument is NULL.
4486:aaeb03a8a6e1 Sun May 27 22:21:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.
4202:f7a05daec670 Sun Mar 11 03:00:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Rework the way SCons recurses into subdirectories, making it
automatic. The point is that now a subdirectory can be added
to the build process just by creating a SConscript file in it.
The process has two passes. On the first pass, all subdirs
of the root of the tree are searched for SConsopts files.
These files contain any command line options that ought to be
added for a particular subdirectory. On the second pass,
all subdirs of the src directory are searched for SConscript
files. These files describe how to build any given subdirectory.
I have added a Source() function. Any file (relative to the
directory in which the SConscript resides) passed to that
function is added to the build. Clean up everything to take
advantage of Source().
function is added to the list of files to be built.
/gem5/src/arch/x86/isa/decoder/
H A Dx87.isa5162:5af26efb306e Fri Oct 19 01:39:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make "Inst" the default format instead of WarnUnimpl for one byte opcodes.
5084:675cb680830f Wed Sep 19 21:28:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement the fld, fst, and fstp instructions.
4827:d4ea1bbfdbc3 Tue Jul 31 17:55:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Add operand type information to the fnstcw and fldw instruction placeholders.
These are the only floating point instructions that get used in my simple hello world test. These instructions are for setting up the floating point control register. Their not being implemented doesn't affect anything because floating point isn't used.
4825:93a992aa87f6 Mon Jul 30 20:54:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Add decoding for x87 floating point.
/gem5/src/dev/mips/
H A DSConscript5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
/gem5/src/arch/mips/linux/
H A Dlinux.hh5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
4661:44458219add1 Fri Jun 22 19:03:00 EDT 2007 Korey Sewell <ksewell@umich.edu> mips import pt. 1

src/arch/mips/SConscript:
"mips import pt.1".
4131:660ebc4994a9 Sun Mar 04 22:26:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Don't use the exact same name as a system header #define
H A Dprocess.hh5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
5154:7e6431213487 Tue Oct 16 21:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the process objects use the Params structs in their constructors, and use a limit to check if access are on the stack.
4661:44458219add1 Fri Jun 22 19:03:00 EDT 2007 Korey Sewell <ksewell@umich.edu> mips import pt. 1

src/arch/mips/SConscript:
"mips import pt.1".
/gem5/src/arch/x86/isa/insts/x87/control/
H A Dsave_and_restore_x87_environment.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/arch/x86/
H A Dpagetable.hh5237:6c819dbe8045 Mon Nov 12 17:38:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Work on the page table walker, TLB, and related faults.
5184:8782de2949e5 Thu Oct 25 22:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> TLB: Fix serialization issues with the tlb entries and make the page table store the process, not the system.
5124:3d8c50376609 Wed Oct 03 02:00:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Start implementing the x86 tlb which will handle segmentation permission and limit checks and paging.
4159:a3cc632b33d8 Mon Mar 05 12:56:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Add some new source files.
H A Dutility.hh5135:6ae576eada5c Sun Oct 07 21:10:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Make initCPU and startupCPU do something basic.
5086:e7913ffb379d Mon Sep 24 20:39:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Get X86_FS to compile.
4587:2c9a2534a489 Tue Jun 19 10:18:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Get rid of the immediate and displacement components of the EmulEnv struct and use them directly out of the instruction. The extra copies are conceptually realistic but are just innefficient as implemented. Also don't use the zeroeth microcode register for general storage since it's now the zero register, and implement a load and a store microops.
4569:8720f7848610 Thu Jun 14 09:50:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Put the mode in the ExtMachInst.
4342:a9ff632aa660 Fri Apr 06 11:19:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Clean up the code a little, fix (I think) a perceived problem with immediate sizes, and sign extend the 32-bit-acting-like-64-bit-immediates.
4334:15815fd6b30c Wed Apr 04 10:27:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Made x86 ExtMachInsts distinguishable from each other by defining a real == and a real hash function.
4241:0a4218540c6d Wed Mar 14 23:17:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Compile fix
4240:cde9d7751cce Wed Mar 14 22:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

src/arch/mips/utility.hh:
src/arch/x86/SConscript:
Hand merge
4194:af4f6022394b Fri Mar 09 16:56:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> implement ipi stufff for SPARC

src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/arch/x86/utility.hh:
add hook for system to startup the cpu or not... in the case of FS sparc, only the first cpu would get spunup.. the rest sit in an idle state until they get an ipi
src/arch/sparc/isa/decoder.isa:
handle writable bits of strandstatus register in miscregfile
src/arch/sparc/miscregfile.hh:
some constants for the strand status register
src/arch/sparc/ua2005.cc:
properly implement the strand status register
src/dev/sparc/iob.cc:
implement ipi generation properly
src/sim/system.cc:
call into the ISA to start the CPU (or not)
4182:5b2c0d266107 Wed Mar 14 22:47:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make the predecoder an object with it's own switched header file. Start adding predecoding functionality to x86.

src/arch/SConscript:
src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/cpu/base.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/static_inst.hh:
src/arch/alpha/predecoder.hh:
src/arch/mips/predecoder.hh:
src/arch/sparc/predecoder.hh:
Make the predecoder an object with it's own switched header file.
/gem5/src/arch/x86/isa/insts/general_purpose/
H A Dcache_and_memory_management.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/dev/
H A DBadDevice.py4486:aaeb03a8a6e1 Sun May 27 22:21:00 EDT 2007 Nathan Binkert <binkertn@umich.edu> Move SimObject python files alongside the C++ and fix
the SConscript files so that only the objects that are
actually available in a given build are compiled in.
Remove a bunch of files that aren't used anymore.
/gem5/src/kern/linux/
H A Dprintk.cc5202:ff56fa8c2091 Wed Oct 31 21:04:00 EDT 2007 Steve Reinhardt <stever@gmail.com> String constant const-ness changes to placate g++ 4.2.
Also some bug fixes in MIPS ISA uncovered by g++ warnings
(Python string compares don't work in C++!).
4826:259b996a6da6 Wed Aug 01 16:59:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> Arguments: Get rid of duplicate code for the Arguments class in each architecture.
Move the argument files to src/sim and add a utility.cc file with a function
getArguments() that returns the given argument in the architecture specific fashion.
getArguments() was getArg() is the architecture specific Argument class and has had
all magic numbers replaced with meaningful constants. Also add a function to the
Argument class for testing if an argument is NULL.
4429:74351f86f49a Tue May 01 18:14:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> change the way dprintf works so the cache accesses required to fulfill the dprintf aren't show in between the Cycle: name:
printing and the actual formatted string being printed
4046:ef34b290091e Sat Feb 10 18:14:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Clean up tracing stuff more, get rid of the trace log since
its not all that useful. Fix a few bugs with python/C++
integration.
/gem5/src/arch/x86/isa/insts/simd128/floating_point/data_transfer/
H A Dmove_non_temporal.py5081:2ccce8600a9d Wed Sep 19 21:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.
/gem5/src/dev/sparc/
H A Dmm_disk.cc4918:3214e3694fb2 Fri Jul 27 02:15:00 EDT 2007 Nathan Binkert <nate@binkert.org> Merge python and x86 changes with cache branch
4870:fcc39d001154 Sat Jun 30 13:16:00 EDT 2007 Steve Reinhardt <stever@eecs.umich.edu> Get rid of Packet result field. Error responses are
now encoded in cmd field.
4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
4198:4ada78de338c Sat Mar 10 15:21:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Compilation fix
4011:e6899d7ca5b1 Tue Feb 06 15:52:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> more fp fixes
fix unaligned accesses in mmaped disk device

src/arch/sparc/isa/decoder.isa:
get (ld|st)fsr ops working right. In reality the fp enable check needs to go higher up in the emitted code
src/arch/sparc/isa/formats/basic.isa:
move the cexec into the aexec field
src/cpu/exetrace.cc:
copy the exception state from legion when we get it wrong. We aren't going to get it right without an fp emulation layer
src/dev/sparc/mm_disk.cc:
src/dev/sparc/mm_disk.hh:
fix unaligned accesses in the memory mapped disk device
3918:1f9a98d198e8 Fri Jan 26 18:48:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make our code a little more standards compliant
pretty close to compiling w/ suns compiler

briefly:
add dummy return after panic()/fatal()
split out flags by compiler vendor
include cstring and cmath where appropriate
use std namespace for string ops

SConstruct:
Add code to detect compiler and choose cflags based on detected compiler
Fix zlib check to work with suncc
src/SConscript:
split out flags by compiler vendor
src/arch/sparc/isa/decoder.isa:
use correct namespace for sqrt
src/arch/sparc/isa/formats/basic.isa:
add dummy return around panic
src/arch/sparc/isa/formats/integerop.isa:
use correct namespace for stringops
src/arch/sparc/isa/includes.isa:
include cstring and cmath where appropriate
src/arch/sparc/isa_traits.hh:
remove dangling comma
src/arch/sparc/system.cc:
dummy return to make sun cc front end happy
src/arch/sparc/tlb.cc:
src/base/compression/lzss_compression.cc:
use std namespace for string ops
src/arch/sparc/utility.hh:
no reason to say something is unsigned unsigned int
src/base/compression/null_compression.hh:
dummy returns to for suncc front end
src/base/cprintf.hh:
use standard variadic argument syntax instead of gnuc specefic renaming
src/base/hashmap.hh:
don't need to define hash for suncc
src/base/hostinfo.cc:
need stdio.h for sprintf
src/base/loader/object_file.cc:
munmap is in std namespace not null
src/base/misc.hh:
use M5 generic noreturn macros
use standard variadic macro __VA_ARGS__
src/base/pollevent.cc:
we need file.h for file flags
src/base/random.cc:
mess with include files to make suncc happy
src/base/remote_gdb.cc:
malloc memory for function instead of having a non-constant in an array size
src/base/statistics.hh:
use std namespace for floor
src/base/stats/text.cc:
include math.h for rint (cmath won't work)
src/base/time.cc:
use suncc version of ctime_r
src/base/time.hh:
change macro to work with both gcc and suncc
src/base/timebuf.hh:
include cstring from memset and use std::
src/base/trace.hh:
change variadic macros to be normal format
src/cpu/SConscript:
add dummy returns where appropriate
src/cpu/activity.cc:
include cstring for memset
src/cpu/exetrace.hh:
include cstring fro memcpy
src/cpu/simple/base.hh:
add dummy return for panic
src/dev/baddev.cc:
src/dev/pciconfigall.cc:
src/dev/platform.cc:
src/dev/sparc/t1000.cc:
add dummy return where appropriate
src/dev/ide_atareg.h:
make define work for both gnuc and suncc
src/dev/io_device.hh:
add dummy returns where approirate
src/dev/pcidev.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.hh:
src/mem/dram.cc:
src/mem/packet.cc:
src/mem/port.cc:
include cstring for string ops
src/dev/sparc/mm_disk.cc:
add dummy return where appropriate
include cstring for string ops
src/mem/cache/miss/blocking_buffer.hh:
src/mem/port.hh:
Add dummy return where appropriate
src/mem/cache/tags/iic.cc:
cast hastSets to double for log() call
src/mem/physical.cc:
cast pmemAddr to char* for munmap
src/sim/byteswap.hh:
make define work for suncc and gnuc
3898:42a529d97cf2 Tue Jan 09 22:16:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> add memory mapped disk device

configs/common/FSConfig.py:
src/python/m5/objects/T1000.py:
add configuration for memory mapped disk
src/dev/sparc/SConscript:
add memory mapped disk to sconscript
/gem5/src/cpu/
H A Dexetrace.cc5034:6186ef720dd4 Thu Aug 30 15:16:00 EDT 2007 Miles Kaufmann <milesck@eecs.umich.edu> params: Deprecate old-style constructors; update most SimObject constructors.

SimObjects not yet updated:
- Process and subclasses
- BaseCPU and subclasses

The SimObject(const std::string &name) constructor was removed. Subclasses
that still rely on that behavior must call the parent initializer as
: SimObject(makeParams(name))
4776:8c8407243a2c Sat Jul 28 23:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Turn the instruction tracing code into pluggable sim objects.
These need to be refined a little still and given parameters.
4762:c94e103c83ad Tue Jul 24 00:51:00 EDT 2007 Nathan Binkert <nate@binkert.org> Major changes to how SimObjects are created and initialized. Almost all
creation and initialization now happens in python. Parameter objects
are generated and initialized by python. The .ini file is now solely for
debugging purposes and is not used in construction of the objects in any
way.
4594:25b6ff860bed Tue Jun 19 15:01:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Missed an "offset" to get rid of.
4572:5499df089a6c Thu Jun 14 16:52:00 EDT 2007 Vincentius Robby <acolyte@umich.edu> Modified instruction decode method.
Make code compatible with new decode method.

src/arch/alpha/remote_gdb.cc:
src/cpu/base_dyn_inst_impl.hh:
src/cpu/exetrace.cc:
src/cpu/simple/base.cc:
Make code compatible with new decode method.
src/cpu/static_inst.cc:
src/cpu/static_inst.hh:
Modified instruction decode method.
4565:94f0760f1b44 Thu Jun 14 09:27:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> A fix for SPARC_FS compilation.
4539:6eeeea62b7c4 Tue Jun 12 12:21:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Make microOp vs microop and macroOp vs macroop capitilization consistent.

src/arch/x86/isa/macroop.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also fill out the emulation environment handling a little more, and use an object to pass around output code.
src/arch/x86/isa/microops/base.isa:
Make microOp vs microop and macroOp vs macroop capitilization consistent. Also adjust python to C++ bool translation.
4359:6b6cb2927594 Mon Apr 09 21:52:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Fixed a compile error.
4268:12a0b7558078 Wed Mar 21 01:18:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer.eecs.umich.edu:/bk/newmem
into zower.eecs.umich.edu:/home/gblack/m5/newmem-statetrace
4266:0952dbfed63f Sun Mar 18 23:09:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Compile fixes for SPARC_FS.

src/arch/alpha/predecoder.hh:
src/arch/sparc/predecoder.hh:
Put in a missing include
src/cpu/exetrace.cc:
Convert the legion lockstep stuff from makeExtMI to the predecoder object.
/gem5/src/arch/mips/
H A Dtlb.cc5268:5bfc53fe60e7 Fri Nov 16 21:32:00 EST 2007 Korey Sewell <ksewell@umich.edu> go back and fix up MIPS copyright headers
5254:c555f8b07345 Thu Nov 15 14:21:00 EST 2007 Korey Sewell <ksewell@umich.edu> fix MIPS headers
5224:0e354459fb8a Wed Nov 14 06:24:00 EST 2007 Korey Sewell <ksewell@umich.edu> Get MIPS_SE actually working again by actually by fixing TLB stuff and running hello world
5222:bb733a878f85 Tue Nov 13 16:58:00 EST 2007 Korey Sewell <ksewell@umich.edu> Add in files from merge-bare-iron, get them compiling in FS and SE mode
5184:8782de2949e5 Thu Oct 25 22:04:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> TLB: Fix serialization issues with the tlb entries and make the page table store the process, not the system.
5034:6186ef720dd4 Thu Aug 30 15:16:00 EDT 2007 Miles Kaufmann <milesck@eecs.umich.edu> params: Deprecate old-style constructors; update most SimObject constructors.

SimObjects not yet updated:
- Process and subclasses
- BaseCPU and subclasses

The SimObject(const std::string &name) constructor was removed. Subclasses
that still rely on that behavior must call the parent initializer as
: SimObject(makeParams(name))
5019:2762e580f5db Tue Aug 28 17:30:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address translation: De-templatize the GenericTLB class.
5014:f9667cf03d3f Mon Aug 27 21:29:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> MIPS: Fixes to get mips to compile.
4997:e7380529bd2d Sun Aug 26 23:24:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
/gem5/src/arch/sparc/isa/formats/
H A Dbasic.isa5091:662c1d7b4795 Tue Sep 25 23:05:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> SPARC: Clean up the branch instructions a bit.
4394:dbaff14bb974 Sat Apr 21 17:50:00 EDT 2007 Ali Saidi <saidi@eecs.umich.edu> create base/fenv.c to standerdize fenv across platforms. It's a c file and not a cpp file because c99
(which defines fenv) doesn't necessarily extend to c++ and it is a problem with solaris. If really
desired this could wrap the ieeefp interface found in bsd* as well, but I see no need at the moment.

src/arch/alpha/isa/fp.isa:
src/arch/sparc/isa/formats/basic.isa:
use m5_fesetround()/m5_fegetround() istead of fenv interface directly
src/arch/sparc/isa/includes.isa:
use base/fenv instead of fenv directly
src/base/SConscript:
add fenv to sconscript
src/base/fenv.hh:
src/base/random.cc:
m5 implementation to standerdize fenv across platforms.
4362:95e5f28ce484 Tue Apr 10 20:25:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Create a filter and a union to translate the SPARC instruction implementations from using doubles to using concatenated singles.
4011:e6899d7ca5b1 Tue Feb 06 15:52:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> more fp fixes
fix unaligned accesses in mmaped disk device

src/arch/sparc/isa/decoder.isa:
get (ld|st)fsr ops working right. In reality the fp enable check needs to go higher up in the emitted code
src/arch/sparc/isa/formats/basic.isa:
move the cexec into the aexec field
src/cpu/exetrace.cc:
copy the exception state from legion when we get it wrong. We aren't going to get it right without an fp emulation layer
src/dev/sparc/mm_disk.cc:
src/dev/sparc/mm_disk.hh:
fix unaligned accesses in the memory mapped disk device
4008:ccad3906006a Fri Feb 02 18:04:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> fix mostly floating point related

src/arch/sparc/floatregfile.cc:
fix fp read/writing to registers... looking for suggestions on cleaner ways if anyone has them
src/arch/sparc/isa/decoder.isa:
fix some fp implementations
src/arch/sparc/isa/formats/basic.isa:
add new fp op class that 0 cexec in fsr and sets rounding mode for the up comming op
src/arch/sparc/isa/includes.isa:
include the appropriate header files for the rounding code
src/arch/sparc/miscregfile.cc:
print fsr out when it's read/written and the Sparc traceflgas in on
src/cpu/exetrace.cc:
fix printing of float registers
3980:9bcb2a2e9bb8 Sat Jan 27 01:59:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Merge zizzer:/bk/newmem
into zower.eecs.umich.edu:/eecshome/m5/newmem

src/arch/sparc/isa/formats/mem/util.isa:
src/arch/sparc/isa_traits.hh:
src/arch/sparc/system.cc:
Hand Merge
3937:a210ce8d4546 Fri Jan 26 18:57:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem
3931:de791fa53d04 Fri Jan 26 18:57:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> Make Sparc traceflag even more chatty
some fixes to fp instructions to use the single precision registers
if this is an fp op emit fp check code
add fpregs to m5legion struct

src/arch/sparc/floatregfile.cc:
Make Sparc traceflag even more chatty
src/arch/sparc/isa/base.isa:
add code to check if the fpu is enabled
src/arch/sparc/isa/decoder.isa:
some fixes to fp instructions to use the single precision registers
fix smul again
fix subc/subcc/subccc condition code setting
src/arch/sparc/isa/formats/basic.isa:
src/arch/sparc/isa/formats/mem/util.isa:
if this is an fp op emit fp check code
src/cpu/exetrace.cc:
check fp regs as well as int regs
src/cpu/m5legion_interface.h:
add fpregs to m5legion struct
3918:1f9a98d198e8 Fri Jan 26 18:48:00 EST 2007 Ali Saidi <saidi@eecs.umich.edu> make our code a little more standards compliant
pretty close to compiling w/ suns compiler

briefly:
add dummy return after panic()/fatal()
split out flags by compiler vendor
include cstring and cmath where appropriate
use std namespace for string ops

SConstruct:
Add code to detect compiler and choose cflags based on detected compiler
Fix zlib check to work with suncc
src/SConscript:
split out flags by compiler vendor
src/arch/sparc/isa/decoder.isa:
use correct namespace for sqrt
src/arch/sparc/isa/formats/basic.isa:
add dummy return around panic
src/arch/sparc/isa/formats/integerop.isa:
use correct namespace for stringops
src/arch/sparc/isa/includes.isa:
include cstring and cmath where appropriate
src/arch/sparc/isa_traits.hh:
remove dangling comma
src/arch/sparc/system.cc:
dummy return to make sun cc front end happy
src/arch/sparc/tlb.cc:
src/base/compression/lzss_compression.cc:
use std namespace for string ops
src/arch/sparc/utility.hh:
no reason to say something is unsigned unsigned int
src/base/compression/null_compression.hh:
dummy returns to for suncc front end
src/base/cprintf.hh:
use standard variadic argument syntax instead of gnuc specefic renaming
src/base/hashmap.hh:
don't need to define hash for suncc
src/base/hostinfo.cc:
need stdio.h for sprintf
src/base/loader/object_file.cc:
munmap is in std namespace not null
src/base/misc.hh:
use M5 generic noreturn macros
use standard variadic macro __VA_ARGS__
src/base/pollevent.cc:
we need file.h for file flags
src/base/random.cc:
mess with include files to make suncc happy
src/base/remote_gdb.cc:
malloc memory for function instead of having a non-constant in an array size
src/base/statistics.hh:
use std namespace for floor
src/base/stats/text.cc:
include math.h for rint (cmath won't work)
src/base/time.cc:
use suncc version of ctime_r
src/base/time.hh:
change macro to work with both gcc and suncc
src/base/timebuf.hh:
include cstring from memset and use std::
src/base/trace.hh:
change variadic macros to be normal format
src/cpu/SConscript:
add dummy returns where appropriate
src/cpu/activity.cc:
include cstring for memset
src/cpu/exetrace.hh:
include cstring fro memcpy
src/cpu/simple/base.hh:
add dummy return for panic
src/dev/baddev.cc:
src/dev/pciconfigall.cc:
src/dev/platform.cc:
src/dev/sparc/t1000.cc:
add dummy return where appropriate
src/dev/ide_atareg.h:
make define work for both gnuc and suncc
src/dev/io_device.hh:
add dummy returns where approirate
src/dev/pcidev.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/miss/blocking_buffer.cc:
src/mem/cache/tags/lru.hh:
src/mem/cache/tags/split.hh:
src/mem/cache/tags/split_lifo.hh:
src/mem/cache/tags/split_lru.hh:
src/mem/dram.cc:
src/mem/packet.cc:
src/mem/port.cc:
include cstring for string ops
src/dev/sparc/mm_disk.cc:
add dummy return where appropriate
include cstring for string ops
src/mem/cache/miss/blocking_buffer.hh:
src/mem/port.hh:
Add dummy return where appropriate
src/mem/cache/tags/iic.cc:
cast hastSets to double for log() call
src/mem/physical.cc:
cast pmemAddr to char* for munmap
src/sim/byteswap.hh:
make define work for suncc and gnuc

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