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11159:9459593cb649 |
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06-Oct-2015 |
Steve Reinhardt <steve.reinhardt@amd.com> |
x86: implement fild, fucomi, and fucomip x87 insts
fild loads an integer value into the x87 top of stack register. fucomi/fucomip compare two x87 register values (the latter also doing a stack pop). These instructions are used by some versions of GNU libstdc++.
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10784:2f1a0f6d5d77 |
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13-Apr-2015 |
Nilay Vaish <nilay@cs.wisc.edu> |
x86: implements x87 mult/div instructions
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10044:42e058cae3d0 |
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27-Jan-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
x86: implements x87 add/sub instructions
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10043:301f2c0b3423 |
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27-Jan-2014 |
Nilay Vaish <nilay@cs.wisc.edu> |
x86: implements fxch instruction.
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9895:a1f661af9dc9 |
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29-Sep-2013 |
Andreas Sandberg <andreas@sandberg.pp.se> |
x86: Add support for FLDENV & FNSTENV
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9894:c0a3920859bd |
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29-Sep-2013 |
Andreas Sandberg <andreas@sandberg.pp.se> |
x86: Add support for loading 32-bit and 80-bit floats in the x87
The x87 FPU supports three floating point formats: 32-bit, 64-bit, and 80-bit floats. The current gem5 implementation supports 32-bit and 64-bit floats, but only works correctly for 64-bit floats. This changeset fixes the 32-bit float handling by correctly loading and rounding (using truncation) 32-bit floats instead of simply truncating the bit pattern.
80-bit floats are loaded by first loading the 80-bits of the float to two temporary integer registers. A micro-op (cvtint_fp80) then converts the contents of the two integer registers to the internal FP representation (double). Similarly, when storing an 80-bit float, there are two conversion routines (ctvfp80h_int and cvtfp80l_int) that convert an internal FP register to 80-bit and stores the upper 64-bits or lower 32-bits to an integer register, which is the written to memory using normal integer stores.
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9582:0632d2d1575c |
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11-Mar-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
x86: implement some of the x87 instructions This patch implements ftan, fprem, fyl2x, fld* floating-point instructions.
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9472:8a2175fa7fa0 |
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15-Jan-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
x86: implements fsin, fcos instructions
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9470:68f7e0bcf4aa |
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15-Jan-2013 |
Nilay Vaish <nilay@cs.wisc.edu> |
x86: implement fabs, fchs instructions
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9372:7ba317c33683 |
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30-Dec-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
x86: implement x87 fp instruction fnstsw This patch implements the fnstsw instruction. The code was originally written by Vince Weaver. Gabe had made some comments about the code, but those were never addressed. This patch addresses those comments.
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9371:7c1484cc9b10 |
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30-Dec-2012 |
Nilay Vaish <nilay@cs.wisc.edu> |
x86: implement x87 fp instruction fsincos This patch implements the fsincos instruction. The code was originally written by Vince Weaver. Gabe had made some comments about the code, but those were never addressed. This patch addresses those comments.
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8106:4a194d4f6fb0 |
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02-Mar-2011 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Decode the mysterious and elusive ffreep x87 instruction.
The internet says this instruction was created by accident when an Intel CPU failed to decode x87 instructions properly. It's been documented on a few rare occasions and has generally worked to ensure backwards compatability. One source claims that the gcc toolchain is basically the only thing that emits it, and that emulators/binary translators like qemu and bochs implement it.
We won't actually implement it here since we're hardly implementing any other x87 instructions either. If we were to implement it, it would behave the same as ffree but then also pop the register stack.
http://www.pagetable.com/?p=16
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7087:fb8d5786ff30 |
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24-May-2010 |
Nathan Binkert <nate@binkert.org> |
copyright: Change HP copyright on x86 code to be more friendly
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6619:de112a8ac3d8 |
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20-Aug-2009 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Fix the decoding for and fill out FST and FSTP.
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5162:5af26efb306e |
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19-Oct-2007 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Make "Inst" the default format instead of WarnUnimpl for one byte opcodes.
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5084:675cb680830f |
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19-Sep-2007 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Implement the fld, fst, and fstp instructions.
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4827:d4ea1bbfdbc3 |
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31-Jul-2007 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Add operand type information to the fnstcw and fldw instruction placeholders. These are the only floating point instructions that get used in my simple hello world test. These instructions are for setting up the floating point control register. Their not being implemented doesn't affect anything because floating point isn't used.
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4825:93a992aa87f6 |
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30-Jul-2007 |
Gabe Black <gblack@eecs.umich.edu> |
X86: Add decoding for x87 floating point.
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