History log of /gem5/src/arch/x86/isa/insts/x87/control/save_and_restore_x87_environment.py
Revision Date Author Comments
# 12368:511bd7aa22d1 05-Dec-2017 Gabe Black <gabeblack@google.com>

x86: Split apart x87's FSW and TOP, and add a missing break.

The FSW and TOP values are technically part of the same register, but
they have very different behaviors. One of them can be renamed and
float along without affecting global state, while the other requires
serialization. They just need to *look* like the same register when
read by the user.

Also, there was a missing break in setMiscRegNoEffect.

Change-Id: If58de0f566f65068208240f4001209fb9e1826d6
Reviewed-on: https://gem5-review.googlesource.com/6441
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>


# 10899:b8b8ad2c72dd 04-Jul-2015 Nikos Nikoleris <nikos.nikoleris@gmail.com>

x86: Adjust the size of the values written to the x87 misc registers
All x87 misc registers are implemented in an array of 64 bit values
but in real hardware the size of some of these registers is smaller.
Previsouly all 64 bits where incorrectly set and then later read. To
ensure correctness we mask the value in setMiscRegNoEffect to write
only the valid bits.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>


# 9895:a1f661af9dc9 29-Sep-2013 Andreas Sandberg <andreas@sandberg.pp.se>

x86: Add support for FLDENV & FNSTENV


# 7087:fb8d5786ff30 24-May-2010 Nathan Binkert <nate@binkert.org>

copyright: Change HP copyright on x86 code to be more friendly


# 5081:2ccce8600a9d 19-Sep-2007 Gabe Black <gblack@eecs.umich.edu>

X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.