History log of /gem5/src/arch/x86/isa/insts/general_purpose/cache_and_memory_management.py
Revision Date Author Comments
# 12463:84f365522633 15-Jan-2018 Swapnil Haria <swapnilster@gmail.com>

arch-x86: Adding clflush, clflushopt, clwb instructions

This patch adds support for cache flushing instructions in x86.
It piggybacks on support for similar instructions in arm ISA
added by Nikos Nikoleris. I have tested each instruction using
microbenchmarks.

Change-Id: I72b6b8dc30c236a21eff7958fa231f0663532d7d
Reviewed-on: https://gem5-review.googlesource.com/7401
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>


# 7087:fb8d5786ff30 24-May-2010 Nathan Binkert <nate@binkert.org>

copyright: Change HP copyright on x86 code to be more friendly


# 5920:5a9c976270d6 25-Feb-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Implement a basic prefetch instruction.


# 5543:3af77710f397 10-Sep-2008 Ali Saidi <saidi@eecs.umich.edu>

style: Remove non-leading tabs everywhere they shouldn't be. Developers should configure their editors to not insert tabs


# 5081:2ccce8600a9d 19-Sep-2007 Gabe Black <gblack@eecs.umich.edu>

X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.