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/gem5/src/arch/x86/
H A Disa_traits.hh10924:d02e9c239892 Fri Jul 17 12:31:00 EDT 2015 Nilay Vaish <nilay@cs.wisc.edu> x86: decode instructions with vex prefix

This patch updates the x86 decoder so that it can decode instructions with vex
prefix. It also updates the isa with opcodes from vex opcode maps 1, 2 and 3.
Note that none of the instructions have been implemented yet. The
implementations would be provided in due course of time.
9329:3fe8438cbcfc Fri Nov 02 12:32:00 EDT 2012 Dam Sunwoo <dam.sunwoo@arm.com> ISA: generic Linux thread info support

This patch takes the Linux thread info support scattered across
different ISA implementations (currently in ARM, ALPHA, and MIPS), and
unifies them into a single file.

Adds a few more helper functions to read out TGID, mm, etc.

ISA-specific information (e.g., ALPHA PCBB register) is now moved to
the corresponding isa_traits.hh files.
7623:072f8b921599 Mon Aug 23 12:44:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Define a noop ExtMachInst.
7580:6f77f379a594 Mon Aug 23 12:18:00 EDT 2010 Ali Saidi <Ali.Saidi@arm.com> Loader: Make the load address mask be a parameter of the system rather than a constant.

This allows one two different OS requirements for the same ISA to be handled.
Some OSes are compiled for a virtual address and need to be loaded into physical
memory that starts at address 0, while other bare metal tools generate
images that start at address 0.
6974:4d4903a3e7c5 Fri Feb 12 14:53:00 EST 2010 Timothy M. Jones <tjones1@inf.ed.ac.uk> O3PCU: Split loads and stores that cross cache line boundaries.

When each load or store is sent to the LSQ, we check whether it will cross a
cache line boundary and, if so, split it in two. This creates two TLB
translations and two memory requests. Care has to be taken if the first
packet of a split load is sent but the second blocks the cache. Similarly,
for a store, if the first packet cannot be sent, we must store the second
one somewhere to retry later.

This modifies the LSQSenderState class to record both packets in a split
load or store.

Finally, a new const variable, HasUnalignedMemAcc, is added to each ISA
to indicate whether unaligned memory accesses are allowed. This is used
throughout the changed code so that compiler can optimise away code dealing
with split requests for ISAs that don't need them.
5958:2d9737bf3c2f Fri Feb 27 12:22:00 EST 2009 Gabe Black <gblack@eecs.umich.edu> Processes: Make getting and setting system call arguments part of a process object.
5152:20fc3ce35147 Fri Oct 12 23:10:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Loader: Identify sections based on virtual addresses, and set the LoadAddrMask correctly for x86.
4121:0ec036be76a7 Sat Mar 03 12:18:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Filled in with basic x86 information. Some things are missing, wrong, or non-sensical in x86.
/gem5/src/arch/power/
H A Dremote_gdb.hh11274:d9a0136ab8cc Fri Dec 18 16:12:00 EST 2015 Boris Shingarov <shingarov@labware.com> arm: remote GDB: rationalize structure of register offsets

Currently, the wire format of register values in g- and G-packets is
modelled using a union of uint8/16/32/64 arrays. The offset positions
of each register are expressed as a "register count" scaled according
to the width of the register in question. This results in counter-
intuitive and error-prone "register count arithmetic", and some
formats would even be altogether unrepresentable in such model, e.g.
a 64-bit register following a 32-bit one would have a fractional index
in the regs64 array.
Another difficulty is that the array is allocated before the actual
architecture of the workload is known (and therefore before the correct
size for the array can be calculated).

With this patch I propose a simpler mechanism for expressing the
register set structure. In the new code, GdbRegCache is an abstract
class; its subclasses contain straightforward structs reflecting the
register representation. The determination whether to use e.g. the
AArch32 vs. AArch64 register set (or SPARCv8 vs SPARCv9, etc.) is made
by polymorphically dispatching getregs() to the concrete subclass.
The subclass is not instantiated until it is needed for actual
g-/G-packet processing, when the mode is already known.

This patch is not meant to be merged in on its own, because it changes
the contract between src/base/remote_gdb.* and src/arch/*/remote_gdb.*,
so as it stands right now, it would break the other architectures.
In this patch only the base and the ARM code are provided for review;
once we agree on the structure, I will provide src/arch/*/remote_gdb.*
for the other architectures; those patches could then be merged in
together.

Review Request: http://reviews.gem5.org/r/3207/
Pushed by Joel Hestness <jthestness@gmail.com>
6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
/gem5/src/sim/power/
H A DPowerModel.py12546:8182d78bebcb Wed Mar 01 12:05:00 EST 2017 Anouk Van Laer <anouk.vanlaer@arm.com> sim: Added model type to power model

Static, dynamic or all to differentiate between types of power models
so for example static models will not be asked for a dynamic power

Change-Id: I3a0385821f7c671aedddaebeb038c677367faa81
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8601
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
11527:9007a9729815 Mon Jun 06 12:16:00 EDT 2016 David Guillen Fandos <david.guillen@arm.com> sim: Adding support for power models

This patch adds some basic support for power models in gem5.

The power interface is defined so it can interact with thermal
models as well. It implements a simple power evaluator that
can be used for simple power models that express power in the
form of a math expression. These expressions can use stats
within the same SimObject (or down its hierarchy) and some
magic variables such as "temp" for temperature.
In future patches we will extend this functionality to allow
slightly more complex expressions.

The model allows it to be extended to use other kinds of models.

Change-Id: I76752f9638b6815e229fd74cdcb7721a305cbc4b
/gem5/src/systemc/core/
H A Dobject.hh13268:9802f3e0a6ae Fri Sep 28 20:12:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Centralize how object parents are chosen.

There's a lot of repeated code for this. Also, the sc_vector type
needs to be able to artificially inject a parent for the objects it
creates.

Change-Id: I76f9b551632cd2cd70e26741b215290b35c382e9
Reviewed-on: https://gem5-review.googlesource.com/c/13194
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
12984:02f20eeeb8ce Thu Jul 19 20:12:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Make orphans top level objects instead of panic-ing.

When a simulation ends, the sc_objects it contains are destroyed one
by one, not necessarily in hierarchy order. That means that a parent
object can legitimately be destroyed before its children. Instead of
panic-ing when that inevitably happens, this change makes gem5 turn
those children into top level objects.

Change-Id: Icad9c99310fbc3ddcadbbb4f8a990b4fbfe35bdf
Reviewed-on: https://gem5-review.googlesource.com/12035
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
/gem5/src/cpu/testers/traffic_gen/
H A Dbase_gen.cc12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files.

Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5722
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
12396:3d04ea44fafb Wed Jul 12 12:33:00 EDT 2017 Riken Gohil <Riken.Gohil@arm.com> cpu-tester: Refactoring traffic generators into separate files.

Change-Id: I2372a0a88e276dcb0c06c3d0a789e010cfba8013
Reviewed-by: Matteo Andreozzi <matteo.andreozzi@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/5722
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/dev/virtio/
H A Dpci.cc13342:1ddb43f47325 Fri Oct 12 08:06:00 EDT 2018 Gabe Black <gabeblack@google.com> dev: Explicitly specify the endianness for packet accessors.

Generally speaking, the endianness of the data devices provide or
accept is dependent on the device and not the ISA the system
executes. This change makes the devices in dev pick an endianness
rather than using the guest's.

For the ISA bus and the UART, accesses are byte sized and so endianness
doesn't matter. The ISA and PCI busses and the devices which use them
are defined to be little endian.

Change-Id: Ib0aa70f192e1d6f3b886d9f3ad41ae03bddb583f
Reviewed-on: https://gem5-review.googlesource.com/c/13462
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
11932:98961d1b51ca Fri Mar 24 12:02:00 EDT 2017 Sascha Bischoff <sascha.bischoff@arm.com> dev: Align BAR0 size to power of 2 for VirtIO devices

When setting the size of a PCI BAR, the kernel only supports powers of
two (as per the PCI spec). Previously, the size was incorrectly read
by the kernel, and the address ranges assigned to the PCI devices
could overlap, resulting in gem5 crashes. We now round up to the next
power of two.

Kudos to Sergei Trofimov who helped to debug this issue!

Change-Id: I54ca399b62ea07c09d4cd989b17dfa670e841bbe
Reviewed-by: Anouk Van Laer <anouk.vanlaer@arm.com>
Reviewed-by: Sergei Trofimov <sergei.trofimov@arm.com>
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2580
Reviewed-by: Paul Rosenfeld <prosenfeld@micron.com>
/gem5/configs/ruby/
H A DGPU_VIPER_Region.py12647:6d7e2f321496 Thu Apr 12 17:38:00 EDT 2018 Tony Gutierrez <anthony.gutierrez@amd.com> configs, mem-ruby: fix issues with style in AMD license

fixes line length and white space issues.

Change-Id: Ia04a91ec68cae2bcdabeb93bb1a0f74e8e5486c3
Reviewed-on: https://gem5-review.googlesource.com/9801
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
12598:b80b2d9a251b Mon Feb 12 10:53:00 EST 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> arch-arm, configs: Treat the bootloader rom as cacheable memory

Prior to this changeset the bootloader rom (instantiated as a
SimpleMemory) in ruby Arm systems was treated as an IO device and it
was fronted by a DMA controller. This changeset moves the bootloader
rom and adds it to the system as another memory with a dedicated
directory controller.

Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8741
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
H A DGPU_VIPER_Baseline.py12647:6d7e2f321496 Thu Apr 12 17:38:00 EDT 2018 Tony Gutierrez <anthony.gutierrez@amd.com> configs, mem-ruby: fix issues with style in AMD license

fixes line length and white space issues.

Change-Id: Ia04a91ec68cae2bcdabeb93bb1a0f74e8e5486c3
Reviewed-on: https://gem5-review.googlesource.com/9801
Reviewed-by: Bradford Beckmann <brad.beckmann@amd.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
12598:b80b2d9a251b Mon Feb 12 10:53:00 EST 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> arch-arm, configs: Treat the bootloader rom as cacheable memory

Prior to this changeset the bootloader rom (instantiated as a
SimpleMemory) in ruby Arm systems was treated as an IO device and it
was fronted by a DMA controller. This changeset moves the bootloader
rom and adds it to the system as another memory with a dedicated
directory controller.

Change-Id: I094fed031cdef7f77a939d94f948d967b349b7e0
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/8741
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
/gem5/src/arch/power/linux/
H A Dprocess.hh13617:34a793c681ce Mon Nov 19 22:12:00 EST 2018 Gabe Black <gabeblack@google.com> power: Get rid of some ISA specific register types.

Change-Id: If63acb10705a9f442255680917d16630748ca8e1
Reviewed-on: https://gem5-review.googlesource.com/c/14465
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
6691:cd68b6ecd68d Tue Oct 27 12:24:00 EDT 2009 Timothy M. Jones <tjones1@inf.ed.ac.uk> POWER: Add support for the Power ISA

This adds support for the 32-bit, big endian Power ISA. This supports both
integer and floating point instructions based on the Power ISA Book I v2.06.
/gem5/src/arch/sparc/
H A DSparcSystem.py9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
7580:6f77f379a594 Mon Aug 23 12:18:00 EDT 2010 Ali Saidi <Ali.Saidi@arm.com> Loader: Make the load address mask be a parameter of the system rather than a constant.

This allows one two different OS requirements for the same ISA to be handled.
Some OSes are compiled for a virtual address and need to be loaded into physical
memory that starts at address 0, while other bare metal tools generate
images that start at address 0.
/gem5/src/base/vnc/
H A DVnc.py9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
9330:4a3269a11230 Fri Nov 02 12:32:00 EDT 2012 Chander Sudanthi <chander.sudanthi@arm.com> base: split out the VncServer into a VncInput and Server classes

This patch adds a VncInput base class which VncServer inherits from.
Another class can implement the same interface and be used instead
of the VncServer, for example a class that replays Vnc traffic.
/gem5/src/dev/pci/
H A Dcopy_engine.cc13342:1ddb43f47325 Fri Oct 12 08:06:00 EDT 2018 Gabe Black <gabeblack@google.com> dev: Explicitly specify the endianness for packet accessors.

Generally speaking, the endianness of the data devices provide or
accept is dependent on the device and not the ISA the system
executes. This change makes the devices in dev pick an endianness
rather than using the guest's.

For the ISA bus and the UART, accesses are byte sized and so endianness
doesn't matter. The ISA and PCI busses and the devices which use them
are defined to be little endian.

Change-Id: Ib0aa70f192e1d6f3b886d9f3ad41ae03bddb583f
Reviewed-on: https://gem5-review.googlesource.com/c/13462
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
11522:348411ec525a Mon Jun 06 12:16:00 EDT 2016 Stephan Diestelhorst <stephan.diestelhorst@arm.com> sim: Call regStats of base-class as well

We want to extend the stats of objects hierarchically and thus it is necessary
to register the statistics of the base-class(es), as well. For now, these are
empty, but generic stats will be added there.

Patch originally provided by Akash Bagdia at ARM Ltd.
/gem5/src/mem/cache/prefetch/
H A Dtagged.hh11439:d0368996f1e0 Thu Apr 07 12:32:00 EDT 2016 Rekai Gonzalez Alberquilla <Rekai.GonzalezAlberquilla@arm.com> mem: Add priority to QueuedPrefetcher

Queued prefetcher entries now count with a priority field. The idea is to
add packets ordered by priority and then by age.

For the existing algorithms in which priority doesn't make sense, it is set
to 0 for all deferred packets in the queue.
8831:6c08a877af8f Sun Feb 12 17:07:00 EST 2012 Mrinmoy Ghosh <mrinmoy.ghosh@arm.com> prefetcher: Make prefetcher a sim object instead of it being a parameter on cache
/gem5/tests/testing/
H A Dresults.py13540:da30e62884ee Thu Jan 10 10:12:00 EST 2019 Andrea Mondelli <andrea.mondelli@ucf.edu> misc: updated shabang for python script

The default python on MacOS doesn’t have an alias to python2.
The official python version supported in gem5 is Python2.7.

This patch updates the shabang according to the version required in gem5.

Change-Id: I9533c0f7858b5b3cab0ef101be1ee5cd718105b0
Reviewed-on: https://gem5-review.googlesource.com/c/15375
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
12581:a8f1d31d3492 Tue Mar 13 12:13:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> tests: Add missing print replacements in tests subdir

Some python files were still using deprecated print statement.

Change-Id: I19b1fe9c28650707f01725d40c87ad0538f9c5e6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/9141
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/util/m5/
H A DMakefile.x8612886:cba9b724a357 Thu Aug 03 12:22:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> tests: Add test for the m5-exit instruction.

Change-Id: I92a589b267ce659b6fbcf710043436b84fcb1c63
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/4423
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
12464:a02f2484c710 Sat Dec 09 12:02:00 EST 2017 Hanhwi Jang <jang.hanhwi@gmail.com> util: Implement Lua module for m5ops.

This module allows m5ops to be executed in Lua programs.
To compile it (in util/m5):
The following command generates Lua moduel, gem5OpLua.so.

make -f Makefile.<arch> gem5OpLua.so

To use it:
First, put gem5OpLua.so in Lua library search path.
Then, import the module and execute the m5op function.

Example usage, creating a checkpoint.

m5 = require("gem5OpLua")
m5.do_checkpoint(0, 0)

Change-Id: Icc18a1fb6c050afeb1cf4558fbdc724fb26a90e2
Reviewed-on: https://gem5-review.googlesource.com/6541
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/util/pbs/
H A Djob.py13540:da30e62884ee Thu Jan 10 10:12:00 EST 2019 Andrea Mondelli <andrea.mondelli@ucf.edu> misc: updated shabang for python script

The default python on MacOS doesn’t have an alias to python2.
The official python version supported in gem5 is Python2.7.

This patch updates the shabang according to the version required in gem5.

Change-Id: I9533c0f7858b5b3cab0ef101be1ee5cd718105b0
Reviewed-on: https://gem5-review.googlesource.com/c/15375
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
1908:73342b7d6f83 Wed Oct 12 13:01:00 EDT 2005 Nathan Binkert <binkertn@umich.edu> don't write the pbs jobid here, do it in send.py so we know
what it is sooner
Don't handle sigstop since you're not allowed to.

util/pbs/send.py:
write the pbs jobid here in send.py so we know what it is sooner
/gem5/src/arch/arm/tracers/
H A Dtarmac_parser.cc13915:24ae4ea846c9 Mon Apr 29 20:12:00 EDT 2019 Gabe Black <gabeblack@google.com> arch: Stop using TheISA within the ISAs.

We know for sure what the ISA is, so there's no need for the
indirection.

Change-Id: I73ff04c50890d40a4c7f40caeee746b68b846cb3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18488
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
13116:d3c3e2533928 Tue Sep 25 12:37:00 EDT 2018 Giacomo Travaglini <giacomo.travaglini@arm.com> arch-arm: Implement AArch64 ID_AA64MMFR2_EL1 register

This patch implements AArch64 Memory Model Feature Register 2
(from ARMv8.2)

Change-Id: I16d9acaf620fac6d1206e208bd143daec1657daf
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/13066
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
/gem5/src/base/
H A Dcircular_queue.hh14036:64006596f613 Fri May 31 12:39:00 EDT 2019 Daniel R. Carvalho <odanrc@yahoo.com.br> base: Fix missing headers to CircularQueue

CircularQueue is currently throwing compilation errors when creating
a derived class.

assert() needs <cassert>
ptrdiff_t needs <cstddef>
(u)intX_t need <cstdint>
random_access_iterator_tag needs <iterator>
is_same, enable_if and others need <type_traits>

Change-Id: I77a78e7b13f7a8b8e7e8b2b872065d78d1ab815a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19089
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
13482:6af7a10675b4 Wed Apr 26 12:44:00 EDT 2017 Rekai Gonzalez-Alberquilla <rekai.gonzalezalberquilla@arm.com> base: Iterable CircularQueue implementation

The former implementation of CircleBuf is functional but a bit too
tailored to match a use-case. This patches introduces a new iterable
circular queue, which adds some more functionality so it can also be
used for the newer LSQ implementation, where iteration and iterators
are a very desirable feature.

Additional contributors: Gabor Dozsa.

Change-Id: I5cfb95c8abc1f5e566a114acdbf23fc52a38ce5e
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/13127
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
/gem5/src/cpu/testers/directedtest/
H A DRubyDirectedTester.py9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
/gem5/src/cpu/minor/
H A Dexecute.cc14105:969b4e972b07 Wed Feb 27 12:26:00 EST 2019 Gabor Dozsa <gabor.dozsa@arm.com> cpu: Add first-/non-faulting load support to Minor and O3

Some architectures allow masking faults of memory load instructions in
some specific circumstances (e.g. first-faulting and non-faulting
loads in Arm SVE). This patch adds support for such loads in the Minor
and O3 CPU models.

Change-Id: I264a81a078f049127779aa834e89f0e693ba0bea
Signed-off-by: Gabor Dozsa <gabor.dozsa@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19178
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
13818:f0126488ef9e Tue Mar 26 18:12:00 EDT 2019 Javier Bueno <javier.bueno@metempsy.com> cpu: Added a probe to notify the address of retired instructions

A probe is added to notify the address of each retired instruction.

Change-Id: Iefc1b09d74b3aa0aa5773b17ba637bf51f5a59c9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17632
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
13652:45d94ac03a27 Mon Jan 22 13:12:00 EST 2018 Tuan Ta <qtt2@cornell.edu> cpu: support atomic memory request type with AtomicOpFunctor

This patch enables all 4 CPU models (AtomicSimpleCPU, TimingSimpleCPU,
MinorCPU and DerivO3CPU) to issue atomic memory (AMO) requests to memory
system.

Atomic memory instruction is treated as a special store instruction in
all CPU models.

In simple CPUs, an AMO request with an associated AtomicOpFunctor is
simply sent to L1 dcache.

In MinorCPU, an AMO request bypasses store buffer and waits for any
conflicting store request(s) currently in the store buffer to retire
before the AMO request is sent to the cache. AMO requests are not buffered
in the store buffer, so their effects appear immediately in the cache.

In DerivO3CPU, an AMO request is inserted in the store buffer so that it
is delivered to the cache only after all previous stores are issued to
the cache. Data forwarding between between an outstanding AMO in the
store buffer and a subsequent load is not allowed since the AMO request
does not hold valid data until it's executed in the cache.

This implementation assumes that a target ISA implementation must insert
enough memory fences as micro-ops around an atomic instruction to
enforce a correct order of memory instructions with respect to its
memory consistency model. Without extra memory fences, this implementation
can allow AMOs and other memory instructions that do not conflict
(i.e., not target the same address) to reorder.

This implementation also assumes that atomic instructions execute within
a cache line boundary since the cache for now is not able to execute an
operation on two different cache lines in one single step. Therefore,
ISAs like x86 that require multi-cache-line atomic instructions need to
either use a pair of locking load and unlocking store or change the
cache implementation to guarantee the atomicity of an atomic
instruction.

Change-Id: Ib8a7c81868ac05b98d73afc7d16eb88486f8cf9a
Reviewed-on: https://gem5-review.googlesource.com/c/8188
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
11568:91e95eb78191 Thu Jul 21 12:19:00 EDT 2016 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Fix Minor SMT WFI/drain interaction issues

The behavior of WFI is to cause minor to cease evaluating
pipeline logic until an interrupt is observed, however
a user may wish to drain the system while a core is sleeping
due to a WFI. This patch makes WFI drain. If an actual
drain occurs during a WFI, the CPU is already drained and will
immediately be ready for swapping, checkpointing, etc. This
should not negatively impact performance as WFI instructions
are 'stream-changing' (treated like unpredicted branches), so
all remaining instructions are wrong-path and will be squashed
rapidly.

Change-Id: I63833d5acb53d8dde78f9f0c9611de0ece385e45
11567:560d7fbbddd1 Thu Jul 21 12:19:00 EDT 2016 Mitch Hayenga <mitch.hayenga@arm.com> cpu: Add SMT support to MinorCPU

This patch adds SMT support to the MinorCPU. Currently
RoundRobin or Random thread scheduling are supported.

Change-Id: I91faf39ff881af5918cca05051829fc6261f20e3
11150:a8a64cca231b Wed Sep 30 12:14:00 EDT 2015 Mitch Hayenga <mitch.hayenga@arm.com> isa,cpu: Add support for FS SMT Interrupts

Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
10774:68d688cbe26c Fri Apr 03 12:42:00 EDT 2015 Nikos Nikoleris <nikos.nikoleris@gmail.com> cpu: fix system total instructions accounting

The totalInstructions counter is only incremented when the whole instruction is
commited and not on every microop. It was incorrectly reset in atomic and
timing cpus.

Committed by: Nilay Vaish <nilay@cs.wisc.edu>"
10366:128c1ed03f4e Fri Sep 12 10:22:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> minor: Fix typo in DPRINTF for Minor branch prediction
/gem5/src/mem/slicc/symbols/
H A DSymbolTable.py9219:258753d3bc47 Wed Sep 12 15:52:00 EDT 2012 Jason Power <power.jg@gmail.com> Ruby: Modify Scons so that we can put .sm files in extras
Also allows for header files which are required in slicc generated
code to be in a directory other than src/mem/ruby/slicc_interface.
6657:ef5fae93a3b2 Tue Sep 22 21:12:00 EDT 2009 Nathan Binkert <nate@binkert.org> slicc: Pure python implementation of slicc.
This is simply a translation of the C++ slicc into python with very minimal
reorganization of the code. The output can be verified as nearly identical
by doing a "diff -wBur".

Slicc can easily be run manually by using util/slicc
/gem5/src/dev/arm/
H A Dgic_v3.hh13878:40a2ec55ad89 Fri Apr 05 08:12:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Add GICv4 extension switch in GICv3

This is currently used only for determining which is the correct
size of redistributors in memory (256KB in GICv4 and 128KB in GICv3)

Change-Id: I2c07005e97167fde03548313c9927176788f31dd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18391
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
13756:12aa26df8c2f Thu Feb 07 17:25:00 EST 2019 Jairo Balart <jairo.balart@metempsy.com> dev-arm: cleanup of gicv3 code

Change-Id: I9aba90022f6408838c4ab87c6b90bba438752e53
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16222
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
/gem5/src/base/stats/
H A Dinfo.hh11565:9b9116df5e88 Thu Jul 21 12:19:00 EDT 2016 David Guillen Fandos <david.guillen@arm.com> base: Add total() to Vector2D stat

This patch adds a total() function to the Vector2D
stat type. Similar to other stats such as Scalar or
Vector it is useful to be able to read the total for
a given stat.
8296:be7f03723412 Thu May 12 14:19:00 EDT 2011 Nathan Binkert <nate@binkert.org> stats: move code that loops over all stats into python
/gem5/src/dev/x86/
H A DI82094AA.py9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
5651:7f0c8006c3d7 Sun Oct 12 16:28:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make APICs communicate through the memory system.
/gem5/src/cpu/o3/
H A Dchecker.cc11150:a8a64cca231b Wed Sep 30 12:14:00 EDT 2015 Mitch Hayenga <mitch.hayenga@arm.com> isa,cpu: Add support for FS SMT Interrupts

Adds per-thread interrupt controllers and thread/context logic
so that interrupts properly get routed in SMT systems.
9340:40f8c6a8f38d Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> cpu: Add header files for checker CPUs

In order to create reliable SWIG wrappers, we need to include the
declaration of the wrapped class in the SWIG file. Previously, we
didn't expose the declaration of checker CPUs. This patch adds header
files for such CPUs and include them in the SWIG wrapper.

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