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/gem5/src/cpu/pred/
H A Dtage_sc_l_64KB.hh14081:f99ed78e5263 Wed Jun 12 09:42:00 EDT 2019 Javier Bueno Hedo <javier.bueno@metempsy.com> cpu: Added the Multiperspective Perceptron Predictor with TAGE (8KB and 64KB)

Described by the following article:
Jiménez, D. "Multiperspective perceptron predictor with TAGE."
Championship Branch Prediction (CBP-5) (2016).

Change-Id: Ica3c121a4c94657d9015573085040e8a1984b069
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19188
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
H A Dtage_sc_l_8KB.cc14081:f99ed78e5263 Wed Jun 12 09:42:00 EDT 2019 Javier Bueno Hedo <javier.bueno@metempsy.com> cpu: Added the Multiperspective Perceptron Predictor with TAGE (8KB and 64KB)

Described by the following article:
Jiménez, D. "Multiperspective perceptron predictor with TAGE."
Championship Branch Prediction (CBP-5) (2016).

Change-Id: Ica3c121a4c94657d9015573085040e8a1984b069
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19188
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
H A Dtage_sc_l_8KB.hh14081:f99ed78e5263 Wed Jun 12 09:42:00 EDT 2019 Javier Bueno Hedo <javier.bueno@metempsy.com> cpu: Added the Multiperspective Perceptron Predictor with TAGE (8KB and 64KB)

Described by the following article:
Jiménez, D. "Multiperspective perceptron predictor with TAGE."
Championship Branch Prediction (CBP-5) (2016).

Change-Id: Ica3c121a4c94657d9015573085040e8a1984b069
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19188
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Ilias Vougioukas <ilias.vougioukas@arm.com>
/gem5/src/dev/arm/
H A Dgic_v3_distributor.hh14168:2a96e30b9400 Wed Aug 14 12:50:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Add GITS_PIDR2 register to the ITS memory map

The GITS Peripheral Identification Register #2 bits assignments are the
same as those for GICD_PIDR2.

Change-Id: I235008a383e08dd557d899cb3aa18202ef943f8b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20254
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
14167:65305e44b642 Wed Aug 14 12:38:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Add Gicv3Distributor members for GICv3 GICD_PIDRx

There is no need of calculating the value every time the registers
are read.

Change-Id: I58b87abb585fb9928959992927f00d9c000a4c35
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20253
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
13927:aafb89c4227b Tue Apr 30 12:16:00 EDT 2019 Giacomo Travaglini <giacomo.travaglini@arm.com> dev-arm: Add named variable for GICD_TYPER.IDBits

This could be used by other GICv3 components to query the maximum
number of implemented interrupt identifiers

Change-Id: I132e50de331aea22523260bcefba7e961b53eccd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18599
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
13756:12aa26df8c2f Thu Feb 07 17:25:00 EST 2019 Jairo Balart <jairo.balart@metempsy.com> dev-arm: cleanup of gicv3 code

Change-Id: I9aba90022f6408838c4ab87c6b90bba438752e53
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/16222
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
/gem5/src/base/filters/
H A Dbulk_bloom_filter.cc14263:4a6d5c4a0813 Sun May 12 08:34:00 EDT 2019 Daniel R. Carvalho <odanrc@yahoo.com.br> base: Make Bulk inherit from MultiBitSel Bloom Filter

Cleanup bulk's code and make it inherit from MultiBitSel.

Change-Id: I83154feb30bb3dac3d02743bcafbdcb57489c2fd
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18876
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
H A Dbulk_bloom_filter.hh14263:4a6d5c4a0813 Sun May 12 08:34:00 EDT 2019 Daniel R. Carvalho <odanrc@yahoo.com.br> base: Make Bulk inherit from MultiBitSel Bloom Filter

Cleanup bulk's code and make it inherit from MultiBitSel.

Change-Id: I83154feb30bb3dac3d02743bcafbdcb57489c2fd
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18876
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
/gem5/src/arch/x86/
H A DX86LocalApic.py9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
5651:7f0c8006c3d7 Sun Oct 12 16:28:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make APICs communicate through the memory system.
5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
H A DSConscript7624:3f32191bcf66 Mon Aug 23 12:44:00 EDT 2010 Gabe Black <gblack@eecs.umich.edu> X86: Make the x86 ExtMachInst serializable with (UN)SERIALIZE_SCALAR.
5800:19c06c037040 Mon Jan 19 12:59:00 EST 2009 Nathan Binkert <nate@binkert.org> tracing: Add help strings for some of the trace flags
5659:f4b9c344d1ca Sun Oct 12 18:31:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement CPUID with a magical function instead of microcode.
5649:0e9c904551c1 Sun Oct 12 03:07:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Add a LocalApic trace flag.
5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
5647:b06b49498c79 Sun Oct 12 12:09:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.
5450:25e395a87745 Thu Jun 12 00:58:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make the e820 table manually or automatically configurable from python.
5245:d94bb8af9f76 Mon Nov 12 21:06:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Separate out the page table walker into it's own cc and hh.
5149:356e00996637 Fri Oct 12 19:37:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions.
There are no priviledge checks, so these instructions will all work in all
modes.
4159:a3cc632b33d8 Mon Mar 05 12:56:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> Add some new source files.
H A Dpagetable_walker.hh14096:bde52fccbf0f Fri Jul 12 13:29:00 EDT 2019 Matthew Poremba <matthew.poremba@amd.com> arch-x86: Don't free PTW state with inflight requests

If a page table walk is squashed, the walker state is being deleted
in the squash code. If there are in flight requests, the deleted
walker state values may be clobbered, leading to undefined behavior.
This adds a squashed boolean to the walker state which is set if a
walk is squashed while requests are still in flight. When packets
for the in flight request return, we check if the walk was squashed
and return that the walk is complete once the number of in flight
requests reaches zero. The walker state is then freed by the PTW.

Change-Id: I57a64b1548b83a8a9e8441fc9d6f33e9842df2b3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19568
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Tested-by: kokoro <noreply+kokoro@google.com>
12088:ffd7952e9929 Thu Jun 08 12:35:00 EDT 2017 Sean Wilson <spwilson2@wisc.edu> sim, x86: Replace EventWrapper use with EventFunctionWrapper

Change-Id: Ie1df07b70776208fc3631a73d403024636fc05a9
Signed-off-by: Sean Wilson <spwilson2@wisc.edu>
Reviewed-on: https://gem5-review.googlesource.com/3749
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
9701:f02f3b6562d5 Tue May 21 12:40:00 EDT 2013 Gedare Bloom <gedare@rtems.org> x86: Squash outstanding walks when instructions are squashed.
This is the x86 version of the ARM changeset baa17ba80e06. In case an
instruction has been squashed by the o3 cpu, this patch allows page
table walker to avoid carrying out a pending translation that the
instruction requested for.
9294:8fb03b13de02 Mon Oct 15 08:12:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Port: Add protocol-agnostic ports in the port hierarchy

This patch adds an additional level of ports in the inheritance
hierarchy, separating out the protocol-specific and protocl-agnostic
parts. All the functionality related to the binding of ports is now
confined to use BaseMaster/BaseSlavePorts, and all the
protocol-specific parts stay in the Master/SlavePort. In the future it
will be possible to add other protocol-specific implementations.

The functions used in the binding of ports, i.e. getMaster/SlavePort
now use the base classes, and the index parameter is updated to use
the PortID typedef with the symbolic InvalidPortID as the default.
9044:904ddeecc653 Tue Jun 05 01:23:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> sim: Remove FastAlloc

While FastAlloc provides a small performance increase (~1.5%) over regular malloc it isn't thread safe.
After removing FastAlloc and using tcmalloc I've seen a performance increase of 12% over libc malloc
when running twolf for ARM.
8953:488d45aeb672 Sun Apr 15 02:24:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> X86: Use the AddrTrie class to implement the TLB.

This change also adjusts the TlbEntry class so that it stores the number of
address bits wide a page is rather than its size in bytes. In other words,
instead of storing 4K for a 4K page, it stores 12. 12 is easy to turn into 4K,
but it's a little harder going the other way.
8953:488d45aeb672 Sun Apr 15 02:24:00 EDT 2012 Gabe Black <gblack@eecs.umich.edu> X86: Use the AddrTrie class to implement the TLB.

This change also adjusts the TlbEntry class so that it stores the number of
address bits wide a page is rather than its size in bytes. In other words,
instead of storing 4K for a 4K page, it stores 12. 12 is easy to turn into 4K,
but it's a little harder going the other way.
8864:fe907afe14a3 Thu Mar 01 12:37:00 EST 2012 Nilay Vaish <nilay@cs.wisc.edu> x86: Fix x86 TLB and Walker
This patch adds a function to X86 tlb that returns the
walker port. This port is required for correctly connecting
the walker ports for the cpu just switched in
8832:247fee427324 Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: Add a master ID to each request object.

This change adds a master id to each request object which can be
used identify every device in the system that is capable of issuing a request.
This is part of the way to removing the numCpus+1 stats in the cache and
replacing them with the master ids. This is one of a series of changes
that make way for the stats output to be changed to python.
5245:d94bb8af9f76 Mon Nov 12 21:06:00 EST 2007 Gabe Black <gblack@eecs.umich.edu> X86: Separate out the page table walker into it's own cc and hh.
/gem5/tests/long/se/20.parser/ref/arm/linux/simple-timing/
H A Dstats.txt11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee
10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming
9265:8fe936e937bd Tue Sep 25 12:49:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ARM: update stats for bp and squash fixes.
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/tests/long/se/30.eon/ref/arm/linux/simple-timing/
H A Dstats.txt11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee
10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming
9265:8fe936e937bd Tue Sep 25 12:49:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ARM: update stats for bp and squash fixes.
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/tests/long/se/40.perlbmk/ref/arm/linux/simple-timing/
H A Dstats.txt11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee
10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming
9265:8fe936e937bd Tue Sep 25 12:49:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ARM: update stats for bp and squash fixes.
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/tests/long/se/60.bzip2/ref/arm/linux/simple-timing/
H A Dstats.txt11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee
10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming
9265:8fe936e937bd Tue Sep 25 12:49:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ARM: update stats for bp and squash fixes.
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/tests/quick/se/00.hello/ref/x86/linux/simple-timing-ruby/
H A Dstats.txt11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee
11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming
9702:094d0280e481 Tue May 21 12:41:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> x86, regressions: updates stats
This is due to op class, function call, walker patches.
9698:db85c5348a96 Tue May 21 12:32:00 EDT 2013 Nilay Vaish <nilay@cs.wisc.edu> stats: updates statistics for ruby regressions
9013:afa278317136 Tue May 22 12:38:00 EDT 2012 Nilay Vaish <nilay@cs.wisc.edu> X86 Regression: update stats due to cc register split
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/src/arch/x86/isa/
H A Dincludes.isa6345:f9ae7c3a036c Thu Jul 16 12:29:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Take limitted advantage of the compilers type checking for microop operands.
5666:e7925fa8f0d6 Sun Oct 12 20:48:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Make X86's microcode ROM actually do something.
5659:f4b9c344d1ca Sun Oct 12 18:31:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Implement CPUID with a magical function instead of microcode.
5425:4226f6c2d03c Thu Jun 12 00:49:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> X86: Add microops which panic, fatal, warn, and warn_once.
4543:4cbcab038791 Tue Jun 12 12:29:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Get rid of unnecessary namespace prototype.
4543:4cbcab038791 Tue Jun 12 12:29:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Get rid of unnecessary namespace prototype.
4528:f0b19ee67a7b Fri Jun 08 12:09:00 EDT 2007 Gabe Black <gblack@eecs.umich.edu> Big changes to use the new microcode assembler.
/gem5/util/
H A Dregress13540:da30e62884ee Thu Jan 10 10:12:00 EST 2019 Andrea Mondelli <andrea.mondelli@ucf.edu> misc: updated shabang for python script

The default python on MacOS doesn’t have an alias to python2.
The official python version supported in gem5 is Python2.7.

This patch updates the shabang according to the version required in gem5.

Change-Id: I9533c0f7858b5b3cab0ef101be1ee5cd718105b0
Reviewed-on: https://gem5-review.googlesource.com/c/15375
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
11730:08ab68477ea0 Wed Nov 30 17:12:00 EST 2016 Alec Roelke <ar4jc@virginia.edu> riscv: [Patch 8/5] Added some regression tests to RISC-V

This patch is the eighth patch in a series adding RISC-V to gem5, and
third of the bonus patches to the original series of five. It adds some
regression tests to RISC-V.

Regression tests included:
- se/00.hello
- se/02.insttest (split into several binaries which are not included due
to large size)

The tests added to 00.insttest will need to be build manually; to
facilitate this, a Makefile is included. The required toolchain and
compiler (riscv64-unknown-elf-gcc) can be built from the riscv-tools
GitHub repository at https://github.com/riscv/riscv-tools.

Note that because EBREAK only makes sense when gdb is running or while in
FS mode, it is not included in the linux-rv64i insttest. ERET is not
included because it does not make sense in SE mode and, in fact, causes
a panic by design.

Note also that not every system call is tested in linux-rv64i; of the ones
defined in linux/process.hh, some have been given numbers but not
definitions for the toolchain, or are merely stubs that always return 0. Of
the ones that do work properly, only a subset are tested due to similar
functionality.

Signed-off by: Alec Roelke

Signed-off by: Jason Lowe-Power <jason@lowepower.com>
8127:e64347d17555 Sat Mar 12 17:38:00 EST 2011 Gabe Black <gblack@eecs.umich.edu> Regressions: Make X86_FS run automatically.
4949:302707329b7e Sun Aug 12 12:56:00 EDT 2007 Nathan Binkert <nate@binkert.org> style: If IGNORE_STYLE=True is set on the scons command line, ignore style.
Use this in the regress script to avoid issues with the checker.
4949:302707329b7e Sun Aug 12 12:56:00 EDT 2007 Nathan Binkert <nate@binkert.org> style: If IGNORE_STYLE=True is set on the scons command line, ignore style.
Use this in the regress script to avoid issues with the checker.
3734:5eb062f81950 Tue Dec 12 12:54:00 EST 2006 Steve Reinhardt <stever@eecs.umich.edu> If no tests are specified for regression, just build the binaries
(instead of complaining and exiting).
3734:5eb062f81950 Tue Dec 12 12:54:00 EST 2006 Steve Reinhardt <stever@eecs.umich.edu> If no tests are specified for regression, just build the binaries
(instead of complaining and exiting).
/gem5/src/mem/
H A Dsimple_mem.hh11169:44b5c183c3cd Mon Oct 12 04:08:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Add explicit overrides and fix other clang >= 3.5 issues

This patch adds explicit overrides as this is now required when using
"-Wall" with clang >= 3.5, the latter now part of the most recent
XCode. The patch consequently removes "virtual" for those methods
where "override" is added. The latter should be enough of an
indication.

As part of this patch, a few minor issues that clang >= 3.5 complains
about are also resolved (unused methods and variables).
11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
9349:844f9e724343 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> mem: fix use after free issue in memories until 4-phase work complete.
9342:6fec8f26e56d Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Move the draining interface into a separate base class

This patch moves the draining interface from SimObject to a separate
class that can be used by any object needing draining. However,
objects not visible to the Python code (i.e., objects not deriving
from SimObject) still depend on their parents informing them when to
drain. This patch also gets rid of the CountedDrainEvent (which isn't
really an event) and replaces it with a DrainManager.
9294:8fb03b13de02 Mon Oct 15 08:12:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Port: Add protocol-agnostic ports in the port hierarchy

This patch adds an additional level of ports in the inheritance
hierarchy, separating out the protocol-specific and protocl-agnostic
parts. All the functionality related to the binding of ports is now
confined to use BaseMaster/BaseSlavePorts, and all the
protocol-specific parts stay in the Master/SlavePort. In the future it
will be possible to add other protocol-specific implementations.

The functions used in the binding of ports, i.e. getMaster/SlavePort
now use the base classes, and the index parameter is updated to use
the PortID typedef with the symbolic InvalidPortID as the default.
9264:1607119c36bb Tue Sep 25 12:49:00 EDT 2012 Djordje Kovacevic <djordje.kovacevic@arm.com> MEM: Put memory system document into doxygen
9120:48eeef8a0997 Thu Jul 12 00:56:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Mem: Make SimpleMemory single ported

This patch changes the simple memory to have a single slave port
rather than a vector port. The simple memory makes no attempts at
modelling the contention between multiple ports, and any such
multiplexing and demultiplexing could be done in a bus (or crossbar)
outside the memory controller. This scenario also matches with the
ongoing work on a SimpleDRAM model, which will be a single-ported
single-channel controller that can be used in conjunction with a bus
(or crossbar) to create a multi-port multi-channel controller.

There are only very few regressions that make use of the vector port,
and these are all for functional accesses only. To facilitate these
cases, memtest and memtest-ruby have been updated to also have a
"functional" bus to perform the (de)multiplexing of the functional
memory accesses.
/gem5/tests/quick/se/00.hello/ref/alpha/linux/o3-timing/
H A Dstats.txt11731:c473ca7cc650 Wed Nov 30 17:12:00 EST 2016 Jason Lowe-Power <jason@lowepower.com> tests: Regression stats updated for recent patches
11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee
11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
10148:4574d5882066 Sun Mar 23 11:12:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for DRAM changes

This patch updates the stats to reflect the changes to the DRAM
controller.
9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/tests/quick/se/00.hello/ref/mips/linux/o3-timing/
H A Dstats.txt11731:c473ca7cc650 Wed Nov 30 17:12:00 EST 2016 Jason Lowe-Power <jason@lowepower.com> tests: Regression stats updated for recent patches
11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee
11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
10148:4574d5882066 Sun Mar 23 11:12:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for DRAM changes

This patch updates the stats to reflect the changes to the DRAM
controller.
9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/tests/quick/se/00.hello/ref/power/linux/o3-timing/
H A Dstats.txt11731:c473ca7cc650 Wed Nov 30 17:12:00 EST 2016 Jason Lowe-Power <jason@lowepower.com> tests: Regression stats updated for recent patches
11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee
11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
10148:4574d5882066 Sun Mar 23 11:12:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for DRAM changes

This patch updates the stats to reflect the changes to the DRAM
controller.
9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/tests/quick/se/02.insttest/ref/sparc/linux/o3-timing/
H A Dstats.txt11731:c473ca7cc650 Wed Nov 30 17:12:00 EST 2016 Jason Lowe-Power <jason@lowepower.com> tests: Regression stats updated for recent patches
11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee
11440:76b5639162af Fri Apr 08 12:01:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update stats for thermals, indirect BP
11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
10148:4574d5882066 Sun Mar 23 11:12:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for DRAM changes

This patch updates the stats to reflect the changes to the DRAM
controller.
9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/tests/quick/se/40.m5threads-test-atomic/ref/sparc/linux/o3-timing-mp/
H A Dstats.txt11731:c473ca7cc650 Wed Nov 30 17:12:00 EST 2016 Jason Lowe-Power <jason@lowepower.com> tests: Regression stats updated for recent patches
11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11606:6b749761c398 Fri Aug 12 09:12:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Update to match classic memory changes
11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
11530:6e143fd2cabf Mon Jun 06 12:16:00 EDT 2016 Andreas Sandberg <andreas.sandberg@arm.com> stats: Add power stats to test references

Change-Id: Ic827213134b199446822f128b81d4a480e777fee
11268:8b4b55d79ddd Sat Dec 12 17:27:00 EST 2015 Anthony Gutierrez <atgutier@umich.edu> stats: bump stats to reflect ruby tester changes
10148:4574d5882066 Sun Mar 23 11:12:00 EDT 2014 Andreas Hansson <andreas.hansson@arm.com> stats: Update stats for DRAM changes

This patch updates the stats to reflect the changes to the DRAM
controller.
9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
9289:a31a1243a3ed Mon Oct 15 08:12:00 EDT 2012 Andreas Hansson <andreas.hansson@arm.com> Stats: Update stats for cache timings in cycles

This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/src/dev/alpha/
H A Dtsunami_io.hh11169:44b5c183c3cd Mon Oct 12 04:08:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Add explicit overrides and fix other clang >= 3.5 issues

This patch adds explicit overrides as this is now required when using
"-Wall" with clang >= 3.5, the latter now part of the most recent
XCode. The patch consequently removes "virtual" for those methods
where "override" is added. The latter should be enough of an
indication.

As part of this patch, a few minor issues that clang >= 3.5 complains
about are also resolved (unused methods and variables).
11168:f98eb2da15a4 Mon Oct 12 04:07:00 EDT 2015 Andreas Hansson <andreas.hansson@arm.com> misc: Remove redundant compiler-specific defines

This patch moves away from using M5_ATTR_OVERRIDE and the m5::hashmap
(and similar) abstractions, as these are no longer needed with gcc 4.7
and clang 3.1 as minimum compiler versions.
9338:97b4a2be1e5b Fri Nov 02 12:32:00 EDT 2012 Andreas Sandberg <Andreas.Sandberg@arm.com> sim: Include object header files in SWIG interfaces

When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.

This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
5443:394d180e8c04 Thu Jun 12 00:54:00 EDT 2008 Gabe Black <gblack@eecs.umich.edu> Dev: Seperate the 8254 timer from tsunami and use it in that and the PC.
3885:fd4067a5b903 Wed Jan 03 13:12:00 EST 2007 Nathan Binkert <binkertn@umich.edu> Add 'Time' as a parameter type that can accept various
formats for time (strings, datetime objects, etc.)
Advance system time to 1/1/2009
Clean up time management code a little bit
/gem5/tests/long/se/20.parser/ref/arm/linux/o3-timing/
H A Dconfig.ini11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
9370:5172ffaf6e30 Wed Dec 12 10:51:00 EST 2012 Nilay Vaish <nilay@cs.wisc.edu> arm regressions: updates to config.ini, terminal files
9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
9265:8fe936e937bd Tue Sep 25 12:49:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> ARM: update stats for bp and squash fixes.
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes
/gem5/tests/long/se/20.parser/ref/x86/linux/o3-timing/
H A Dsimout11570:4aac82f10951 Thu Jul 21 12:19:00 EDT 2016 Curtis Dunham <Curtis.Dunham@arm.com> stats: update references
10063:9595c7a1d837 Sun Feb 16 12:40:00 EST 2014 Nilay Vaish <nilay@cs.wisc.edu> stats: updates due to branch predictor warming
9348:44d31345e360 Fri Nov 02 12:50:00 EDT 2012 Ali Saidi <Ali.Saidi@ARM.com> update stats for preceeding changes
9013:afa278317136 Tue May 22 12:38:00 EDT 2012 Nilay Vaish <nilay@cs.wisc.edu> X86 Regression: update stats due to cc register split
8835:7c68f84d7c4e Sun Feb 12 17:07:00 EST 2012 Ali Saidi <Ali.Saidi@ARM.com> stats: update stats for insts/ops and master id changes

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