arm,sparc,x86,base,cpu,sim: Replace the Twin(32|64)_t types with.

Replace them with std::array<>s.

Change-Id: I76624c87a1cd9b21c386a96147a18de92b8a8a34
Reviewed-on: https://gem5-review.googlesource.com/6602
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

misc: Rename misc.(hh|cc) to logging.(hh|cc)

These files aren't a collection of miscellaneous stuff, they're the
definition of the Logger interface, and a few utility macros for
calling into that interface (panic, warn, etc.).

Change-Id: I84267ac3f45896a83c0ef027f8f19c5e9a5667d1
Reviewed-on: https://gem5-review.googlesource.com/6226
Reviewed-by: Brandon Potter <Brandon.Potter@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch, x86: add support for arrays as memory operands

Although the cache models support wider accesses, the ISA descriptions
assume that (for the most part) memory operands are integer types,
which makes it difficult to define instructions that do memory accesses
larger than 64 bits.

This patch adds some generic support for memory operands that are arrays
of uint64_t, and specifically a 'u2qw' operand type for x86 that is an
array of 2 uint64_ts (128 bits). This support is unused at this point,
but will be needed shortly for cmpxchg16b. Ideally the 128-bit SSE
memory accesses will also be rewritten to use this support.

Support for 128-bit accesses could also have been added using the gcc
__int128_t extension, which would have been less disruptive. However,
although clang also supports __int128_t, it's still non-standard.
Also, more importantly, this approach creates a path to defining
256- and 512-byte operands as well, which will be useful for eventual
AVX support.

x86: Fix loading of floating point constants

This changeset actually fixes two issues:

* The lfpimm instruction didn't work correctly when applied to a
floating point constant (it did work for integers containing the
bit string representation of a constant) since it used
reinterpret_cast to convert a double to a uint64_t. This caused a
compilation error, at least, in gcc 4.6.3.

* The instructions loading floating point constants in the x87
processor didn't work correctly since they just stored a truncated
integer instead of a double in the floating point register. This
changeset fixes the old microcode by using lfpimm instruction
instead of the limm instructions.

ISA: Make the decode function part of the ISA's decoder.

X86: Use the M5PanicFault fault in execute methods instead of calling panic.

If an instruction is executed speculatively and hits a situation where it
wants to panic, it should return a fault instead. If the instruction was
misspeculated, the fault can be thrown away. If the instruction wasn't
misspeculated, the fault will be invoked and the panic will still happen.

SE/FS: Use the new FullSystem constant where possible.

PseudoInst: Remove the now unnecessary #if FULL_SYSTEMs around pseudoinsts.

ISA: Use readBytes/writeBytes for all instruction level memory operations.

trace: reimplement the DTRACE function so it doesn't use a vector
At the same time, rename the trace flags to debug flags since they
have broader usage than simply tracing. This means that
--trace-flags is now --debug-flags and --trace-help is now --debug-help

includes: sort all includes

X86: Put the result used for flags in an intermediate variable.

Using the destination register directly causes the ISA parser to treat it as a
source even if none of the original bits are used.

X86: Define fault objects to carry debug messages.

These faults can panic/warn/warn_once, etc., instead of instructions doing
that themselves directly. That way, instructions can be speculatively
executed, and only if they're actually going to commit will their fault be
invoked and the panic, etc., happen.

X86: Create a directory for files that define register indexes.

This is to help tidy up arch/x86. These files should not be used external to
the ISA.

copyright: Change HP copyright on x86 code to be more friendly

X86: Implement an integer media addition microop with optional saturation.

X86: Set up a media microop framework and create mov2int and mov2fp microops.

X86: Take limitted advantage of the compilers type checking for microop operands.

X86: Fold the MiscRegFile all the way into the ISA object.

Registers: Add a registers.hh file as an ISA switched header.
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.

X86: Implement a basic prefetch instruction.

X86: Add a flag to force memory accesses to happen at CPL 0.

X86: Hook in the M5 pseudo insts.

X86: Move the macroop class out of the isa description into C++.

X86: Make X86's microcode ROM actually do something.

X86: Implement CPUID with a magical function instead of microcode.

X86: Add microops which panic, fatal, warn, and warn_once.

X86: Implement the ldst microop and put it in existing microcode where appropriate.

X86: Move the fp microops to their own file with their own base classes in C++ and python.

X86: Add SSE comparison instructions and microops and move some FP microops to be with the other ones.

X86: Add operands to handle floating point registers.

Actually include miscregs.hh

Pull some hard coded base classes out of the isa description.

Get rid of an unnecessary include file.

Needed for last change set to work :P

Make memory instructions work better, add more macroop implementations, add an lea microop, move EmulEnv into it's own .cc and .hh.

Get rid of unnecessary namespace prototype.

Big changes to use the new microcode assembler.

A batch of changes and fixes. Macroops are now generated automatically, multiops do alot more of what they're supposed to (excluding memory operands), and microops are slightly more implemented.

Stub decoder. This is probably even farther from finished than it looks...