History log of /gem5/src/arch/x86/SConscript
Revision Date Author Comments
# 12222:6db0fc7407a5 15-Oct-2017 Gabe Black <gabeblack@google.com>

scons: Stop generating inc.d in the isa parser.

Generating dependency/build product information in the isa parser breaks scons
idea of how a build is supposed to work. Arm twisting it into working forced
a lot of false dependencies which slowed down the build.

Change-Id: Iadee8c930fd7c80136d200d69870df7672a6b3ca
Reviewed-on: https://gem5-review.googlesource.com/5081
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Gabe Black <gabeblack@google.com>


# 10553:c1ad57c53a36 23-Nov-2014 Alexandru Dutu <alexandru.dutu@amd.com>

kvm, x86: Adding support for SE mode execution
This patch adds methods in KvmCPU model to handle KVM exits caused by syscall
instructions and page faults. These types of exits will be encountered if
KvmCPU is run in SE mode.


# 10494:ffe6ab7141ab 20-Oct-2014 Andreas Hansson <andreas.hansson@arm.com>

x86: Fixes to avoid LTO warnings

This patch fixes a few minor issues that caused link-time warnings
when using LTO, mainly for x86. The most important change is how the
syscall array is created. Previously gcc and clang would complain that
the declaration and definition types did not match. The organisation
is now changed to match how it is done for ARM, moving the code that
was previously in syscalls.cc into process.cc, and having a class
variable pointing to the static array.

With these changes, there are no longer any warnings using gcc 4.6.3
with LTO.


# 10196:be0e1724eb39 09-May-2014 Curtis Dunham <Curtis.Dunham@arm.com>

arch: teach ISA parser how to split code across files

This patch encompasses several interrelated and interdependent changes
to the ISA generation step. The end goal is to reduce the size of the
generated compilation units for instruction execution and decoding so
that batch compilation can proceed with all CPUs active without
exhausting physical memory.

The ISA parser (src/arch/isa_parser.py) has been improved so that it can
accept 'split [output_type];' directives at the top level of the grammar
and 'split(output_type)' python calls within 'exec {{ ... }}' blocks.
This has the effect of "splitting" the files into smaller compilation
units. I use air-quotes around "splitting" because the files themselves
are not split, but preprocessing directives are inserted to have the same
effect.

Architecturally, the ISA parser has had some changes in how it works.
In general, it emits code sooner. It doesn't generate per-CPU files,
and instead defers to the C preprocessor to create the duplicate copies
for each CPU type. Likewise there are more files emitted and the C
preprocessor does more substitution that used to be done by the ISA parser.

Finally, the build system (SCons) needs to be able to cope with a
dynamic list of source files coming out of the ISA parser. The changes
to the SCons{cript,truct} files support this. In broad strokes, the
targets requested on the command line are hidden from SCons until all
the build dependencies are determined, otherwise it would try, realize
it can't reach the goal, and terminate in failure. Since build steps
(i.e. running the ISA parser) must be taken to determine the file list,
several new build stages have been inserted at the very start of the
build. First, the build dependencies from the ISA parser will be emitted
to arch/$ISA/generated/inc.d, which is then read by a new SCons builder
to finalize the dependencies. (Once inc.d exists, the ISA parser will not
need to be run to complete this step.) Once the dependencies are known,
the 'Environments' are made by the makeEnv() function. This function used
to be called before the build began but now happens during the build.
It is easy to see that this step is quite slow; this is a known issue
and it's important to realize that it was already slow, but there was
no obvious cause to attribute it to since nothing was displayed to the
terminal. Since new steps that used to be performed serially are now in a
potentially-parallel build phase, the pathname handling in the SCons scripts
has been tightened up to deal with chdir() race conditions. In general,
pathnames are computed earlier and more likely to be stored, passed around,
and processed as absolute paths rather than relative paths. In the end,
some of these issues had to be fixed by inserting serializing dependencies
in the build.

Minor note:
For the null ISA, we just provide a dummy inc.d so SCons is never
compelled to try to generate it. While it seems slightly wrong to have
anything in src/arch/*/generated (i.e. a non-generated 'generated' file),
it's by far the simplest solution.


# 9384:877293183bdf 07-Jan-2013 Andreas Sandberg <Andreas.Sandberg@arm.com>

arch: Make the ISA class inherit from SimObject

The ISA class on stores the contents of ID registers on many
architectures. In order to make reset values of such registers
configurable, we make the class inherit from SimObject, which allows
us to use the normal generated parameter headers.

This patch introduces a Python helper method, BaseCPU.createThreads(),
which creates a set of ISAs for each of the threads in an SMT
system. Although it is currently only needed when creating
multi-threaded CPUs, it should always be called before instantiating
the system as this is an obvious place to configure ID registers
identifying a thread/CPU.


# 9057:f5ee56466b91 05-Jun-2012 Ali Saidi <Ali.Saidi@ARM.com>

ISA: Back-out NoopMachInst as a StaticInstPtr change.


# 9040:cdfe09f9bdee 04-Jun-2012 Gabe Black <gblack@eecs.umich.edu>

ISA: Turn the ExtMachInst NoopMachinst into the StaticInstPtr NoopStaticInst.

This eliminates a use of the ExtMachInst type outside of the ISAs.


# 9023:e9201a7bce59 26-May-2012 Gabe Black <gblack@eecs.umich.edu>

CPU: Merge the predecoder and decoder.

These classes are always used together, and merging them will give the ISAs
more flexibility in how they cache things and manage the process.


# 9022:bb25e7646c41 25-May-2012 Gabe Black <gblack@eecs.umich.edu>

ISA: Make the decode function part of the ISA's decoder.


# 8771:a2a4416cadc8 30-Oct-2011 Gabe Black <gblack@eecs.umich.edu>

X86: Build the same files in SE and FS.


# 8753:8369dcf5b3a8 13-Oct-2011 Gabe Black <gblack@eecs.umich.edu>

X86: Build vtophys in SE mode.


# 8752:28e899b7dee3 13-Oct-2011 Gabe Black <gblack@eecs.umich.edu>

X86: Turn on the page table walker in SE mode.


# 8745:575cab0db076 09-Oct-2011 Gabe Black <gblack@eecs.umich.edu>

SE/FS: Build the Interrupt objects in SE mode.


# 8740:253aeee61e66 30-Sep-2011 Gabe Black <gblack@eecs.umich.edu>

X86: Remove FULL_SYSTEM from the x86 faults.


# 8335:9228e00459d4 02-Jun-2011 Nathan Binkert <nate@binkert.org>

scons: rename TraceFlags to DebugFlags


# 7966:0dff1ff293d0 13-Feb-2011 Gabe Black <gblack@eecs.umich.edu>

X86: On a bad microopc, return a microop that returns a fault that panics.

This way a bad micropc will have to get all the way to commit before killing
the simulation. This accounts for misspeculated branches.


# 7624:3f32191bcf66 23-Aug-2010 Gabe Black <gblack@eecs.umich.edu>

X86: Make the x86 ExtMachInst serializable with (UN)SERIALIZE_SCALAR.


# 7087:fb8d5786ff30 24-May-2010 Nathan Binkert <nate@binkert.org>

copyright: Change HP copyright on x86 code to be more friendly


# 6515:a785733109e7 17-Aug-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Create base classes for use with media/SIMD microops.


# 6365:a3037fa327a0 20-Jul-2009 Gabe Black <gblack@eecs.umich.edu>

CPU: Separate out native trace into ISA (in)dependent code and SimObjects.


# 6336:25635830e33c 09-Jul-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Fold the MiscRegFile all the way into the ISA object.


# 6329:5d8b91875859 09-Jul-2009 Gabe Black <gblack@eecs.umich.edu>

Registers: Add a registers.hh file as an ISA switched header.
This file is for register indices, Num* constants, and register types.
copyRegs and copyMiscRegs were moved to utility.hh and utility.cc.


# 6316:51f3026d4cbb 09-Jul-2009 Gabe Black <gblack@eecs.umich.edu>

Registers: Eliminate the ISA defined integer register file.


# 6315:c7295a4826d5 09-Jul-2009 Gabe Black <gblack@eecs.umich.edu>

Registers: Eliminate the ISA defined floating point register file.


# 6313:95f69a436c82 09-Jul-2009 Gabe Black <gblack@eecs.umich.edu>

Registers: Add an ISA object which replaces the MiscRegFile.
This object encapsulates (or will eventually) the identity and characteristics
of the ISA in the CPU.


# 5933:8b9bc09b149c 25-Feb-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Implement CLTS.


# 5909:ecbd27e5d1f8 25-Feb-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Add a trace flag for tracing faults.


# 5904:5c61233cbd53 25-Feb-2009 Gabe Black <gblack@eecs.umich.edu>

X86: Add a trace flag for the page table walker.


# 5800:19c06c037040 19-Jan-2009 Nathan Binkert <nate@binkert.org>

tracing: Add help strings for some of the trace flags


# 5793:321f79ddb500 13-Jan-2009 Nathan Binkert <nate@binkert.org>

SCons: centralize the Dir() workaround for newer versions of scons.
Scons bug id: 2006 M5 Bug id: 308


# 5680:39ae093fb4eb 13-Oct-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Implement entering an interrupt in microcode.


# 5659:f4b9c344d1ca 12-Oct-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Implement CPUID with a magical function instead of microcode.


# 5649:0e9c904551c1 12-Oct-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Add a LocalApic trace flag.


# 5647:b06b49498c79 12-Oct-2008 Gabe Black <gblack@eecs.umich.edu>

Turn Interrupts objects into SimObjects. Also, move local APIC state into x86's Interrupts object.


# 5612:1bd333953e49 10-Oct-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Move the smbios objects into a folder for BIOS objects.


# 5450:25e395a87745 12-Jun-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Make the e820 table manually or automatically configurable from python.


# 5406:fc680749b40e 11-Jun-2008 Ali Saidi <saidi@eecs.umich.edu>

SCons: Fix more SCons version issues


# 5359:8c6ff200e4c1 26-Feb-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Implement the INVLPG instruction and the TIA microop.


# 5334:5136aad50b97 23-Jan-2008 Gabe Black <gblack@eecs.umich.edu>

X86: Put an SMBios/DMI table in memory.
This is basically just the header right now, but there's an untested
mechanism in place to fill out the table and make sure everything is
updated correctly.


# 5299:e61b9f2a9732 02-Dec-2007 Gabe Black <gblack@eecs.umich.edu>

X86: Move startup code to the system object to initialize a Linux system.


# 5298:a836e89a8ee0 02-Dec-2007 Gabe Black <gblack@eecs.umich.edu>

X86: Add a missing microcode file to the sconscript.


# 5245:d94bb8af9f76 12-Nov-2007 Gabe Black <gblack@eecs.umich.edu>

X86: Separate out the page table walker into it's own cc and hh.


# 5192:582e583f8e7e 31-Oct-2007 Ali Saidi <saidi@eecs.umich.edu>

Traceflags: Add SCons function to created a traceflag instead of having one file with them all.


# 5173:07204d59a328 19-Oct-2007 Gabe Black <gblack@eecs.umich.edu>

X86: Impelement the HLT instruction and fix the "halt" microop.


# 5149:356e00996637 12-Oct-2007 Gabe Black <gblack@eecs.umich.edu>

X86: Implement MSR reads and writes and the wrsmr and rdmsr instructions.
There are no priviledge checks, so these instructions will all work in all
modes.


# 5135:6ae576eada5c 07-Oct-2007 Gabe Black <gblack@eecs.umich.edu>

X86: Make initCPU and startupCPU do something basic.


# 5132:ad5e94876bfc 07-Oct-2007 Gabe Black <gblack@eecs.umich.edu>

X86: Make an x86 system object.


# 5124:3d8c50376609 03-Oct-2007 Gabe Black <gblack@eecs.umich.edu>

X86: Start implementing the x86 tlb which will handle segmentation permission and limit checks and paging.


# 5086:e7913ffb379d 24-Sep-2007 Gabe Black <gblack@eecs.umich.edu>

X86: Get X86_FS to compile.


# 5083:49559a8060e8 19-Sep-2007 Gabe Black <gblack@eecs.umich.edu>

X86: Move the fp microops to their own file with their own base classes in C++ and python.


# 5081:2ccce8600a9d 19-Sep-2007 Gabe Black <gblack@eecs.umich.edu>

X86: Put in stubs for x87, 64 bit and 128 bit SIMD instruction microcode.


# 5069:9cc257fa60cd 10-Sep-2007 Gabe Black <gblack@eecs.umich.edu>

X86: Make the isa parser run if any of the microcode files change.


# 4997:e7380529bd2d 26-Aug-2007 Gabe Black <gblack@eecs.umich.edu>

Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.


# 4679:0b39fa8f5eb8 14-Jul-2007 Gabe Black <gblack@eecs.umich.edu>

Pull some hard coded base classes out of the isa description.


# 4601:38c989d15fef 20-Jun-2007 Gabe Black <gblack@eecs.umich.edu>

Make memory instructions work better, add more macroop implementations, add an lea microop, move EmulEnv into it's own .cc and .hh.


# 4249:3a3be2b708b0 15-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Split the x86 "process" predecoder method into it's own file.


# 4240:cde9d7751cce 14-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Merge zizzer.eecs.umich.edu:/bk/newmem
into ahchoo.blinky.homelinux.org:/home/gblack/m5/newmem-x86

src/arch/mips/utility.hh:
src/arch/x86/SConscript:
Hand merge


# 4202:f7a05daec670 11-Mar-2007 Nathan Binkert <binkertn@umich.edu>

Rework the way SCons recurses into subdirectories, making it
automatic. The point is that now a subdirectory can be added
to the build process just by creating a SConscript file in it.
The process has two passes. On the first pass, all subdirs
of the root of the tree are searched for SConsopts files.
These files contain any command line options that ought to be
added for a particular subdirectory. On the second pass,
all subdirs of the src directory are searched for SConscript
files. These files describe how to build any given subdirectory.
I have added a Source() function. Any file (relative to the
directory in which the SConscript resides) passed to that
function is added to the build. Clean up everything to take
advantage of Source().
function is added to the list of files to be built.


# 4182:5b2c0d266107 14-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Make the predecoder an object with it's own switched header file. Start adding predecoding functionality to x86.

src/arch/SConscript:
src/arch/alpha/utility.hh:
src/arch/mips/utility.hh:
src/arch/sparc/utility.hh:
src/cpu/base.hh:
src/cpu/o3/fetch.hh:
src/cpu/o3/fetch_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/base.cc:
src/cpu/simple/base.hh:
src/cpu/static_inst.hh:
src/arch/alpha/predecoder.hh:
src/arch/mips/predecoder.hh:
src/arch/sparc/predecoder.hh:
Make the predecoder an object with it's own switched header file.


# 4166:ecebe3ac19b4 06-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Get X86 to load an elf and start a process for it.

src/arch/x86/SConscript:
Add in process source files.
src/arch/x86/isa_traits.hh:
Replace magic constant numbers with the x86 register names.
src/arch/x86/miscregfile.cc:
Make clear the miscreg file succeed. There aren't any misc regs, so clearing them is very easy.
src/arch/x86/process.hh:
An X86 process class.
src/base/loader/elf_object.cc:
Add in code to recognize x86 as an architecture.
src/base/traceflags.py:
Add an x86 traceflag
src/sim/process.cc:
Add in code to create an x86 process.
src/arch/x86/intregs.hh:
A file which declares names for the integer register indices.
src/arch/x86/linux/linux.cc:
src/arch/x86/linux/linux.hh:
A very simple translation of SPARC's linux.cc and linux.hh. It's probably not correct for x86, but it might not be correct for SPARC either.
src/arch/x86/linux/process.cc:
src/arch/x86/linux/process.hh:
An x86 linux process. The syscall table is split out into it's own file.
src/arch/x86/linux/syscalls.cc:
The x86 Linux syscall table and the uname function.
src/arch/x86/process.cc:
The x86 process base class.
tests/test-progs/hello/bin/x86/linux/hello:
An x86 hello world test binary.


# 4159:a3cc632b33d8 05-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Add some new source files.


# 4120:3e09b5d32c45 03-Mar-2007 Gabe Black <gblack@eecs.umich.edu>

Add build hooks for x86.