13096SN/A 23096SN/A---------- Begin Simulation Statistics ---------- 311680SCurtis.Dunham@arm.comsim_seconds 0.000024 # Number of seconds simulated 411680SCurtis.Dunham@arm.comsim_ticks 23776000 # Number of ticks simulated 511680SCurtis.Dunham@arm.comfinal_tick 23776000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 68428SN/Asim_freq 1000000000000 # Frequency of simulated ticks 711860Sandreas.hansson@arm.comhost_inst_rate 135386 # Simulator instruction rate (inst/s) 811860Sandreas.hansson@arm.comhost_op_rate 135348 # Simulator op (including micro ops) rate (op/s) 911860Sandreas.hansson@arm.comhost_tick_rate 503875461 # Simulator tick rate (ticks/s) 1011860Sandreas.hansson@arm.comhost_mem_usage 253920 # Number of bytes of host memory used 1111860Sandreas.hansson@arm.comhost_seconds 0.05 # Real time elapsed on the host 1211390Ssteve.reinhardt@amd.comsim_insts 6385 # Number of instructions simulated 1311390Ssteve.reinhardt@amd.comsim_ops 6385 # Number of ops (including micro ops) simulated 1410036SAli.Saidi@ARM.comsystem.voltage_domain.voltage 1 # Voltage in Volts 1510036SAli.Saidi@ARM.comsystem.clk_domain.clock 1000 # Clock period in ticks 1611680SCurtis.Dunham@arm.comsystem.physmem.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 1711860Sandreas.hansson@arm.comsystem.physmem.bytes_read::cpu.inst 19904 # Number of bytes read from this memory 1811390Ssteve.reinhardt@amd.comsystem.physmem.bytes_read::cpu.data 11072 # Number of bytes read from this memory 1911860Sandreas.hansson@arm.comsystem.physmem.bytes_read::total 30976 # Number of bytes read from this memory 2011860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::cpu.inst 19904 # Number of instructions bytes read from this memory 2111860Sandreas.hansson@arm.comsystem.physmem.bytes_inst_read::total 19904 # Number of instructions bytes read from this memory 2211860Sandreas.hansson@arm.comsystem.physmem.num_reads::cpu.inst 311 # Number of read requests responded to by this memory 2311390Ssteve.reinhardt@amd.comsystem.physmem.num_reads::cpu.data 173 # Number of read requests responded to by this memory 2411860Sandreas.hansson@arm.comsystem.physmem.num_reads::total 484 # Number of read requests responded to by this memory 2511860Sandreas.hansson@arm.comsystem.physmem.bw_read::cpu.inst 837146703 # Total read bandwidth from this memory (bytes/s) 2611680SCurtis.Dunham@arm.comsystem.physmem.bw_read::cpu.data 465679677 # Total read bandwidth from this memory (bytes/s) 2711860Sandreas.hansson@arm.comsystem.physmem.bw_read::total 1302826380 # Total read bandwidth from this memory (bytes/s) 2811860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::cpu.inst 837146703 # Instruction read bandwidth from this memory (bytes/s) 2911860Sandreas.hansson@arm.comsystem.physmem.bw_inst_read::total 837146703 # Instruction read bandwidth from this memory (bytes/s) 3011860Sandreas.hansson@arm.comsystem.physmem.bw_total::cpu.inst 837146703 # Total bandwidth to/from this memory (bytes/s) 3111680SCurtis.Dunham@arm.comsystem.physmem.bw_total::cpu.data 465679677 # Total bandwidth to/from this memory (bytes/s) 3211860Sandreas.hansson@arm.comsystem.physmem.bw_total::total 1302826380 # Total bandwidth to/from this memory (bytes/s) 3311860Sandreas.hansson@arm.comsystem.physmem.readReqs 484 # Number of read requests accepted 349978Sandreas.hansson@arm.comsystem.physmem.writeReqs 0 # Number of write requests accepted 3511860Sandreas.hansson@arm.comsystem.physmem.readBursts 484 # Number of DRAM read bursts, including those serviced by the write queue 369978Sandreas.hansson@arm.comsystem.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 3711860Sandreas.hansson@arm.comsystem.physmem.bytesReadDRAM 30976 # Total number of bytes read from DRAM 389978Sandreas.hansson@arm.comsystem.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 399978Sandreas.hansson@arm.comsystem.physmem.bytesWritten 0 # Total number of bytes written to DRAM 4011860Sandreas.hansson@arm.comsystem.physmem.bytesReadSys 30976 # Total read bytes from the system interface side 419978Sandreas.hansson@arm.comsystem.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 429978Sandreas.hansson@arm.comsystem.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 439978Sandreas.hansson@arm.comsystem.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 449978Sandreas.hansson@arm.comsystem.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 4511440SCurtis.Dunham@arm.comsystem.physmem.perBankRdBursts::0 69 # Per bank write bursts 4611103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::1 32 # Per bank write bursts 4711860Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::2 32 # Per bank write bursts 489978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::3 47 # Per bank write bursts 4911390Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::4 42 # Per bank write bursts 5010352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::5 20 # Per bank write bursts 519978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::6 1 # Per bank write bursts 529978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::7 3 # Per bank write bursts 539978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::8 0 # Per bank write bursts 549978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::9 1 # Per bank write bursts 5510726Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::10 22 # Per bank write bursts 5610352Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::11 25 # Per bank write bursts 579978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::12 14 # Per bank write bursts 5811103Snilay@cs.wisc.edusystem.physmem.perBankRdBursts::13 118 # Per bank write bursts 599978Sandreas.hansson@arm.comsystem.physmem.perBankRdBursts::14 45 # Per bank write bursts 6011390Ssteve.reinhardt@amd.comsystem.physmem.perBankRdBursts::15 13 # Per bank write bursts 619978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::0 0 # Per bank write bursts 629978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::1 0 # Per bank write bursts 639978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::2 0 # Per bank write bursts 649978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::3 0 # Per bank write bursts 659978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::4 0 # Per bank write bursts 669978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::5 0 # Per bank write bursts 679978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::6 0 # Per bank write bursts 689978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::7 0 # Per bank write bursts 699978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::8 0 # Per bank write bursts 709978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::9 0 # Per bank write bursts 719978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::10 0 # Per bank write bursts 729978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::11 0 # Per bank write bursts 739978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::12 0 # Per bank write bursts 749978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::13 0 # Per bank write bursts 759978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::14 0 # Per bank write bursts 769978Sandreas.hansson@arm.comsystem.physmem.perBankWrBursts::15 0 # Per bank write bursts 779978Sandreas.hansson@arm.comsystem.physmem.numRdRetry 0 # Number of times read queue was full causing retry 789978Sandreas.hansson@arm.comsystem.physmem.numWrRetry 0 # Number of times write queue was full causing retry 7911680SCurtis.Dunham@arm.comsystem.physmem.totGap 23381000 # Total gap between requests 809978Sandreas.hansson@arm.comsystem.physmem.readPktSize::0 0 # Read request sizes (log2) 819978Sandreas.hansson@arm.comsystem.physmem.readPktSize::1 0 # Read request sizes (log2) 829978Sandreas.hansson@arm.comsystem.physmem.readPktSize::2 0 # Read request sizes (log2) 839978Sandreas.hansson@arm.comsystem.physmem.readPktSize::3 0 # Read request sizes (log2) 849978Sandreas.hansson@arm.comsystem.physmem.readPktSize::4 0 # Read request sizes (log2) 859978Sandreas.hansson@arm.comsystem.physmem.readPktSize::5 0 # Read request sizes (log2) 8611860Sandreas.hansson@arm.comsystem.physmem.readPktSize::6 484 # Read request sizes (log2) 879978Sandreas.hansson@arm.comsystem.physmem.writePktSize::0 0 # Write request sizes (log2) 889978Sandreas.hansson@arm.comsystem.physmem.writePktSize::1 0 # Write request sizes (log2) 899978Sandreas.hansson@arm.comsystem.physmem.writePktSize::2 0 # Write request sizes (log2) 909978Sandreas.hansson@arm.comsystem.physmem.writePktSize::3 0 # Write request sizes (log2) 919978Sandreas.hansson@arm.comsystem.physmem.writePktSize::4 0 # Write request sizes (log2) 929978Sandreas.hansson@arm.comsystem.physmem.writePktSize::5 0 # Write request sizes (log2) 939978Sandreas.hansson@arm.comsystem.physmem.writePktSize::6 0 # Write request sizes (log2) 9411680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::0 260 # What read queue length does an incoming req see 9511860Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::1 140 # What read queue length does an incoming req see 9611680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::2 52 # What read queue length does an incoming req see 9711680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see 9811680SCurtis.Dunham@arm.comsystem.physmem.rdQLenPdf::4 11 # What read queue length does an incoming req see 999322Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 1009312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 1019312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 1029312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 1039312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 1049312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 1059312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 1069312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 1079312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 1089312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 1099312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 1109312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 1119312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 1129312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 1139312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 1149312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 1159312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 1169312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 1179312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 1189312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 1199312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 1209312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 1219312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 1229312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 1239312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 1249312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 1259312Sandreas.hansson@arm.comsystem.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 1269312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 1279312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 1289312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 1299312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 1309312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 1319312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 1329312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 1339312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 1349312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 1359312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 1369312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 1379312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 1389312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 1399312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 1409312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 1419312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 1429312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 1439312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 1449312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 1459312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 1469312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 1479312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 1489312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 1499312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 1509312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 1519312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 1529312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 1539312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 1549312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 1559312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 1569312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 1579312Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 15810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 15910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 16010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 16110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 16210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 16310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 16410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 16510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 16610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 16710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 16810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 16910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 17010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 17110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 17210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 17310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 17410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 17510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 17610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 17710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 17810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 17910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 18010148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 18110148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 18210148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 18310148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 18410148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 18510148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 18610148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 18710148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 18810148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 18910148Sandreas.hansson@arm.comsystem.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 19011680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::samples 89 # Bytes accessed per row activation 19111860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::mean 347.325843 # Bytes accessed per row activation 19211860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::gmean 230.027877 # Bytes accessed per row activation 19311860Sandreas.hansson@arm.comsystem.physmem.bytesPerActivate::stdev 312.328054 # Bytes accessed per row activation 19411680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::0-127 21 23.60% 23.60% # Bytes accessed per row activation 19511680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::128-255 22 24.72% 48.31% # Bytes accessed per row activation 19611680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::256-383 15 16.85% 65.17% # Bytes accessed per row activation 19711680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::384-511 9 10.11% 75.28% # Bytes accessed per row activation 19811680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::512-639 6 6.74% 82.02% # Bytes accessed per row activation 19911680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::640-767 3 3.37% 85.39% # Bytes accessed per row activation 20011680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::768-895 2 2.25% 87.64% # Bytes accessed per row activation 20111680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::896-1023 1 1.12% 88.76% # Bytes accessed per row activation 20211680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::1024-1151 10 11.24% 100.00% # Bytes accessed per row activation 20311680SCurtis.Dunham@arm.comsystem.physmem.bytesPerActivate::total 89 # Bytes accessed per row activation 20411860Sandreas.hansson@arm.comsystem.physmem.totQLat 8020750 # Total ticks spent queuing 20511860Sandreas.hansson@arm.comsystem.physmem.totMemAccLat 17095750 # Total ticks spent from burst creation until serviced by the DRAM 20611860Sandreas.hansson@arm.comsystem.physmem.totBusLat 2420000 # Total ticks spent in databus transfers 20711860Sandreas.hansson@arm.comsystem.physmem.avgQLat 16571.80 # Average queueing delay per DRAM burst 2089978Sandreas.hansson@arm.comsystem.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst 20911860Sandreas.hansson@arm.comsystem.physmem.avgMemAccLat 35321.80 # Average memory access latency per DRAM burst 21011860Sandreas.hansson@arm.comsystem.physmem.avgRdBW 1302.83 # Average DRAM read bandwidth in MiByte/s 2119978Sandreas.hansson@arm.comsystem.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 21211860Sandreas.hansson@arm.comsystem.physmem.avgRdBWSys 1302.83 # Average system read bandwidth in MiByte/s 2139978Sandreas.hansson@arm.comsystem.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 2149978Sandreas.hansson@arm.comsystem.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 21511860Sandreas.hansson@arm.comsystem.physmem.busUtil 10.18 # Data bus utilization in percentage 21611860Sandreas.hansson@arm.comsystem.physmem.busUtilRead 10.18 # Data bus utilization in percentage for reads 2179978Sandreas.hansson@arm.comsystem.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 21811680SCurtis.Dunham@arm.comsystem.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing 2199978Sandreas.hansson@arm.comsystem.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 22011860Sandreas.hansson@arm.comsystem.physmem.readRowHits 394 # Number of row buffer hits during reads 2219312Sandreas.hansson@arm.comsystem.physmem.writeRowHits 0 # Number of row buffer hits during writes 22211860Sandreas.hansson@arm.comsystem.physmem.readRowHitRate 81.40 # Row buffer hit rate for reads 2239312Sandreas.hansson@arm.comsystem.physmem.writeRowHitRate nan # Row buffer hit rate for writes 22411860Sandreas.hansson@arm.comsystem.physmem.avgGap 48307.85 # Average gap between requests 22511860Sandreas.hansson@arm.comsystem.physmem.pageHitRate 81.40 # Row buffer hit rate, read and write combined 22611680SCurtis.Dunham@arm.comsystem.physmem_0.actEnergy 242760 # Energy for activate commands per rank (pJ) 22711680SCurtis.Dunham@arm.comsystem.physmem_0.preEnergy 125235 # Energy for precharge commands per rank (pJ) 22811860Sandreas.hansson@arm.comsystem.physmem_0.readEnergy 1756440 # Energy for read commands per rank (pJ) 22910628Sandreas.hansson@arm.comsystem.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 23011680SCurtis.Dunham@arm.comsystem.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) 23111860Sandreas.hansson@arm.comsystem.physmem_0.actBackEnergy 3000480 # Energy for active background per rank (pJ) 23211860Sandreas.hansson@arm.comsystem.physmem_0.preBackEnergy 47040 # Energy for precharge background per rank (pJ) 23311860Sandreas.hansson@arm.comsystem.physmem_0.actPowerDownEnergy 7630020 # Energy for active power-down per rank (pJ) 23411860Sandreas.hansson@arm.comsystem.physmem_0.prePowerDownEnergy 131040 # Energy for precharge power-down per rank (pJ) 23511680SCurtis.Dunham@arm.comsystem.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 23611860Sandreas.hansson@arm.comsystem.physmem_0.totalEnergy 14776935 # Total energy per rank (pJ) 23711860Sandreas.hansson@arm.comsystem.physmem_0.averagePower 621.499816 # Core power per rank (mW) 23811860Sandreas.hansson@arm.comsystem.physmem_0.totalIdleTime 16971750 # Total Idle time Per DRAM Rank 23911680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::IDLE 40500 # Time in different power states 24011680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::REF 780000 # Time in different power states 24111680SCurtis.Dunham@arm.comsystem.physmem_0.memoryStateTime::SREF 0 # Time in different power states 24211860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::PRE_PDN 340500 # Time in different power states 24311860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT 5886000 # Time in different power states 24411860Sandreas.hansson@arm.comsystem.physmem_0.memoryStateTime::ACT_PDN 16729000 # Time in different power states 24511680SCurtis.Dunham@arm.comsystem.physmem_1.actEnergy 399840 # Energy for activate commands per rank (pJ) 24611680SCurtis.Dunham@arm.comsystem.physmem_1.preEnergy 212520 # Energy for precharge commands per rank (pJ) 24711680SCurtis.Dunham@arm.comsystem.physmem_1.readEnergy 1699320 # Energy for read commands per rank (pJ) 24810628Sandreas.hansson@arm.comsystem.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 24911680SCurtis.Dunham@arm.comsystem.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) 25011860Sandreas.hansson@arm.comsystem.physmem_1.actBackEnergy 2975400 # Energy for active background per rank (pJ) 25111680SCurtis.Dunham@arm.comsystem.physmem_1.preBackEnergy 130080 # Energy for precharge background per rank (pJ) 25211860Sandreas.hansson@arm.comsystem.physmem_1.actPowerDownEnergy 7630590 # Energy for active power-down per rank (pJ) 25311860Sandreas.hansson@arm.comsystem.physmem_1.prePowerDownEnergy 68640 # Energy for precharge power-down per rank (pJ) 25411680SCurtis.Dunham@arm.comsystem.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 25511860Sandreas.hansson@arm.comsystem.physmem_1.totalEnergy 14960310 # Total energy per rank (pJ) 25611860Sandreas.hansson@arm.comsystem.physmem_1.averagePower 629.212344 # Core power per rank (mW) 25711860Sandreas.hansson@arm.comsystem.physmem_1.totalIdleTime 16765250 # Total Idle time Per DRAM Rank 25811680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::IDLE 214000 # Time in different power states 25911680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::REF 780000 # Time in different power states 26011680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::SREF 0 # Time in different power states 26111680SCurtis.Dunham@arm.comsystem.physmem_1.memoryStateTime::PRE_PDN 178500 # Time in different power states 26211860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT 5879250 # Time in different power states 26311860Sandreas.hansson@arm.comsystem.physmem_1.memoryStateTime::ACT_PDN 16724250 # Time in different power states 26411680SCurtis.Dunham@arm.comsystem.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 26511860Sandreas.hansson@arm.comsystem.cpu.branchPred.lookups 2851 # Number of BP lookups 26611860Sandreas.hansson@arm.comsystem.cpu.branchPred.condPredicted 1679 # Number of conditional branches predicted 26711860Sandreas.hansson@arm.comsystem.cpu.branchPred.condIncorrect 484 # Number of conditional branches incorrect 26811860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBLookups 2196 # Number of BTB lookups 26911860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHits 719 # Number of BTB hits 2709481Snilay@cs.wisc.edusystem.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 27111860Sandreas.hansson@arm.comsystem.cpu.branchPred.BTBHitPct 32.741348 # BTB Hit Percentage 27211860Sandreas.hansson@arm.comsystem.cpu.branchPred.usedRAS 442 # Number of times the RAS was used to get a target. 27311680SCurtis.Dunham@arm.comsystem.cpu.branchPred.RASInCorrect 42 # Number of incorrect RAS predictions. 27411860Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectLookups 461 # Number of indirect predictor lookups. 27511440SCurtis.Dunham@arm.comsystem.cpu.branchPred.indirectHits 25 # Number of indirect target hits. 27611860Sandreas.hansson@arm.comsystem.cpu.branchPred.indirectMisses 436 # Number of indirect misses. 27711440SCurtis.Dunham@arm.comsystem.cpu.branchPredindirectMispredicted 123 # Number of mispredicted indirect branches. 27810628Sandreas.hansson@arm.comsystem.cpu_clk_domain.clock 500 # Clock period in ticks 2798428SN/Asystem.cpu.dtb.fetch_hits 0 # ITB hits 2808428SN/Asystem.cpu.dtb.fetch_misses 0 # ITB misses 2818428SN/Asystem.cpu.dtb.fetch_acv 0 # ITB acv 2828428SN/Asystem.cpu.dtb.fetch_accesses 0 # ITB accesses 28311860Sandreas.hansson@arm.comsystem.cpu.dtb.read_hits 2241 # DTB read hits 28411440SCurtis.Dunham@arm.comsystem.cpu.dtb.read_misses 48 # DTB read misses 2858428SN/Asystem.cpu.dtb.read_acv 0 # DTB read access violations 28611860Sandreas.hansson@arm.comsystem.cpu.dtb.read_accesses 2289 # DTB read accesses 28711860Sandreas.hansson@arm.comsystem.cpu.dtb.write_hits 1046 # DTB write hits 28811103Snilay@cs.wisc.edusystem.cpu.dtb.write_misses 28 # DTB write misses 2898428SN/Asystem.cpu.dtb.write_acv 0 # DTB write access violations 29011860Sandreas.hansson@arm.comsystem.cpu.dtb.write_accesses 1074 # DTB write accesses 29111860Sandreas.hansson@arm.comsystem.cpu.dtb.data_hits 3287 # DTB hits 29211440SCurtis.Dunham@arm.comsystem.cpu.dtb.data_misses 76 # DTB misses 2938428SN/Asystem.cpu.dtb.data_acv 0 # DTB access violations 29411860Sandreas.hansson@arm.comsystem.cpu.dtb.data_accesses 3363 # DTB accesses 29511860Sandreas.hansson@arm.comsystem.cpu.itb.fetch_hits 2298 # ITB hits 29611440SCurtis.Dunham@arm.comsystem.cpu.itb.fetch_misses 27 # ITB misses 2978428SN/Asystem.cpu.itb.fetch_acv 0 # ITB acv 29811860Sandreas.hansson@arm.comsystem.cpu.itb.fetch_accesses 2325 # ITB accesses 2998428SN/Asystem.cpu.itb.read_hits 0 # DTB read hits 3008428SN/Asystem.cpu.itb.read_misses 0 # DTB read misses 3018428SN/Asystem.cpu.itb.read_acv 0 # DTB read access violations 3028428SN/Asystem.cpu.itb.read_accesses 0 # DTB read accesses 3038428SN/Asystem.cpu.itb.write_hits 0 # DTB write hits 3048428SN/Asystem.cpu.itb.write_misses 0 # DTB write misses 3058428SN/Asystem.cpu.itb.write_acv 0 # DTB write access violations 3068428SN/Asystem.cpu.itb.write_accesses 0 # DTB write accesses 3078428SN/Asystem.cpu.itb.data_hits 0 # DTB hits 3088428SN/Asystem.cpu.itb.data_misses 0 # DTB misses 3098428SN/Asystem.cpu.itb.data_acv 0 # DTB access violations 3108428SN/Asystem.cpu.itb.data_accesses 0 # DTB accesses 31111955Sgabeblack@google.comsystem.cpu.workload.numSyscalls 17 # Number of system calls 31211680SCurtis.Dunham@arm.comsystem.cpu.pwrStateResidencyTicks::ON 23776000 # Cumulative time (in ticks) in various power states 31311680SCurtis.Dunham@arm.comsystem.cpu.numCycles 47553 # number of cpu cycles simulated 3148428SN/Asystem.cpu.numWorkItemsStarted 0 # number of work items this cpu started 3158428SN/Asystem.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 31611860Sandreas.hansson@arm.comsystem.cpu.fetch.icacheStallCycles 8497 # Number of cycles fetch is stalled on an Icache miss 31711860Sandreas.hansson@arm.comsystem.cpu.fetch.Insts 16552 # Number of instructions fetch has processed 31811860Sandreas.hansson@arm.comsystem.cpu.fetch.Branches 2851 # Number of branches that fetch encountered 31911860Sandreas.hansson@arm.comsystem.cpu.fetch.predictedBranches 1186 # Number of branches that fetch has predicted taken 32011860Sandreas.hansson@arm.comsystem.cpu.fetch.Cycles 5772 # Number of cycles fetch has run and was not squashing or blocked 32111860Sandreas.hansson@arm.comsystem.cpu.fetch.SquashCycles 1050 # Number of cycles fetch has spent squashing 32211440SCurtis.Dunham@arm.comsystem.cpu.fetch.MiscStallCycles 22 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 32311606Sandreas.sandberg@arm.comsystem.cpu.fetch.PendingTrapStallCycles 656 # Number of stall cycles due to pending traps 32411860Sandreas.hansson@arm.comsystem.cpu.fetch.CacheLines 2298 # Number of cache lines fetched 32511860Sandreas.hansson@arm.comsystem.cpu.fetch.IcacheSquashes 338 # Number of outstanding Icache misses that were squashed 32611860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::samples 15472 # Number of instructions fetched each cycle (Total) 32711860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::mean 1.069804 # Number of instructions fetched each cycle (Total) 32811860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::stdev 2.455665 # Number of instructions fetched each cycle (Total) 3296291SN/Asystem.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 33011860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::0 12480 80.66% 80.66% # Number of instructions fetched each cycle (Total) 33111860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::1 299 1.93% 82.59% # Number of instructions fetched each cycle (Total) 33211860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::2 231 1.49% 84.09% # Number of instructions fetched each cycle (Total) 33311860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::3 265 1.71% 85.80% # Number of instructions fetched each cycle (Total) 33411860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::4 295 1.91% 87.71% # Number of instructions fetched each cycle (Total) 33511860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::5 231 1.49% 89.20% # Number of instructions fetched each cycle (Total) 33611860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::6 280 1.81% 91.01% # Number of instructions fetched each cycle (Total) 33711860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::7 147 0.95% 91.96% # Number of instructions fetched each cycle (Total) 33811860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::8 1244 8.04% 100.00% # Number of instructions fetched each cycle (Total) 3396291SN/Asystem.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 3406291SN/Asystem.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 3416291SN/Asystem.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 34211860Sandreas.hansson@arm.comsystem.cpu.fetch.rateDist::total 15472 # Number of instructions fetched each cycle (Total) 34311860Sandreas.hansson@arm.comsystem.cpu.fetch.branchRate 0.059954 # Number of branch fetches per cycle 34411860Sandreas.hansson@arm.comsystem.cpu.fetch.rate 0.348075 # Number of inst fetches per cycle 34511860Sandreas.hansson@arm.comsystem.cpu.decode.IdleCycles 8344 # Number of cycles decode is idle 34611860Sandreas.hansson@arm.comsystem.cpu.decode.BlockedCycles 4012 # Number of cycles decode is blocked 34711860Sandreas.hansson@arm.comsystem.cpu.decode.RunCycles 2454 # Number of cycles decode is running 34811860Sandreas.hansson@arm.comsystem.cpu.decode.UnblockCycles 211 # Number of cycles decode is unblocking 34911860Sandreas.hansson@arm.comsystem.cpu.decode.SquashCycles 451 # Number of cycles decode is squashing 35011860Sandreas.hansson@arm.comsystem.cpu.decode.BranchResolved 754 # Number of times decode resolved a branch 35111440SCurtis.Dunham@arm.comsystem.cpu.decode.BranchMispred 75 # Number of times decode detected a branch misprediction 35211860Sandreas.hansson@arm.comsystem.cpu.decode.DecodedInsts 14992 # Number of instructions handled by decode 35311440SCurtis.Dunham@arm.comsystem.cpu.decode.SquashedInsts 221 # Number of squashed instructions handled by decode 35411860Sandreas.hansson@arm.comsystem.cpu.rename.SquashCycles 451 # Number of cycles rename is squashing 35511860Sandreas.hansson@arm.comsystem.cpu.rename.IdleCycles 8504 # Number of cycles rename is idle 35611860Sandreas.hansson@arm.comsystem.cpu.rename.BlockCycles 1836 # Number of cycles rename is blocking 35711680SCurtis.Dunham@arm.comsystem.cpu.rename.serializeStallCycles 655 # count of cycles rename stalled for serializing inst 35811860Sandreas.hansson@arm.comsystem.cpu.rename.RunCycles 2480 # Number of cycles rename is running 35911860Sandreas.hansson@arm.comsystem.cpu.rename.UnblockCycles 1546 # Number of cycles rename is unblocking 36011860Sandreas.hansson@arm.comsystem.cpu.rename.RenamedInsts 14425 # Number of instructions processed by rename 36111440SCurtis.Dunham@arm.comsystem.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full 36211440SCurtis.Dunham@arm.comsystem.cpu.rename.IQFullEvents 21 # Number of times rename has blocked due to IQ full 36311440SCurtis.Dunham@arm.comsystem.cpu.rename.LQFullEvents 10 # Number of times rename has blocked due to LQ full 36411860Sandreas.hansson@arm.comsystem.cpu.rename.SQFullEvents 1479 # Number of times rename has blocked due to SQ full 36511860Sandreas.hansson@arm.comsystem.cpu.rename.RenamedOperands 10912 # Number of destination operands rename has renamed 36611860Sandreas.hansson@arm.comsystem.cpu.rename.RenameLookups 17882 # Number of register rename lookups that rename has made 36711860Sandreas.hansson@arm.comsystem.cpu.rename.int_rename_lookups 17873 # Number of integer rename lookups 3689924Ssteve.reinhardt@amd.comsystem.cpu.rename.fp_rename_lookups 8 # Number of floating rename lookups 36911390Ssteve.reinhardt@amd.comsystem.cpu.rename.CommittedMaps 4577 # Number of HB maps that are committed 37011860Sandreas.hansson@arm.comsystem.cpu.rename.UndoneMaps 6335 # Number of HB maps that are undone due to squashing 37111440SCurtis.Dunham@arm.comsystem.cpu.rename.serializingInsts 28 # count of serializing insts renamed 37211440SCurtis.Dunham@arm.comsystem.cpu.rename.tempSerializingInsts 22 # count of temporary serializing insts renamed 37311860Sandreas.hansson@arm.comsystem.cpu.rename.skidInsts 586 # count of insts added to the skid buffer 37411860Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedLoads 2823 # Number of loads inserted to the mem dependence unit. 37511860Sandreas.hansson@arm.comsystem.cpu.memDep0.insertedStores 1299 # Number of stores inserted to the mem dependence unit. 37611860Sandreas.hansson@arm.comsystem.cpu.memDep0.conflictingLoads 17 # Number of conflicting loads. 37711440SCurtis.Dunham@arm.comsystem.cpu.memDep0.conflictingStores 6 # Number of conflicting stores. 37811860Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsAdded 13035 # Number of instructions added to the IQ (excludes non-spec) 37911440SCurtis.Dunham@arm.comsystem.cpu.iq.iqNonSpecInstsAdded 27 # Number of non-speculative instructions added to the IQ 38011860Sandreas.hansson@arm.comsystem.cpu.iq.iqInstsIssued 10770 # Number of instructions issued 38111440SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedInstsIssued 17 # Number of squashed instructions issued 38211860Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedInstsExamined 6676 # Number of squashed instructions iterated over during squash; mainly for profiling 38311860Sandreas.hansson@arm.comsystem.cpu.iq.iqSquashedOperandsExamined 3655 # Number of squashed operands that are examined and possibly removed from graph 38411440SCurtis.Dunham@arm.comsystem.cpu.iq.iqSquashedNonSpecRemoved 10 # Number of squashed non-spec instructions that were removed 38511860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::samples 15472 # Number of insts issued each cycle 38611860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::mean 0.696096 # Number of insts issued each cycle 38711860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::stdev 1.440906 # Number of insts issued each cycle 3888428SN/Asystem.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 38911860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::0 11426 73.85% 73.85% # Number of insts issued each cycle 39011860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::1 1307 8.45% 82.30% # Number of insts issued each cycle 39111860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::2 919 5.94% 88.24% # Number of insts issued each cycle 39211860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::3 676 4.37% 92.61% # Number of insts issued each cycle 39311860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::4 515 3.33% 95.93% # Number of insts issued each cycle 39411860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::5 346 2.24% 98.17% # Number of insts issued each cycle 39511860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::6 202 1.31% 99.48% # Number of insts issued each cycle 39611860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::7 53 0.34% 99.82% # Number of insts issued each cycle 39711860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::8 28 0.18% 100.00% # Number of insts issued each cycle 3988428SN/Asystem.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 3998428SN/Asystem.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 4008428SN/Asystem.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 40111860Sandreas.hansson@arm.comsystem.cpu.iq.issued_per_cycle::total 15472 # Number of insts issued each cycle 4028428SN/Asystem.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 40311860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntAlu 21 14.79% 14.79% # attempts to use FU when none available 40411860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntMult 0 0.00% 14.79% # attempts to use FU when none available 40511860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::IntDiv 0 0.00% 14.79% # attempts to use FU when none available 40611860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatAdd 0 0.00% 14.79% # attempts to use FU when none available 40711860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCmp 0 0.00% 14.79% # attempts to use FU when none available 40811860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatCvt 0 0.00% 14.79% # attempts to use FU when none available 40911860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMult 0 0.00% 14.79% # attempts to use FU when none available 41011860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMultAcc 0 0.00% 14.79% # attempts to use FU when none available 41111860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatDiv 0 0.00% 14.79% # attempts to use FU when none available 41211860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMisc 0 0.00% 14.79% # attempts to use FU when none available 41311860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatSqrt 0 0.00% 14.79% # attempts to use FU when none available 41411860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAdd 0 0.00% 14.79% # attempts to use FU when none available 41511860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAddAcc 0 0.00% 14.79% # attempts to use FU when none available 41611860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdAlu 0 0.00% 14.79% # attempts to use FU when none available 41711860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCmp 0 0.00% 14.79% # attempts to use FU when none available 41811860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdCvt 0 0.00% 14.79% # attempts to use FU when none available 41911860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMisc 0 0.00% 14.79% # attempts to use FU when none available 42011860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMult 0 0.00% 14.79% # attempts to use FU when none available 42111860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdMultAcc 0 0.00% 14.79% # attempts to use FU when none available 42211860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShift 0 0.00% 14.79% # attempts to use FU when none available 42311860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 14.79% # attempts to use FU when none available 42411860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdSqrt 0 0.00% 14.79% # attempts to use FU when none available 42511860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 14.79% # attempts to use FU when none available 42611860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 14.79% # attempts to use FU when none available 42711860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 14.79% # attempts to use FU when none available 42811860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 14.79% # attempts to use FU when none available 42911860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 14.79% # attempts to use FU when none available 43011860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 14.79% # attempts to use FU when none available 43111860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMult 0 0.00% 14.79% # attempts to use FU when none available 43211860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 14.79% # attempts to use FU when none available 43311860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 14.79% # attempts to use FU when none available 43411860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemRead 83 58.45% 73.24% # attempts to use FU when none available 43511860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::MemWrite 37 26.06% 99.30% # attempts to use FU when none available 43611860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMemRead 0 0.00% 99.30% # attempts to use FU when none available 43711860Sandreas.hansson@arm.comsystem.cpu.iq.fu_full::FloatMemWrite 1 0.70% 100.00% # attempts to use FU when none available 4388428SN/Asystem.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 4398428SN/Asystem.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 4408241SN/Asystem.cpu.iq.FU_type_0::No_OpClass 2 0.02% 0.02% # Type of FU issued 44111860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntAlu 7179 66.66% 66.68% # Type of FU issued 44211860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntMult 1 0.01% 66.69% # Type of FU issued 44311860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::IntDiv 0 0.00% 66.69% # Type of FU issued 44411860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatAdd 2 0.02% 66.70% # Type of FU issued 44511860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCmp 0 0.00% 66.70% # Type of FU issued 44611860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatCvt 0 0.00% 66.70% # Type of FU issued 44711860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMult 0 0.00% 66.70% # Type of FU issued 44811860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 66.70% # Type of FU issued 44911860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatDiv 0 0.00% 66.70% # Type of FU issued 45011860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMisc 0 0.00% 66.70% # Type of FU issued 45111860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 66.70% # Type of FU issued 45211860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAdd 0 0.00% 66.70% # Type of FU issued 45311860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 66.70% # Type of FU issued 45411860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdAlu 0 0.00% 66.70% # Type of FU issued 45511860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCmp 0 0.00% 66.70% # Type of FU issued 45611860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdCvt 0 0.00% 66.70% # Type of FU issued 45711860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMisc 0 0.00% 66.70% # Type of FU issued 45811860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMult 0 0.00% 66.70% # Type of FU issued 45911860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 66.70% # Type of FU issued 46011860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShift 0 0.00% 66.70% # Type of FU issued 46111860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 66.70% # Type of FU issued 46211860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 66.70% # Type of FU issued 46311860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 66.70% # Type of FU issued 46411860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 66.70% # Type of FU issued 46511860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 66.70% # Type of FU issued 46611860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 66.70% # Type of FU issued 46711860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 66.70% # Type of FU issued 46811860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 66.70% # Type of FU issued 46911860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 66.70% # Type of FU issued 47011860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 66.70% # Type of FU issued 47111860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 66.70% # Type of FU issued 47211860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemRead 2465 22.89% 89.59% # Type of FU issued 47311860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::MemWrite 1113 10.33% 99.93% # Type of FU issued 47411687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMemRead 1 0.01% 99.94% # Type of FU issued 47511687Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::FloatMemWrite 7 0.06% 100.00% # Type of FU issued 4768241SN/Asystem.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 4778241SN/Asystem.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 47811860Sandreas.hansson@arm.comsystem.cpu.iq.FU_type_0::total 10770 # Type of FU issued 47911860Sandreas.hansson@arm.comsystem.cpu.iq.rate 0.226484 # Inst issue rate 48011860Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_cnt 142 # FU busy when requested 48111860Sandreas.hansson@arm.comsystem.cpu.iq.fu_busy_rate 0.013185 # FU busy rate (busy events/executed inst) 48211860Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_reads 37150 # Number of integer instruction queue reads 48311860Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_writes 19749 # Number of integer instruction queue writes 48411860Sandreas.hansson@arm.comsystem.cpu.iq.int_inst_queue_wakeup_accesses 9744 # Number of integer instruction queue wakeup accesses 4858428SN/Asystem.cpu.iq.fp_inst_queue_reads 21 # Number of floating instruction queue reads 4868428SN/Asystem.cpu.iq.fp_inst_queue_writes 10 # Number of floating instruction queue writes 4878428SN/Asystem.cpu.iq.fp_inst_queue_wakeup_accesses 10 # Number of floating instruction queue wakeup accesses 48811860Sandreas.hansson@arm.comsystem.cpu.iq.int_alu_accesses 10899 # Number of integer alu accesses 4898428SN/Asystem.cpu.iq.fp_alu_accesses 11 # Number of floating point alu accesses 49011440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.forwLoads 119 # Number of loads that had data forwarded from stores 4918428SN/Asystem.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 49211860Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedLoads 1638 # Number of loads squashed 49311440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed 49411440SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.memOrderViolation 23 # Number of memory ordering violations 49511860Sandreas.hansson@arm.comsystem.cpu.iew.lsq.thread0.squashedStores 434 # Number of stores squashed 4968428SN/Asystem.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 4978428SN/Asystem.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 4988428SN/Asystem.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 49911680SCurtis.Dunham@arm.comsystem.cpu.iew.lsq.thread0.cacheBlocked 78 # Number of times an access to memory failed due to the cache being blocked 5008428SN/Asystem.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 50111860Sandreas.hansson@arm.comsystem.cpu.iew.iewSquashCycles 451 # Number of cycles IEW is squashing 50211860Sandreas.hansson@arm.comsystem.cpu.iew.iewBlockCycles 1424 # Number of cycles IEW is blocking 50311680SCurtis.Dunham@arm.comsystem.cpu.iew.iewUnblockCycles 338 # Number of cycles IEW is unblocking 50411860Sandreas.hansson@arm.comsystem.cpu.iew.iewDispatchedInsts 13146 # Number of instructions dispatched to IQ 50511440SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispSquashedInsts 125 # Number of squashed instructions skipped by dispatch 50611860Sandreas.hansson@arm.comsystem.cpu.iew.iewDispLoadInsts 2823 # Number of dispatched load instructions 50711860Sandreas.hansson@arm.comsystem.cpu.iew.iewDispStoreInsts 1299 # Number of dispatched store instructions 50811440SCurtis.Dunham@arm.comsystem.cpu.iew.iewDispNonSpecInsts 27 # Number of dispatched non-speculative instructions 50911440SCurtis.Dunham@arm.comsystem.cpu.iew.iewIQFullEvents 7 # Number of times the IQ has become full, causing a stall 51011680SCurtis.Dunham@arm.comsystem.cpu.iew.iewLSQFullEvents 331 # Number of times the LSQ has become full, causing a stall 51111440SCurtis.Dunham@arm.comsystem.cpu.iew.memOrderViolationEvents 23 # Number of memory order violations 51211860Sandreas.hansson@arm.comsystem.cpu.iew.predictedTakenIncorrect 110 # Number of branches that were predicted taken incorrectly 51311860Sandreas.hansson@arm.comsystem.cpu.iew.predictedNotTakenIncorrect 389 # Number of branches that were predicted not taken incorrectly 51411860Sandreas.hansson@arm.comsystem.cpu.iew.branchMispredicts 499 # Number of branch mispredicts detected at execute 51511860Sandreas.hansson@arm.comsystem.cpu.iew.iewExecutedInsts 10283 # Number of executed instructions 51611860Sandreas.hansson@arm.comsystem.cpu.iew.iewExecLoadInsts 2289 # Number of load instructions executed 51711860Sandreas.hansson@arm.comsystem.cpu.iew.iewExecSquashedInsts 487 # Number of squashed instructions skipped in execute 5188428SN/Asystem.cpu.iew.exec_swp 0 # number of swp insts executed 51911440SCurtis.Dunham@arm.comsystem.cpu.iew.exec_nop 84 # number of nop insts executed 52011860Sandreas.hansson@arm.comsystem.cpu.iew.exec_refs 3373 # number of memory reference insts executed 52111860Sandreas.hansson@arm.comsystem.cpu.iew.exec_branches 1639 # Number of branches executed 52211860Sandreas.hansson@arm.comsystem.cpu.iew.exec_stores 1084 # Number of stores executed 52311860Sandreas.hansson@arm.comsystem.cpu.iew.exec_rate 0.216243 # Inst execution rate 52411860Sandreas.hansson@arm.comsystem.cpu.iew.wb_sent 9942 # cumulative count of insts sent to commit 52511860Sandreas.hansson@arm.comsystem.cpu.iew.wb_count 9754 # cumulative count of insts written-back 52611860Sandreas.hansson@arm.comsystem.cpu.iew.wb_producers 5150 # num instructions producing a value 52711680SCurtis.Dunham@arm.comsystem.cpu.iew.wb_consumers 7025 # num instructions consuming a value 52811860Sandreas.hansson@arm.comsystem.cpu.iew.wb_rate 0.205118 # insts written-back per cycle 52911860Sandreas.hansson@arm.comsystem.cpu.iew.wb_fanout 0.733096 # average fanout of values written-back 53011860Sandreas.hansson@arm.comsystem.cpu.commit.commitSquashedInsts 6693 # The number of squashed insts skipped by commit 5318428SN/Asystem.cpu.commit.commitNonSpecStalls 17 # The number of times commit has been forced to stall to communicate backwards 53211860Sandreas.hansson@arm.comsystem.cpu.commit.branchMispredicts 410 # The number of times a branch was mispredicted 53311860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::samples 14238 # Number of insts commited each cycle 53411860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::mean 0.449642 # Number of insts commited each cycle 53511860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::stdev 1.359190 # Number of insts commited each cycle 5368428SN/Asystem.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 53711860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::0 11808 82.93% 82.93% # Number of insts commited each cycle 53811860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::1 1161 8.15% 91.09% # Number of insts commited each cycle 53911860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::2 469 3.29% 94.38% # Number of insts commited each cycle 54011860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::3 204 1.43% 95.81% # Number of insts commited each cycle 54111860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::4 134 0.94% 96.76% # Number of insts commited each cycle 54211860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::5 86 0.60% 97.36% # Number of insts commited each cycle 54311860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::6 97 0.68% 98.04% # Number of insts commited each cycle 54411860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::7 89 0.63% 98.67% # Number of insts commited each cycle 54511860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::8 190 1.33% 100.00% # Number of insts commited each cycle 5468428SN/Asystem.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 5478428SN/Asystem.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 5488428SN/Asystem.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 54911860Sandreas.hansson@arm.comsystem.cpu.commit.committed_per_cycle::total 14238 # Number of insts commited each cycle 55011390Ssteve.reinhardt@amd.comsystem.cpu.commit.committedInsts 6402 # Number of instructions committed 55111390Ssteve.reinhardt@amd.comsystem.cpu.commit.committedOps 6402 # Number of ops (including micro ops) committed 5528428SN/Asystem.cpu.commit.swp_count 0 # Number of s/w prefetches committed 55311390Ssteve.reinhardt@amd.comsystem.cpu.commit.refs 2050 # Number of memory references committed 55411390Ssteve.reinhardt@amd.comsystem.cpu.commit.loads 1185 # Number of loads committed 5558428SN/Asystem.cpu.commit.membars 0 # Number of memory barriers committed 55611390Ssteve.reinhardt@amd.comsystem.cpu.commit.branches 1056 # Number of branches committed 5578428SN/Asystem.cpu.commit.fp_insts 10 # Number of committed floating point instructions. 55811390Ssteve.reinhardt@amd.comsystem.cpu.commit.int_insts 6319 # Number of committed integer instructions. 5598428SN/Asystem.cpu.commit.function_calls 127 # Number of function calls committed. 56010220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::No_OpClass 19 0.30% 0.30% # Class of committed instruction 56111390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::IntAlu 4330 67.64% 67.93% # Class of committed instruction 56211390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::IntMult 1 0.02% 67.95% # Class of committed instruction 56311390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::IntDiv 0 0.00% 67.95% # Class of committed instruction 56411390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatAdd 2 0.03% 67.98% # Class of committed instruction 56511390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatCmp 0 0.00% 67.98% # Class of committed instruction 56611390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatCvt 0 0.00% 67.98% # Class of committed instruction 56711390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatMult 0 0.00% 67.98% # Class of committed instruction 56811687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMultAcc 0 0.00% 67.98% # Class of committed instruction 56911390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatDiv 0 0.00% 67.98% # Class of committed instruction 57011687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMisc 0 0.00% 67.98% # Class of committed instruction 57111390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::FloatSqrt 0 0.00% 67.98% # Class of committed instruction 57211390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdAdd 0 0.00% 67.98% # Class of committed instruction 57311390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 67.98% # Class of committed instruction 57411390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdAlu 0 0.00% 67.98% # Class of committed instruction 57511390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdCmp 0 0.00% 67.98% # Class of committed instruction 57611390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdCvt 0 0.00% 67.98% # Class of committed instruction 57711390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdMisc 0 0.00% 67.98% # Class of committed instruction 57811390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdMult 0 0.00% 67.98% # Class of committed instruction 57911390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 67.98% # Class of committed instruction 58011390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdShift 0 0.00% 67.98% # Class of committed instruction 58111390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 67.98% # Class of committed instruction 58211390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdSqrt 0 0.00% 67.98% # Class of committed instruction 58311390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 67.98% # Class of committed instruction 58411390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 67.98% # Class of committed instruction 58511390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 67.98% # Class of committed instruction 58611390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 67.98% # Class of committed instruction 58711390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 67.98% # Class of committed instruction 58811390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 67.98% # Class of committed instruction 58911390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 67.98% # Class of committed instruction 59011390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 67.98% # Class of committed instruction 59111390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 67.98% # Class of committed instruction 59211687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemRead 1184 18.49% 86.47% # Class of committed instruction 59311687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::MemWrite 858 13.40% 99.88% # Class of committed instruction 59411687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMemRead 1 0.02% 99.89% # Class of committed instruction 59511687Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::FloatMemWrite 7 0.11% 100.00% # Class of committed instruction 59610220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 59710220Sandreas.hansson@arm.comsystem.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 59811390Ssteve.reinhardt@amd.comsystem.cpu.commit.op_class_0::total 6402 # Class of committed instruction 59911860Sandreas.hansson@arm.comsystem.cpu.commit.bw_lim_events 190 # number cycles where commit BW limit reached 60011731Sjason@lowepower.comsystem.cpu.rob.rob_reads 26792 # The number of ROB reads 60111860Sandreas.hansson@arm.comsystem.cpu.rob.rob_writes 27441 # The number of ROB writes 60211606Sandreas.sandberg@arm.comsystem.cpu.timesIdled 250 # Number of times that the entire CPU went into an idle state and unscheduled itself 60311860Sandreas.hansson@arm.comsystem.cpu.idleCycles 32081 # Total number of cycles that the CPU has spent unscheduled due to idling 60411390Ssteve.reinhardt@amd.comsystem.cpu.committedInsts 6385 # Number of Instructions Simulated 60511390Ssteve.reinhardt@amd.comsystem.cpu.committedOps 6385 # Number of Ops (including micro ops) Simulated 60611680SCurtis.Dunham@arm.comsystem.cpu.cpi 7.447612 # CPI: Cycles Per Instruction 60711680SCurtis.Dunham@arm.comsystem.cpu.cpi_total 7.447612 # CPI: Total CPI of All Threads 60811680SCurtis.Dunham@arm.comsystem.cpu.ipc 0.134271 # IPC: Instructions Per Cycle 60911680SCurtis.Dunham@arm.comsystem.cpu.ipc_total 0.134271 # IPC: Total IPC of All Threads 61011860Sandreas.hansson@arm.comsystem.cpu.int_regfile_reads 13028 # number of integer regfile reads 61111860Sandreas.hansson@arm.comsystem.cpu.int_regfile_writes 7426 # number of integer regfile writes 6128428SN/Asystem.cpu.fp_regfile_reads 8 # number of floating regfile reads 6138428SN/Asystem.cpu.fp_regfile_writes 2 # number of floating regfile writes 6148428SN/Asystem.cpu.misc_regfile_reads 1 # number of misc regfile reads 6158428SN/Asystem.cpu.misc_regfile_writes 1 # number of misc regfile writes 61611680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 61710628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.replacements 0 # number of replacements 61811860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tagsinuse 110.199847 # Cycle average of tags in use 61911860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.total_refs 2391 # Total number of references to valid blocks. 62011390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.sampled_refs 173 # Sample count of references to valid blocks. 62111860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.avg_refs 13.820809 # Average number of references to valid blocks. 62210628Sandreas.hansson@arm.comsystem.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 62311860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_blocks::cpu.data 110.199847 # Average occupied blocks per requestor 62411860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::cpu.data 0.026904 # Average percentage of cache occupancy 62511860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.occ_percent::total 0.026904 # Average percentage of cache occupancy 62611390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.occ_task_id_blocks::1024 173 # Occupied blocks per task id 62711680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::0 42 # Occupied blocks per task id 62811680SCurtis.Dunham@arm.comsystem.cpu.dcache.tags.age_task_id_blocks_1024::1 131 # Occupied blocks per task id 62911390Ssteve.reinhardt@amd.comsystem.cpu.dcache.tags.occ_task_id_percent::1024 0.042236 # Percentage of cache occupancy per task id 63011860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.tag_accesses 6029 # Number of tag accesses 63111860Sandreas.hansson@arm.comsystem.cpu.dcache.tags.data_accesses 6029 # Number of data accesses 63211680SCurtis.Dunham@arm.comsystem.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 63311860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::cpu.data 1883 # number of ReadReq hits 63411860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_hits::total 1883 # number of ReadReq hits 63511606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_hits::cpu.data 508 # number of WriteReq hits 63611606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_hits::total 508 # number of WriteReq hits 63711860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::cpu.data 2391 # number of demand (read+write) hits 63811860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_hits::total 2391 # number of demand (read+write) hits 63911860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::cpu.data 2391 # number of overall hits 64011860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_hits::total 2391 # number of overall hits 64111440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::cpu.data 180 # number of ReadReq misses 64211440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_misses::total 180 # number of ReadReq misses 64311606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_misses::cpu.data 357 # number of WriteReq misses 64411606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_misses::total 357 # number of WriteReq misses 64511606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_misses::cpu.data 537 # number of demand (read+write) misses 64611606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_misses::total 537 # number of demand (read+write) misses 64711606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_misses::cpu.data 537 # number of overall misses 64811606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_misses::total 537 # number of overall misses 64911860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::cpu.data 13954000 # number of ReadReq miss cycles 65011860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_latency::total 13954000 # number of ReadReq miss cycles 65111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::cpu.data 31258982 # number of WriteReq miss cycles 65211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_miss_latency::total 31258982 # number of WriteReq miss cycles 65311860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::cpu.data 45212982 # number of demand (read+write) miss cycles 65411860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_latency::total 45212982 # number of demand (read+write) miss cycles 65511860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::cpu.data 45212982 # number of overall miss cycles 65611860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_latency::total 45212982 # number of overall miss cycles 65711860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::cpu.data 2063 # number of ReadReq accesses(hits+misses) 65811860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_accesses::total 2063 # number of ReadReq accesses(hits+misses) 65910628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::cpu.data 865 # number of WriteReq accesses(hits+misses) 66010628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_accesses::total 865 # number of WriteReq accesses(hits+misses) 66111860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::cpu.data 2928 # number of demand (read+write) accesses 66211860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_accesses::total 2928 # number of demand (read+write) accesses 66311860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::cpu.data 2928 # number of overall (read+write) accesses 66411860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_accesses::total 2928 # number of overall (read+write) accesses 66511860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::cpu.data 0.087252 # miss rate for ReadReq accesses 66611860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_miss_rate::total 0.087252 # miss rate for ReadReq accesses 66711606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_rate::cpu.data 0.412717 # miss rate for WriteReq accesses 66811606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_miss_rate::total 0.412717 # miss rate for WriteReq accesses 66911860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::cpu.data 0.183402 # miss rate for demand accesses 67011860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_miss_rate::total 0.183402 # miss rate for demand accesses 67111860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::cpu.data 0.183402 # miss rate for overall accesses 67211860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_miss_rate::total 0.183402 # miss rate for overall accesses 67311860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 77522.222222 # average ReadReq miss latency 67411860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_miss_latency::total 77522.222222 # average ReadReq miss latency 67511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 87560.173669 # average WriteReq miss latency 67611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_miss_latency::total 87560.173669 # average WriteReq miss latency 67711860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::cpu.data 84195.497207 # average overall miss latency 67811860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_miss_latency::total 84195.497207 # average overall miss latency 67911860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::cpu.data 84195.497207 # average overall miss latency 68011860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_miss_latency::total 84195.497207 # average overall miss latency 68111860Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_mshrs 3108 # number of cycles access was blocked 68210628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 68311680SCurtis.Dunham@arm.comsystem.cpu.dcache.blocked::no_mshrs 37 # number of cycles access was blocked 68410628Sandreas.hansson@arm.comsystem.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 68511860Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_mshrs 84 # average number of cycles each access was blocked 68610628Sandreas.hansson@arm.comsystem.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 68711440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::cpu.data 79 # number of ReadReq MSHR hits 68811440SCurtis.Dunham@arm.comsystem.cpu.dcache.ReadReq_mshr_hits::total 79 # number of ReadReq MSHR hits 68911606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::cpu.data 285 # number of WriteReq MSHR hits 69011606Sandreas.sandberg@arm.comsystem.cpu.dcache.WriteReq_mshr_hits::total 285 # number of WriteReq MSHR hits 69111606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_hits::cpu.data 364 # number of demand (read+write) MSHR hits 69211606Sandreas.sandberg@arm.comsystem.cpu.dcache.demand_mshr_hits::total 364 # number of demand (read+write) MSHR hits 69311606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_hits::cpu.data 364 # number of overall MSHR hits 69411606Sandreas.sandberg@arm.comsystem.cpu.dcache.overall_mshr_hits::total 364 # number of overall MSHR hits 69511390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_misses::cpu.data 101 # number of ReadReq MSHR misses 69611390Ssteve.reinhardt@amd.comsystem.cpu.dcache.ReadReq_mshr_misses::total 101 # number of ReadReq MSHR misses 69710628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::cpu.data 72 # number of WriteReq MSHR misses 69810628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_misses::total 72 # number of WriteReq MSHR misses 69911390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses 70011390Ssteve.reinhardt@amd.comsystem.cpu.dcache.demand_mshr_misses::total 173 # number of demand (read+write) MSHR misses 70111390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses 70211390Ssteve.reinhardt@amd.comsystem.cpu.dcache.overall_mshr_misses::total 173 # number of overall MSHR misses 70311860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 9402500 # number of ReadReq MSHR miss cycles 70411860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_latency::total 9402500 # number of ReadReq MSHR miss cycles 70511860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 7030000 # number of WriteReq MSHR miss cycles 70611860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_latency::total 7030000 # number of WriteReq MSHR miss cycles 70711860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::cpu.data 16432500 # number of demand (read+write) MSHR miss cycles 70811860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_latency::total 16432500 # number of demand (read+write) MSHR miss cycles 70911860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::cpu.data 16432500 # number of overall MSHR miss cycles 71011860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_latency::total 16432500 # number of overall MSHR miss cycles 71111860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.048958 # mshr miss rate for ReadReq accesses 71211860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_mshr_miss_rate::total 0.048958 # mshr miss rate for ReadReq accesses 71310628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.083237 # mshr miss rate for WriteReq accesses 71410628Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_mshr_miss_rate::total 0.083237 # mshr miss rate for WriteReq accesses 71511860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.059085 # mshr miss rate for demand accesses 71611860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_mshr_miss_rate::total 0.059085 # mshr miss rate for demand accesses 71711860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.059085 # mshr miss rate for overall accesses 71811860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_mshr_miss_rate::total 0.059085 # mshr miss rate for overall accesses 71911860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 93094.059406 # average ReadReq mshr miss latency 72011860Sandreas.hansson@arm.comsystem.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 93094.059406 # average ReadReq mshr miss latency 72111860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 97638.888889 # average WriteReq mshr miss latency 72211860Sandreas.hansson@arm.comsystem.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 97638.888889 # average WriteReq mshr miss latency 72311860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 94985.549133 # average overall mshr miss latency 72411860Sandreas.hansson@arm.comsystem.cpu.dcache.demand_avg_mshr_miss_latency::total 94985.549133 # average overall mshr miss latency 72511860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 94985.549133 # average overall mshr miss latency 72611860Sandreas.hansson@arm.comsystem.cpu.dcache.overall_avg_mshr_miss_latency::total 94985.549133 # average overall mshr miss latency 72711680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 7289838Sandreas.hansson@arm.comsystem.cpu.icache.tags.replacements 0 # number of replacements 72911860Sandreas.hansson@arm.comsystem.cpu.icache.tags.tagsinuse 160.011089 # Cycle average of tags in use 73011860Sandreas.hansson@arm.comsystem.cpu.icache.tags.total_refs 1840 # Total number of references to valid blocks. 73111860Sandreas.hansson@arm.comsystem.cpu.icache.tags.sampled_refs 312 # Sample count of references to valid blocks. 73211860Sandreas.hansson@arm.comsystem.cpu.icache.tags.avg_refs 5.897436 # Average number of references to valid blocks. 7339838Sandreas.hansson@arm.comsystem.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 73411860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_blocks::cpu.inst 160.011089 # Average occupied blocks per requestor 73511860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::cpu.inst 0.078130 # Average percentage of cache occupancy 73611860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_percent::total 0.078130 # Average percentage of cache occupancy 73711860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_blocks::1024 312 # Occupied blocks per task id 73811680SCurtis.Dunham@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::0 126 # Occupied blocks per task id 73911860Sandreas.hansson@arm.comsystem.cpu.icache.tags.age_task_id_blocks_1024::1 186 # Occupied blocks per task id 74011860Sandreas.hansson@arm.comsystem.cpu.icache.tags.occ_task_id_percent::1024 0.152344 # Percentage of cache occupancy per task id 74111860Sandreas.hansson@arm.comsystem.cpu.icache.tags.tag_accesses 4908 # Number of tag accesses 74211860Sandreas.hansson@arm.comsystem.cpu.icache.tags.data_accesses 4908 # Number of data accesses 74311680SCurtis.Dunham@arm.comsystem.cpu.icache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 74411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::cpu.inst 1840 # number of ReadReq hits 74511860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_hits::total 1840 # number of ReadReq hits 74611860Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::cpu.inst 1840 # number of demand (read+write) hits 74711860Sandreas.hansson@arm.comsystem.cpu.icache.demand_hits::total 1840 # number of demand (read+write) hits 74811860Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::cpu.inst 1840 # number of overall hits 74911860Sandreas.hansson@arm.comsystem.cpu.icache.overall_hits::total 1840 # number of overall hits 75011680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::cpu.inst 458 # number of ReadReq misses 75111680SCurtis.Dunham@arm.comsystem.cpu.icache.ReadReq_misses::total 458 # number of ReadReq misses 75211680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::cpu.inst 458 # number of demand (read+write) misses 75311680SCurtis.Dunham@arm.comsystem.cpu.icache.demand_misses::total 458 # number of demand (read+write) misses 75411680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::cpu.inst 458 # number of overall misses 75511680SCurtis.Dunham@arm.comsystem.cpu.icache.overall_misses::total 458 # number of overall misses 75611860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::cpu.inst 35481000 # number of ReadReq miss cycles 75711860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_latency::total 35481000 # number of ReadReq miss cycles 75811860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::cpu.inst 35481000 # number of demand (read+write) miss cycles 75911860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_latency::total 35481000 # number of demand (read+write) miss cycles 76011860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::cpu.inst 35481000 # number of overall miss cycles 76111860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_latency::total 35481000 # number of overall miss cycles 76211860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::cpu.inst 2298 # number of ReadReq accesses(hits+misses) 76311860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_accesses::total 2298 # number of ReadReq accesses(hits+misses) 76411860Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::cpu.inst 2298 # number of demand (read+write) accesses 76511860Sandreas.hansson@arm.comsystem.cpu.icache.demand_accesses::total 2298 # number of demand (read+write) accesses 76611860Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::cpu.inst 2298 # number of overall (read+write) accesses 76711860Sandreas.hansson@arm.comsystem.cpu.icache.overall_accesses::total 2298 # number of overall (read+write) accesses 76811860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::cpu.inst 0.199304 # miss rate for ReadReq accesses 76911860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_miss_rate::total 0.199304 # miss rate for ReadReq accesses 77011860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::cpu.inst 0.199304 # miss rate for demand accesses 77111860Sandreas.hansson@arm.comsystem.cpu.icache.demand_miss_rate::total 0.199304 # miss rate for demand accesses 77211860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::cpu.inst 0.199304 # miss rate for overall accesses 77311860Sandreas.hansson@arm.comsystem.cpu.icache.overall_miss_rate::total 0.199304 # miss rate for overall accesses 77411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 77469.432314 # average ReadReq miss latency 77511860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_miss_latency::total 77469.432314 # average ReadReq miss latency 77611860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::cpu.inst 77469.432314 # average overall miss latency 77711860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_miss_latency::total 77469.432314 # average overall miss latency 77811860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::cpu.inst 77469.432314 # average overall miss latency 77911860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_miss_latency::total 77469.432314 # average overall miss latency 78011860Sandreas.hansson@arm.comsystem.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 7818428SN/Asystem.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 78211860Sandreas.hansson@arm.comsystem.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 7838428SN/Asystem.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 78411860Sandreas.hansson@arm.comsystem.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 7858983Snate@binkert.orgsystem.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 78611860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::cpu.inst 146 # number of ReadReq MSHR hits 78711860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_hits::total 146 # number of ReadReq MSHR hits 78811860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::cpu.inst 146 # number of demand (read+write) MSHR hits 78911860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_hits::total 146 # number of demand (read+write) MSHR hits 79011860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::cpu.inst 146 # number of overall MSHR hits 79111860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_hits::total 146 # number of overall MSHR hits 79211860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::cpu.inst 312 # number of ReadReq MSHR misses 79311860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_misses::total 312 # number of ReadReq MSHR misses 79411860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::cpu.inst 312 # number of demand (read+write) MSHR misses 79511860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_misses::total 312 # number of demand (read+write) MSHR misses 79611860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::cpu.inst 312 # number of overall MSHR misses 79711860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_misses::total 312 # number of overall MSHR misses 79811860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26195000 # number of ReadReq MSHR miss cycles 79911860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_latency::total 26195000 # number of ReadReq MSHR miss cycles 80011860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::cpu.inst 26195000 # number of demand (read+write) MSHR miss cycles 80111860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_latency::total 26195000 # number of demand (read+write) MSHR miss cycles 80211860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::cpu.inst 26195000 # number of overall MSHR miss cycles 80311860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_latency::total 26195000 # number of overall MSHR miss cycles 80411860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.135770 # mshr miss rate for ReadReq accesses 80511860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_mshr_miss_rate::total 0.135770 # mshr miss rate for ReadReq accesses 80611860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.135770 # mshr miss rate for demand accesses 80711860Sandreas.hansson@arm.comsystem.cpu.icache.demand_mshr_miss_rate::total 0.135770 # mshr miss rate for demand accesses 80811860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.135770 # mshr miss rate for overall accesses 80911860Sandreas.hansson@arm.comsystem.cpu.icache.overall_mshr_miss_rate::total 0.135770 # mshr miss rate for overall accesses 81011860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 83958.333333 # average ReadReq mshr miss latency 81111860Sandreas.hansson@arm.comsystem.cpu.icache.ReadReq_avg_mshr_miss_latency::total 83958.333333 # average ReadReq mshr miss latency 81211860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 83958.333333 # average overall mshr miss latency 81311860Sandreas.hansson@arm.comsystem.cpu.icache.demand_avg_mshr_miss_latency::total 83958.333333 # average overall mshr miss latency 81411860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 83958.333333 # average overall mshr miss latency 81511860Sandreas.hansson@arm.comsystem.cpu.icache.overall_avg_mshr_miss_latency::total 83958.333333 # average overall mshr miss latency 81611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 8179838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.replacements 0 # number of replacements 81811860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tagsinuse 270.308724 # Cycle average of tags in use 8199838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.total_refs 1 # Total number of references to valid blocks. 82011860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.sampled_refs 484 # Sample count of references to valid blocks. 82111860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.avg_refs 0.002066 # Average number of references to valid blocks. 8229838Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 82311860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.inst 160.032476 # Average occupied blocks per requestor 82411860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_blocks::cpu.data 110.276248 # Average occupied blocks per requestor 82511860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.inst 0.004884 # Average percentage of cache occupancy 82611680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.occ_percent::cpu.data 0.003365 # Average percentage of cache occupancy 82711860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_percent::total 0.008249 # Average percentage of cache occupancy 82811860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_blocks::1024 484 # Occupied blocks per task id 82911680SCurtis.Dunham@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::0 167 # Occupied blocks per task id 83011860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.age_task_id_blocks_1024::1 317 # Occupied blocks per task id 83111860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.occ_task_id_percent::1024 0.014771 # Percentage of cache occupancy per task id 83211860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.tag_accesses 4364 # Number of tag accesses 83311860Sandreas.hansson@arm.comsystem.cpu.l2cache.tags.data_accesses 4364 # Number of data accesses 83411680SCurtis.Dunham@arm.comsystem.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 83510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::cpu.inst 1 # number of ReadCleanReq hits 83610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_hits::total 1 # number of ReadCleanReq hits 8378835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::cpu.inst 1 # number of demand (read+write) hits 8388835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_hits::total 1 # number of demand (read+write) hits 8398835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::cpu.inst 1 # number of overall hits 8408835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_hits::total 1 # number of overall hits 84110242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::cpu.data 72 # number of ReadExReq misses 84210242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_misses::total 72 # number of ReadExReq misses 84311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::cpu.inst 311 # number of ReadCleanReq misses 84411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_misses::total 311 # number of ReadCleanReq misses 84511390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_misses::cpu.data 101 # number of ReadSharedReq misses 84611390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_misses::total 101 # number of ReadSharedReq misses 84711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::cpu.inst 311 # number of demand (read+write) misses 84811390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_misses::cpu.data 173 # number of demand (read+write) misses 84911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_misses::total 484 # number of demand (read+write) misses 85011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::cpu.inst 311 # number of overall misses 85111390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_misses::cpu.data 173 # number of overall misses 85211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_misses::total 484 # number of overall misses 85311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::cpu.data 6919000 # number of ReadExReq miss cycles 85411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_miss_latency::total 6919000 # number of ReadExReq miss cycles 85511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25713500 # number of ReadCleanReq miss cycles 85611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_latency::total 25713500 # number of ReadCleanReq miss cycles 85711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 9242500 # number of ReadSharedReq miss cycles 85811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_latency::total 9242500 # number of ReadSharedReq miss cycles 85911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.inst 25713500 # number of demand (read+write) miss cycles 86011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::cpu.data 16161500 # number of demand (read+write) miss cycles 86111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_latency::total 41875000 # number of demand (read+write) miss cycles 86211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.inst 25713500 # number of overall miss cycles 86311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::cpu.data 16161500 # number of overall miss cycles 86411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_latency::total 41875000 # number of overall miss cycles 86510242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::cpu.data 72 # number of ReadExReq accesses(hits+misses) 86610242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_accesses::total 72 # number of ReadExReq accesses(hits+misses) 86711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 312 # number of ReadCleanReq accesses(hits+misses) 86811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_accesses::total 312 # number of ReadCleanReq accesses(hits+misses) 86911390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_accesses::cpu.data 101 # number of ReadSharedReq accesses(hits+misses) 87011390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_accesses::total 101 # number of ReadSharedReq accesses(hits+misses) 87111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::cpu.inst 312 # number of demand (read+write) accesses 87211390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_accesses::cpu.data 173 # number of demand (read+write) accesses 87311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_accesses::total 485 # number of demand (read+write) accesses 87411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::cpu.inst 312 # number of overall (read+write) accesses 87511390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_accesses::cpu.data 173 # number of overall (read+write) accesses 87611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_accesses::total 485 # number of overall (read+write) accesses 8778835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 8789055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 87911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.996795 # miss rate for ReadCleanReq accesses 88011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_miss_rate::total 0.996795 # miss rate for ReadCleanReq accesses 88110892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 88210892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 88311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::cpu.inst 0.996795 # miss rate for demand accesses 8848835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 88511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_miss_rate::total 0.997938 # miss rate for demand accesses 88611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::cpu.inst 0.996795 # miss rate for overall accesses 8878835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 88811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_miss_rate::total 0.997938 # miss rate for overall accesses 88911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96097.222222 # average ReadExReq miss latency 89011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_miss_latency::total 96097.222222 # average ReadExReq miss latency 89111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 82680.064309 # average ReadCleanReq miss latency 89211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 82680.064309 # average ReadCleanReq miss latency 89311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 91509.900990 # average ReadSharedReq miss latency 89411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 91509.900990 # average ReadSharedReq miss latency 89511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.inst 82680.064309 # average overall miss latency 89611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::cpu.data 93419.075145 # average overall miss latency 89711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_miss_latency::total 86518.595041 # average overall miss latency 89811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.inst 82680.064309 # average overall miss latency 89911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::cpu.data 93419.075145 # average overall miss latency 90011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_miss_latency::total 86518.595041 # average overall miss latency 9018428SN/Asystem.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 9028428SN/Asystem.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 9038428SN/Asystem.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 9048428SN/Asystem.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 9058983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 9068983Snate@binkert.orgsystem.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 90710242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 72 # number of ReadExReq MSHR misses 90810242Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadExReq_mshr_misses::total 72 # number of ReadExReq MSHR misses 90911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 311 # number of ReadCleanReq MSHR misses 91011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_misses::total 311 # number of ReadCleanReq MSHR misses 91111390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 101 # number of ReadSharedReq MSHR misses 91211390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.ReadSharedReq_mshr_misses::total 101 # number of ReadSharedReq MSHR misses 91311860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::cpu.inst 311 # number of demand (read+write) MSHR misses 91411390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.demand_mshr_misses::cpu.data 173 # number of demand (read+write) MSHR misses 91511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_misses::total 484 # number of demand (read+write) MSHR misses 91611860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::cpu.inst 311 # number of overall MSHR misses 91711390Ssteve.reinhardt@amd.comsystem.cpu.l2cache.overall_mshr_misses::cpu.data 173 # number of overall MSHR misses 91811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_misses::total 484 # number of overall MSHR misses 91911860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 6199000 # number of ReadExReq MSHR miss cycles 92011860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_mshr_miss_latency::total 6199000 # number of ReadExReq MSHR miss cycles 92111860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22603500 # number of ReadCleanReq MSHR miss cycles 92211860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22603500 # number of ReadCleanReq MSHR miss cycles 92311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 8232500 # number of ReadSharedReq MSHR miss cycles 92411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 8232500 # number of ReadSharedReq MSHR miss cycles 92511860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22603500 # number of demand (read+write) MSHR miss cycles 92611860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::cpu.data 14431500 # number of demand (read+write) MSHR miss cycles 92711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_latency::total 37035000 # number of demand (read+write) MSHR miss cycles 92811860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22603500 # number of overall MSHR miss cycles 92911860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::cpu.data 14431500 # number of overall MSHR miss cycles 93011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_latency::total 37035000 # number of overall MSHR miss cycles 9318835SAli.Saidi@ARM.comsystem.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 9329055Ssaidi@eecs.umich.edusystem.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 93311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for ReadCleanReq accesses 93411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.996795 # mshr miss rate for ReadCleanReq accesses 93510892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 93610892Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 93711860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for demand accesses 9388835SAli.Saidi@ARM.comsystem.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 93911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_mshr_miss_rate::total 0.997938 # mshr miss rate for demand accesses 94011860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.996795 # mshr miss rate for overall accesses 9418835SAli.Saidi@ARM.comsystem.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 94211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_mshr_miss_rate::total 0.997938 # mshr miss rate for overall accesses 94311860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86097.222222 # average ReadExReq mshr miss latency 94411860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86097.222222 # average ReadExReq mshr miss latency 94511860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 72680.064309 # average ReadCleanReq mshr miss latency 94611860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 72680.064309 # average ReadCleanReq mshr miss latency 94711860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 81509.900990 # average ReadSharedReq mshr miss latency 94811860Sandreas.hansson@arm.comsystem.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 81509.900990 # average ReadSharedReq mshr miss latency 94911860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 72680.064309 # average overall mshr miss latency 95011860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 83419.075145 # average overall mshr miss latency 95111860Sandreas.hansson@arm.comsystem.cpu.l2cache.demand_avg_mshr_miss_latency::total 76518.595041 # average overall mshr miss latency 95211860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 72680.064309 # average overall mshr miss latency 95311860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 83419.075145 # average overall mshr miss latency 95411860Sandreas.hansson@arm.comsystem.cpu.l2cache.overall_avg_mshr_miss_latency::total 76518.595041 # average overall mshr miss latency 95511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_requests 485 # Total number of requests made to the snoop filter. 95611138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_requests 1 # Number of requests hitting in the snoop filter with a single holder of the requested data. 95711138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 95811138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 95911138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 96011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 96111680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 96211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadResp 413 # Transaction distribution 96310628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExReq 72 # Transaction distribution 96410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadExResp 72 # Transaction distribution 96511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.trans_dist::ReadCleanReq 312 # Transaction distribution 96611390Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.trans_dist::ReadSharedReq 101 # Transaction distribution 96711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 624 # Packet count per connected master and slave (bytes) 96811390Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 346 # Packet count per connected master and slave (bytes) 96911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_count::total 970 # Packet count per connected master and slave (bytes) 97011860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19968 # Cumulative packet size per connected master and slave (bytes) 97111390Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 11072 # Cumulative packet size per connected master and slave (bytes) 97211860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.pkt_size::total 31040 # Cumulative packet size per connected master and slave (bytes) 97310628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoops 0 # Total snoops (count) 97411570SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.snoopTraffic 0 # Total snoop traffic (bytes) 97511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::samples 485 # Request fanout histogram 97611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::mean 0.002062 # Request fanout histogram 97711860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::stdev 0.045408 # Request fanout histogram 97810628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 97911860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::0 484 99.79% 99.79% # Request fanout histogram 98011138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::1 1 0.21% 100.00% # Request fanout histogram 98110628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 98210628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 98311138Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 98410628Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 98511860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.snoop_fanout::total 485 # Request fanout histogram 98611860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.reqLayer0.occupancy 242500 # Layer occupancy (ticks) 98711680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) 98811860Sandreas.hansson@arm.comsystem.cpu.toL2Bus.respLayer0.occupancy 468000 # Layer occupancy (ticks) 98911680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) 99011390Ssteve.reinhardt@amd.comsystem.cpu.toL2Bus.respLayer1.occupancy 259500 # Layer occupancy (ticks) 99111680SCurtis.Dunham@arm.comsystem.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) 99211860Sandreas.hansson@arm.comsystem.membus.snoop_filter.tot_requests 484 # Total number of requests made to the snoop filter. 99311606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 99411606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 99511606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 99611606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 99711606Sandreas.sandberg@arm.comsystem.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 99811680SCurtis.Dunham@arm.comsystem.membus.pwrStateResidencyTicks::UNDEFINED 23776000 # Cumulative time (in ticks) in various power states 99911860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadResp 412 # Transaction distribution 100010628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExReq 72 # Transaction distribution 100110628Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadExResp 72 # Transaction distribution 100211860Sandreas.hansson@arm.comsystem.membus.trans_dist::ReadSharedReq 412 # Transaction distribution 100311860Sandreas.hansson@arm.comsystem.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 968 # Packet count per connected master and slave (bytes) 100411860Sandreas.hansson@arm.comsystem.membus.pkt_count::total 968 # Packet count per connected master and slave (bytes) 100511860Sandreas.hansson@arm.comsystem.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30976 # Cumulative packet size per connected master and slave (bytes) 100611860Sandreas.hansson@arm.comsystem.membus.pkt_size::total 30976 # Cumulative packet size per connected master and slave (bytes) 100710628Sandreas.hansson@arm.comsystem.membus.snoops 0 # Total snoops (count) 100811570SCurtis.Dunham@arm.comsystem.membus.snoopTraffic 0 # Total snoop traffic (bytes) 100911860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::samples 484 # Request fanout histogram 101010628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::mean 0 # Request fanout histogram 101110628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::stdev 0 # Request fanout histogram 101210628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 101311860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::0 484 100.00% 100.00% # Request fanout histogram 101410628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 101510628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 101610628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::min_value 0 # Request fanout histogram 101710628Sandreas.hansson@arm.comsystem.membus.snoop_fanout::max_value 0 # Request fanout histogram 101811860Sandreas.hansson@arm.comsystem.membus.snoop_fanout::total 484 # Request fanout histogram 101911860Sandreas.hansson@arm.comsystem.membus.reqLayer0.occupancy 593000 # Layer occupancy (ticks) 102011680SCurtis.Dunham@arm.comsystem.membus.reqLayer0.utilization 2.5 # Layer utilization (%) 102111860Sandreas.hansson@arm.comsystem.membus.respLayer1.occupancy 2566000 # Layer occupancy (ticks) 102211680SCurtis.Dunham@arm.comsystem.membus.respLayer1.utilization 10.8 # Layer utilization (%) 10233096SN/A 10243096SN/A---------- End Simulation Statistics ---------- 1025