/gem5/src/arch/arm/ |
H A D | interrupts.cc | 58 SCR scr; local 65 scr = tc->readMiscReg(MISCREG_SCR); 67 scr = tc->readMiscReg(MISCREG_SCR_EL3); 74 scr_routing_bit = scr.fiq; 75 scr_fwaw_bit = scr.fw; 80 scr_routing_bit = scr.irq; 86 scr_routing_bit = scr.ea; 87 scr_fwaw_bit = scr.aw; 122 if (!scr.rw) {
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H A D | isa.cc | 456 SCR scr = 0; 497 scr = readMiscRegNoEffect(MISCREG_SCR); 499 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 523 scr = readMiscRegNoEffect(MISCREG_SCR); 524 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 780 SCR scr; 840 scr = readMiscRegNoEffect(MISCREG_SCR); 842 if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 1057 scr = readMiscRegNoEffect(MISCREG_SCR); 1060 if (haveSecurity && !highestELIs64 && !scr [all...] |
H A D | faults.cc | 499 SCR scr = tc->readMiscReg(MISCREG_SCR); local 518 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); local 519 if (scr.ns) { 520 scr.ns = 0; 521 tc->setMiscRegNoEffect(MISCREG_SCR, scr); 533 if (!scr.ea) {cpsr.a = 1;} 534 if (!scr.fiq) {cpsr.f = 1;} 535 if (!scr.irq) {cpsr.i = 1;} 798 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); local 803 toHyp = scr 870 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); local 1012 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); local 1180 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); local 1270 SCR scr = 0; local 1284 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); local 1331 SCR scr = 0; local 1345 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); local 1434 SCR scr = 0; local 1447 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); local 1460 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); local 1473 SCR scr = 0; local 1486 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); local 1499 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); local 1511 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR); local 1534 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); local 1561 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); local 1571 SCR scr = tc->readMiscRegNoEffect(MISCREG_SCR_EL3); local [all...] |
H A D | utility.cc | 198 SCR scr = inAArch64(tc) ? tc->readMiscReg(MISCREG_SCR_EL3) : local 201 scr, tc->readMiscReg(MISCREG_CPSR)); 207 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); local 208 return ArmSystem::haveEL(tc, EL3) && scr.ns == 0; 329 SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); local 330 bool aarch32_below_el3 = (have_el3 && scr.rw == 0); 474 const SCR scr = tc->readMiscReg(MISCREG_SCR); local 479 if (!inSecureState(scr, cpsr) && (cpsr.mode != MODE_HYP)) { 602 mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, argument 613 if (!inSecureState(scr, cps 652 mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr, HCR hcr, uint32_t iss) argument 700 decodeMrsMsrBankedReg(uint8_t sysM, bool r, bool &isIntReg, int ®Idx, CPSR cpsr, SCR scr, NSACR nsacr, bool checkSecurity) argument [all...] |
H A D | utility.hh | 237 inSecureState(SCR scr, CPSR cpsr) argument 249 return !scr.ns; 324 mcrMrc14TrapToHyp(const MiscRegIndex miscReg, HCR hcr, CPSR cpsr, SCR scr, 327 mcrrMrrc15TrapToHyp(const MiscRegIndex miscReg, CPSR cpsr, SCR scr, HSTR hstr, 355 CPSR cpsr, SCR scr, NSACR nsacr,
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H A D | interrupts.hh | 176 checkWfiWake(HCR hcr, CPSR cpsr, SCR scr) const 186 virtWake &= (cpsr.mode != MODE_HYP) && !inSecureState(scr, cpsr); 191 getISR(HCR hcr, CPSR cpsr, SCR scr) argument 196 useHcrMux = (cpsr.mode != MODE_HYP) && !inSecureState(scr, cpsr);
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H A D | miscregs.hh | 1124 "scr", 1908 std::tuple<bool, bool> canReadCoprocReg(MiscRegIndex reg, SCR scr, 1924 std::tuple<bool, bool> canWriteCoprocReg(MiscRegIndex reg, SCR scr, 1928 bool canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, 1932 bool canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, 1935 // Uses just the scr.ns bit to pre flatten the misc regs. This is useful
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H A D | tlb.cc | 758 (isSecure && te->ns && scr.sif))) { 762 ap, is_priv, is_write, te->ns, scr.sif,sctlr.afe); 993 ap, is_priv, is_write, te->ns, scr.sif, sctlr.afe); 1064 DPRINTF(TLB, "translateFs addr %#x, mode %d, st2 %d, scr %#x sctlr %#x " 1066 scr, sctlr, flags, tranType); 1342 scr = tc->readMiscReg(MISCREG_SCR_EL3); 1372 scr = tc->readMiscReg(MISCREG_SCR);
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H A D | pmu.cc | 500 const SCR scr(pmu.isa->readMiscRegNoEffect(MISCREG_SCR)); 503 const bool secure(inSecureState(scr, cpsr));
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H A D | tlb.hh | 415 SCR scr; member in class:ArmISA::TLB
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H A D | miscregs.cc | 989 canReadCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr) argument 991 bool secure = !scr.ns; 1025 canWriteCoprocReg(MiscRegIndex reg, SCR scr, CPSR cpsr) argument 1027 bool secure = !scr.ns; 1063 SCR scr = tc->readMiscReg(MISCREG_SCR); local 1064 return snsBankedIndex(reg, tc, scr.ns); 1081 SCR scr = tc->readMiscReg(MISCREG_SCR); local 1082 return tc->getIsaPtr()->snsBankedIndex64(reg, scr.ns); 1118 canReadAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) argument 1136 bool secure = ArmSystem::haveSecurity(tc) && !scr 1156 canWriteAArch64SysReg(MiscRegIndex reg, SCR scr, CPSR cpsr, ThreadContext *tc) argument [all...] |
H A D | table_walker.hh | 729 /** Cached copy of the scr as it existed when translation began */ 730 SCR scr; member in class:ArmISA::TableWalker::LongDescriptor::WalkerState
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H A D | table_walker.cc | 134 sctlr(0), scr(0), cpsr(0), tcr(0),
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/gem5/src/arch/arm/insts/ |
H A D | static_inst.hh | 203 cpsrWriteByInstr(CPSR cpsr, uint32_t val, SCR scr, NSACR nsacr, argument 209 bool isSecure = inSecureState(scr, cpsr) || !haveSecurity; 222 unsigned lowIdx = (privileged && (isSecure || scr.aw || haveVirt)) 230 (isSecure || scr.fw || haveVirt) ) { 248 if (scr.ns == '0' && newMode == MODE_HYP) 446 Fault trapWFx(ThreadContext *tc, CPSR cpsr, SCR scr, bool isWfe) const;
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H A D | static_inst.cc | 782 SCR scr = ((SCR)tc->readMiscReg(MISCREG_SCR_EL3)); 792 trap = isWfe? scr.twe : scr.twi; 875 CPSR cpsr, SCR scr, 886 ArmSystem::haveEL(tc, EL2) && !inSecureState(scr, cpsr) && 1060 SCR scr = ((SCR)tc->readMiscReg(MISCREG_SCR_EL3)); 1068 if (target_el == EL1 && ArmSystem::haveEL(tc, EL2) && scr.ns && hcr.tge) 1071 if (target_el == EL2 && ArmSystem::haveEL(tc, EL3) && !scr.ns)
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H A D | misc64.cc | 148 const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3); local 154 if (!inSecureState(scr, cpsr) && (el != EL2)) {
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/gem5/util/cpt_upgraders/ |
H A D | armv8.py | 180 scr = int(mr_new[115]) 181 scr = scr | 0x1 182 mr_new[115] = str(scr)
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/gem5/src/dev/arm/ |
H A D | gic_v3_cpu_interface.cc | 2332 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR); local 2333 return ArmISA::inSecureState(scr, cpsr); 2384 SCR scr = isa->readMiscRegNoEffect(MISCREG_SCR_EL3); local 2385 return haveEL(EL3) && scr.ns == 0;
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