Searched refs:tcBase (Results 1 - 17 of 17) sorted by relevance

/gem5/src/cpu/
H A Dexec_context.hh314 virtual ThreadContext *tcBase() = 0;
H A Dbase_dyn_inst.hh922 ThreadContext *tcBase() { return thread->getTC(); } function in class:BaseDynInst
/gem5/src/arch/arm/insts/
H A Dmisc.cc342 bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), iss);
367 bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), iss);
H A Dmisc64.cc376 auto tc = xc->tcBase();
H A Dstatic_inst.cc632 const auto tc = xc->tcBase();
/gem5/src/arch/mips/
H A Dmt.hh107 return readRegOtherThread(xc->tcBase(), reg, tid);
114 setRegOtherThread(xc->tcBase(), reg, val, tid);
/gem5/src/cpu/checker/
H A Dcpu_impl.hh555 if (inst->tcBase()->readMiscRegNoEffect(misc_reg_idx) !=
560 inst->tcBase()->readMiscRegNoEffect(misc_reg_idx),
585 thread->copyArchRegs(unverifiedInst->tcBase());
H A Dcpu.hh598 ThreadContext *tcBase() override { return tc; }
/gem5/src/cpu/o3/
H A Dcpu.cc781 src_tc = tcBase(tid);
1179 return this->isa[tid]->readMiscReg(misc_reg, tcBase(tid));
1194 this->isa[tid]->setMiscReg(misc_reg, val, tcBase(tid));
1770 assert(tcBase(tid)->status() != ThreadContext::Halted);
1827 tcBase(thread_id)->setStatus(ThreadContext::Halted);
H A Dcommit_impl.hh739 if (!cpu->checkInterrupts(cpu->tcBase(0))) {
819 if (cpu->checkInterrupts(cpu->tcBase(0)))
1133 onInstBoundary && cpu->checkInterrupts(cpu->tcBase(0)))
H A Dcpu.hh678 tcBase(ThreadID tid) function in class:FullO3CPU
H A Drename_impl.hh1068 ThreadContext *tc = inst->tcBase();
1135 ThreadContext *tc = inst->tcBase();
H A Dlsq_unit.hh667 ThreadContext *thread = cpu->tcBase(lsqID);
H A Dlsq_unit_impl.hh821 ThreadContext *thread = cpu->tcBase(lsqID);
H A Dfetch_impl.hh1131 cpu->getTracer()->getInstRecord(curTick(), cpu->tcBase(tid),
/gem5/src/cpu/minor/
H A Dexec_context.hh398 ThreadContext *tcBase() override { return thread.getTC(); }
/gem5/src/cpu/simple/
H A Dexec_context.hh509 ThreadContext *tcBase() override { return thread->getTC(); }

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