Searched refs:pio (Results 1 - 22 of 22) sorted by relevance

/gem5/src/dev/alpha/
H A DTsunami.py109 self.cchip.pio = bus.master
110 self.pchip.pio = bus.master
111 self.fake_sm_chip.pio = bus.master
112 self.fake_uart1.pio = bus.master
113 self.fake_uart2.pio = bus.master
114 self.fake_uart3.pio = bus.master
115 self.fake_uart4.pio = bus.master
116 self.fake_ppc.pio = bus.master
117 self.fake_OROM.pio = bus.master
118 self.fake_pnp_addr.pio
[all...]
/gem5/src/dev/x86/
H A DPc.py80 self.i_dont_exist1.pio = bus.master
81 self.i_dont_exist2.pio = bus.master
82 self.behind_pci.pio = bus.master
83 self.com_1.pio = bus.master
84 self.fake_com_2.pio = bus.master
85 self.fake_com_3.pio = bus.master
86 self.fake_com_4.pio = bus.master
87 self.fake_floppy.pio = bus.master
88 self.pci_host.pio = bus.default
H A DSouthBridge.py102 self.cmos.pio = bus.master
103 self.dma1.pio = bus.master
104 self.ide.pio = bus.master
107 self.keyboard.pio = bus.master
108 self.pic1.pio = bus.master
109 self.pic2.pio = bus.master
110 self.pit.pio = bus.master
111 self.speaker.pio = bus.master
112 self.io_apic.pio = bus.master
/gem5/src/dev/sparc/
H A DT1000.py117 self.iob.pio = bus.master
118 self.htod.pio = bus.master
127 self.fake_clk.pio = bus.master
128 self.fake_membnks.pio = bus.master
129 self.fake_l2_1.pio = bus.master
130 self.fake_l2_2.pio = bus.master
131 self.fake_l2_3.pio = bus.master
132 self.fake_l2_4.pio = bus.master
133 self.fake_l2esr_1.pio = bus.master
134 self.fake_l2esr_2.pio
[all...]
/gem5/src/dev/mips/
H A DMalta.py64 self.cchip.pio = bus.master
65 self.io.pio = bus.master
66 self.uart.pio = bus.master
/gem5/src/dev/arm/
H A DRealView.py554 if hasattr(device, "pio"):
555 device.pio = bus.master
669 self.gic.pio = bus.master
670 self.l2x0_fake.pio = bus.master
671 self.a9scu.pio = bus.master
672 self.global_timer.pio = bus.master
673 self.local_cpu_timer.pio = bus.master
694 self.uart.pio = bus.master
695 self.realview_io.pio = bus.master
696 self.pci_host.pio
[all...]
/gem5/configs/learning_gem5/part1/
H A Dsimple.py77 system.cpu.interrupts[0].pio = system.membus.master
H A Dtwo_level.py129 system.cpu.interrupts[0].pio = system.membus.master
/gem5/configs/learning_gem5/part2/
H A Dsimple_cache.py76 system.cpu.interrupts[0].pio = system.membus.master
H A Dsimple_memobj.py74 system.cpu.interrupts[0].pio = system.membus.master
/gem5/src/dev/
H A DDevice.py52 pio = SlavePort("Programmed I/O port") variable in class:PioDevice
/gem5/tests/configs/
H A Dpc-simple-timing-ruby.py88 cpu.interrupts[0].pio = system.ruby._cpu_ports[i].master
H A Dgpu-ruby.py330 dispatcher.pio = system.piobus.master
/gem5/tests/gem5/cpu_tests/
H A Drun.py154 system.cpu.interrupts[0].pio = system.membus.master
/gem5/configs/common/
H A DFSConfig.py72 default = Self.badaddr_responder.pio
100 self.tsunami.ide.pio = self.iobus.master
102 self.tsunami.ethernet.pio = self.iobus.master
176 self.disk0.pio = self.iobus.master
422 self.malta.ide.pio = self.iobus.master
424 self.malta.ethernet.pio = self.iobus.master
H A DHMC.py306 system.membus.default = Self.badaddr_responder.pio
/gem5/configs/example/
H A Dapu_se.py464 system.cpu[i].interrupts[0].pio = system.piobus.master
506 system.cpu[cp_idx].interrupts[0].pio = system.piobus.master
512 dispatcher.pio = system.piobus.master
H A Dse.py267 system.cpu[i].interrupts[0].pio = ruby_port.master
H A Dfs.py179 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
/gem5/configs/learning_gem5/part3/
H A Dmsi_caches.py114 cpu.interrupts[0].pio = self.sequencers[i].master
H A Druby_caches_MI_example.py112 cpu.interrupts[0].pio = self.sequencers[i].master
/gem5/configs/example/arm/
H A Ddevices.py109 default = Self.badaddr_responder.pio

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