| /gem5/util/ |
| H A D | o3-pipeview.py | 53 insts = { variable
72 global insts
74 insts['sn_start'] = start_sn
75 insts['sn_stop'] = stop_sn
76 insts['tick_start'] = start_tick
77 insts['tick_stop'] = stop_tick
78 insts['tick_drift'] = insts['tick_drift'] * cycle_time
79 insts['only_committed'] = committed_only
132 if ((stop_tick > 0 and int(fields[2]) > stop_tick+insts['tick_drif
[all...] |
| /gem5/src/cpu/o3/ |
| H A D | comm.hh | 62 DynInstPtr insts[Impl::MaxWidth]; member in struct:DefaultFetchDefaultDecode
75 DynInstPtr insts[Impl::MaxWidth]; member in struct:DefaultDecodeDefaultRename
85 DynInstPtr insts[Impl::MaxWidth]; member in struct:DefaultRenameDefaultIEW
95 DynInstPtr insts[Impl::MaxWidth]; member in struct:DefaultIEWDefaultCommit
113 DynInstPtr insts[Impl::MaxWidth]; member in struct:IssueStruct
|
| H A D | decode_impl.hh | 217 assert(insts[tid].empty());
227 if (!insts[tid].empty() || !skidBuffer[tid].empty() ||
336 if (fromFetch->insts[i]->threadNumber == tid &&
337 fromFetch->insts[i]->seqNum > squash_seq_num) {
338 fromFetch->insts[i]->setSquashed();
343 // insts in them.
344 while (!insts[tid].empty()) {
345 insts[tid].pop();
385 if (fromFetch->insts[i]->threadNumber == tid) {
386 fromFetch->insts[
[all...] |
| H A D | iew_impl.hh | 232 .desc("number of swp insts executed")
238 .desc("number of nop insts executed")
244 .desc("number of memory reference insts executed")
269 .desc("cumulative count of insts sent to commit")
275 .desc("cumulative count of insts written-back")
299 .desc("insts written-back per cycle")
401 if (!insts[tid].empty()) {
528 "insts, PC: %s [sn:%llu].\n", tid, inst->pcState(), inst->seqNum);
635 while ((*iewQueue)[wbCycle].insts[wbNumInst]) {
646 (*iewQueue)[wbCycle].insts[wbNumIns
[all...] |
| H A D | rename_impl.hh | 174 .desc("count of serializing insts renamed")
179 .desc("count of temporary serializing insts renamed")
184 .desc("count of insts added to the skid buffer")
347 !insts[tid].empty() ||
367 assert(insts[tid].empty());
409 if (fromDecode->insts[i]->threadNumber == tid &&
410 fromDecode->insts[i]->seqNum > squash_seq_num) {
411 fromDecode->insts[i]->setSquashed();
418 // insts in them.
419 insts[ti
[all...] |
| H A D | decode.hh | 243 std::queue<DynInstPtr> insts[Impl::MaxThreads]; member in class:DefaultDecode
|
| H A D | commit_impl.hh | 155 .desc("The number of squashed insts skipped by commit")
172 .desc("Number of insts commited each cycle")
683 " insts this cycle.\n", tid);
721 DPRINTF(Commit, "[tid:%i] ROB has %d insts & %d free entries.\n",
1348 const DynInstPtr &inst = fromRename->insts[inst_num];
1376 // Grab completed insts out of the IEW instruction queue, and mark
1379 assert(fromIEW->insts[inst_num]);
1380 if (!fromIEW->insts[inst_num]->isSquashed()) {
1383 fromIEW->insts[inst_num]->threadNumber,
1384 fromIEW->insts[inst_nu
[all...] |
| H A D | iew.hh | 337 std::queue<DynInstPtr> insts[Impl::MaxThreads]; member in class:DefaultIEW
375 /** Records if the queues have been changed (inserted or issued insts),
|
| H A D | rename.hh | 88 // A deque is used to queue the instructions. Barrier insts must
356 InstQueue insts[Impl::MaxThreads]; member in class:DefaultRename
|
| H A D | fetch_impl.hh | 970 toDecode->insts[toDecode->size++] = inst;
1148 //toDecode->insts[toDecode->size++] = instruction;
|
| /gem5/src/cpu/minor/ |
| H A D | pipe_data.cc | 243 insts[i] = src.insts[i];
251 return numInsts == 0 || insts[0]->isBubble();
258 insts[i] = MinorDynInst::bubble();
280 insts[i]->reportData(os);
|
| H A D | pipe_data.hh | 258 /** Array of carried insts, ref counted */
259 MinorDynInstPtr insts[MAX_FORWARD_INSTS]; member in class:Minor::ForwardInstData
261 /** The number of insts slots that can be expected to be valid insts */
|
| H A D | decode.cc | 76 name + ".inputBuffer" + std::to_string(tid), "insts",
84 /* Get insts from the inputBuffer to work with */
151 MinorDynInstPtr inst = insts_in->insts[decode_info.inputIndex];
244 insts_out.insts[output_index] = output_inst;
268 * assert(insts_out.insts[output_index]->isBubble());
347 MINORTRACE("insts=%s\n", data.str());
|
| H A D | execute.cc | 176 name_ + ".inputBuffer" + tid_str, "insts",
185 name_ + ".inFlightInsts" + tid_str, "insts", total_slots);
189 name_ + ".inFUMemInsts" + tid_str, "insts", total_slots);
561 /* Number of insts issues this cycle to check for issueLimit */
572 MinorDynInstPtr inst = insts_in->insts[thread.inputIndex];
618 /* Issue free insts. to a fake numbered FU */
1059 /* Number of insts committed this cycle to check against commitLimit */
1080 DPRINTF(MinorInterrupt, "Committing tail of insts before"
1092 * Start by considering the the head of the in flight insts queue */
1191 /* Try and commit FU-less insts */
1647 std::ostringstream insts; local
[all...] |
| H A D | fetch2.cc | 489 insts_out.insts[output_index] = dyn_inst;
655 MINORTRACE("inputIndex=%d havePC=%d predictionSeqNum=%d insts=%s\n",
|
| /gem5/src/gpu-compute/ |
| H A D | hsa_code.hh | 78 std::vector<TheGpuISA::RawMachInst>* insts() { return &_insts; } function in class:HsaCode
|
| H A D | kernel_cfg.cc | 58 ControlFlowInfo::ControlFlowInfo(const std::vector<GPUStaticInst*>& insts) : argument
59 instructions(insts)
|
| H A D | cl_driver.cc | 225 bufp[buf_idx] = k->insts()->at(j);
|
| /gem5/src/cpu/simple/probes/ |
| H A D | simpoint.hh | 107 /** Num of static insts in BB */
108 uint64_t insts; member in struct:SimPoint::BBInfo
|
| H A D | simpoint.cc | 99 // add a new unique id, record num of insts and insert into bbMap.
102 info.insts = currentBBVInstCount;
107 // number of insts in basic block.
|
| /gem5/util/minorview/ |
| H A D | model.py | 398 'insts': Id,
555 self.insts = {}
577 if inst.id.execSeqNum != 0 and macroop_key not in self.insts:
578 self.insts[macroop_key] = inst
580 self.insts[full_key] = inst
587 if full_key in self.insts:
588 return self.insts[full_key]
589 elif macroop_key in self.insts:
590 return self.insts[macroop_key]
|
| H A D | view.py | 363 insts = event.find_ided_objects(self.model, self.blob.picChar,
370 # Get formatted data from the insts to format into a table
371 lines = list(inst.table_line() for inst in insts)
399 size = Point(total_width, text_size * len(insts))
413 for i in xrange(0, len(insts)):
415 inst = insts[i]
|
| /gem5/src/cpu/ |
| H A D | base.hh | 461 * @param insts Number of instructions into the future.
464 void scheduleInstStop(ThreadID tid, Counter insts, const char *cause);
|
| H A D | base.cc | 110 DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
115 cprintf("%lli: %s progress event, total committed:%i, progress insts "
751 BaseCPU::scheduleInstStop(ThreadID tid, Counter insts, const char *cause)
756 comInstEventQueue[tid]->schedule(event, now + insts);
|