| /gem5/src/mem/ruby/system/ |
| H A D | GPUCoalescer.py | 52 dcache = Param.RubyCache("") variable in class:RubyGPUCoalescer
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| H A D | Sequencer.py | 65 dcache = Param.RubyCache("") variable in class:RubySequencer
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| /gem5/util/tlm/conf/ |
| H A D | tlm_elastic_slave.py | 94 system.cpu.dcache = L1_DCache(size="32kB")
96 system.cpu.dcache.cpu_side = system.cpu.dcache_port
116 system.cpu.dcache.mem_side = system.membus.slave
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| /gem5/util/tlm/examples/ |
| H A D | tlm_elastic_slave_with_l2.py | 101 system.cpu.dcache = L1_DCache(size="32kB")
103 system.cpu.dcache.cpu_side = system.cpu.dcache_port
124 system.cpu.dcache.mem_side = system.tol2bus.slave
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| /gem5/configs/common/ |
| H A D | CacheConfig.py | 124 dcache = dcache_class(size=options.l1d_size,
138 dcache_real = dcache
146 dcache_mon.mem_side = dcache.cpu_side
149 dcache = dcache_mon
153 if dcache.prefetcher != m5.params.NULL:
156 "of type", type(dcache.prefetcher), ", using the",
158 dcache.prefetcher = hwpClass()
171 system.cpu[i].addPrivateSplitL1Caches(icache, dcache,
177 system.cpu[i].dcache = dcache_real
189 ExternalCache("cpu%d.dcache"
[all...] |
| /gem5/configs/learning_gem5/part1/ |
| H A D | two_level.py | 100 system.cpu.dcache = L1DCache(opts)
104 system.cpu.dcache.connectCPU(system.cpu)
111 system.cpu.dcache.connectBus(system.l2bus)
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| /gem5/configs/ruby/ |
| H A D | Garnet_standalone.py | 86 dcache = cache,
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| H A D | AMD_Base_Constructor.py | 85 self.sequencer.dcache = self.L1D0cache
93 self.sequencer1.dcache = self.L1D1cache
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| H A D | GPU_RfO.py | 120 self.sequencer.dcache = self.L1D0cache
128 self.sequencer1.dcache = self.L1D1cache
133 # Defines icache/dcache hit latency
166 self.coalescer.dcache = self.L1cache
177 self.sequencer.dcache = self.L1cache
198 self.coalescer.dcache = self.L1cache
206 self.sequencer.dcache = self.L1cache
240 self.sequencer.dcache = self.L1cache
261 self.sequencer.dcache = self.L1cache
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| H A D | GPU_VIPER.py | 106 self.sequencer.dcache = self.L1D0cache
114 self.sequencer1.dcache = self.L1D1cache
154 self.coalescer.dcache = self.L1cache
162 self.sequencer.dcache = self.L1cache
185 self.coalescer.dcache = self.L1cache
193 self.sequencer.dcache = self.L1cache
228 self.sequencer.dcache = self.L1cache
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| H A D | GPU_VIPER_Region.py | 107 self.sequencer.dcache = self.L1D0cache
115 self.sequencer1.dcache = self.L1D1cache
155 self.coalescer.dcache = self.L1cache
163 self.sequencer.dcache = self.L1cache
194 self.sequencer.dcache = self.L1cache
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| H A D | GPU_VIPER_Baseline.py | 106 self.sequencer.dcache = self.L1D0cache
114 self.sequencer1.dcache = self.L1D1cache
154 self.coalescer.dcache = self.L1cache
162 self.sequencer.dcache = self.L1cache
193 self.sequencer.dcache = self.L1cache
|
| H A D | MOESI_AMD_Base.py | 107 self.sequencer.dcache = self.L1D0cache
115 self.sequencer1.dcache = self.L1D1cache
120 # Defines icache/dcache hit latency
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| H A D | MI_example.py | 97 cpu_seq = RubySequencer(version=i, icache=cache, dcache=cache,
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| H A D | MESI_Two_Level.py | 108 dcache = l1d_cache, clk_domain = clk_domain,
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| H A D | MOESI_CMP_directory.py | 119 dcache=l1d_cache, clk_domain=clk_domain,
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| H A D | MOESI_hammer.py | 115 dcache=l1d_cache,clk_domain=clk_domain,
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| H A D | MOESI_CMP_token.py | 123 dcache=l1d_cache, clk_domain=clk_domain,
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| H A D | MESI_Three_Level.py | 120 dcache = l0d_cache,
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| /gem5/src/cpu/testers/traffic_gen/ |
| H A D | BaseTrafficGen.py | 125 self.dcache = dc
127 self._cached_ports = ['dcache.mem_side']
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| /gem5/configs/learning_gem5/part3/ |
| H A D | test_caches.py | 81 dcache = self.controllers[i].cacheMemory,
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| H A D | msi_caches.py | 87 dcache = self.controllers[i].cacheMemory,
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| H A D | ruby_caches_MI_example.py | 87 dcache = self.controllers[i].cacheMemory,
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| /gem5/src/arch/arm/ |
| H A D | ArmPMU.py | 104 icache=None, dcache=None,
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| /gem5/ext/mcpat/ |
| H A D | core.h | 188 CacheUnit* dcache; member in class:LoadStoreU
|