Searched refs:cpuId (Results 1 - 25 of 37) sorted by relevance

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/gem5/src/arch/riscv/
H A Dutility.cc38 void initCPU(ThreadContext *tc, int cpuId) argument
H A Dutility.hh120 inline void startupCPU(ThreadContext *tc, int cpuId) argument
192 void initCPU(ThreadContext *tc, int cpuId);
/gem5/src/arch/null/
H A Dutility.hh51 inline void startupCPU(ThreadContext *tc, int cpuId) {} argument
/gem5/src/arch/power/
H A Dutility.hh60 startupCPU(ThreadContext *tc, int cpuId) argument
95 void initCPU(ThreadContext *, int cpuId);
H A Dutility.cc76 initCPU(ThreadContext *tc, int cpuId) argument
/gem5/src/arch/alpha/
H A Dutility.hh70 inline void startupCPU(ThreadContext *tc, int cpuId) argument
98 void initIPRs(ThreadContext *tc, int cpuId);
99 void initCPU(ThreadContext *tc, int cpuId);
H A Dev5.cc69 initCPU(ThreadContext *tc, int cpuId) argument
71 initIPRs(tc, cpuId);
73 tc->setIntReg(16, cpuId);
74 tc->setIntReg(0, cpuId);
99 initIPRs(ThreadContext *tc, int cpuId) argument
107 tc->setMiscRegNoEffect(IPR_PALtemp16, cpuId);
/gem5/src/arch/sparc/
H A Dutility.hh72 void initCPU(ThreadContext *tc, int cpuId);
75 startupCPU(ThreadContext *tc, int cpuId) argument
78 if (cpuId == 0 || !FullSystem)
H A Dutility.cc258 initCPU(ThreadContext *tc, int cpuId) argument
261 if (cpuId == 0)
/gem5/src/arch/x86/
H A Dutility.hh79 void initCPU(ThreadContext *tc, int cpuId);
81 void startupCPU(ThreadContext *tc, int cpuId);
H A Dutility.cc74 void initCPU(ThreadContext *tc, int cpuId) argument
182 lApicBase.bsp = (cpuId == 0);
189 interrupts->setRegNoEffect(APIC_ID, cpuId << 24);
201 void startupCPU(ThreadContext *tc, int cpuId) argument
203 if (cpuId == 0 || !FullSystem) {
/gem5/src/arch/arm/tracers/
H A Dtarmac_tracer.cc52 auto id = thread->getCpuPtr()->cpuId();
H A Dtarmac_parser.hh223 cpuId(p->cpu_id),
288 bool cpuId; member in class:Trace::TarmacParser
/gem5/src/arch/mips/
H A Dutility.hh109 void startupCPU(ThreadContext *tc, int cpuId);
110 void initCPU(ThreadContext *tc, int cpuId);
H A Dutility.cc232 startupCPU(ThreadContext *tc, int cpuId) argument
238 initCPU(ThreadContext *tc, int cpuId) argument
/gem5/src/cpu/
H A Dthread_state.hh70 int cpuId() const { return baseCpu->cpuId(); } function in struct:ThreadState
H A Dinst_pb_trace.cc160 curMsg->set_cpuid(tc->cpuId());
H A Dthread_context.cc119 int id1 = one->cpuId();
120 int id2 = two->cpuId();
/gem5/src/dev/arm/
H A Dgic_v3_redistributor.hh67 uint32_t cpuId; member in class:Gicv3Redistributor
211 return cpuId;
H A Dgic_v3_redistributor.cc58 cpuId(cpu_id),
84 cpuInterface = gic->getCPUInterface(cpuId);
164 int last = cpuId == (gic->getSystem()->numContexts() - 1);
165 return (affinity << 32) | (1 << 24) | (cpuId << 8) |
983 ThreadContext * tc = gic->getSystem()->getThreadContext(cpuId);
H A Dgic_v3_cpu_interface.cc59 cpuId(cpu_id)
68 redistributor = gic->getRedistributor(cpuId);
2048 gic->postInt(cpuId, ArmISA::INT_IRQ);
2050 gic->deassertInt(cpuId, ArmISA::INT_IRQ);
2054 gic->postInt(cpuId, ArmISA::INT_FIQ);
2056 gic->deassertInt(cpuId, ArmISA::INT_FIQ);
2091 gic->postInt(cpuId, ArmISA::INT_VIRT_IRQ);
2093 gic->deassertInt(cpuId, ArmISA::INT_VIRT_IRQ);
2099 gic->postInt(cpuId, ArmISA::INT_VIRT_FIQ);
2101 gic->deassertInt(cpuId, ArmIS
[all...]
/gem5/src/sim/
H A Dpseudo_inst.cc625 int cpuId = tc->getCpuPtr()->cpuId(); local
628 sys->markWorkItem(cpuId) >= params->work_cpus_ckpt_count) {
650 if (cpuId == params->work_begin_cpu_id_exit) {
687 int cpuId = tc->getCpuPtr()->cpuId(); local
690 sys->markWorkItem(cpuId) >= params->work_cpus_ckpt_count) {
/gem5/src/arch/arm/
H A Dutility.hh105 inline void startupCPU(ThreadContext *tc, int cpuId) argument
118 void initCPU(ThreadContext *tc, int cpuId);
H A Dutility.cc58 initCPU(ThreadContext *tc, int cpuId) argument
267 assert((0 <= tc->cpuId()) && (tc->cpuId() < 256));
275 tc->cpuId() | tc->socketId() << 8;
279 tc->cpuId() | tc->socketId() << 8;
/gem5/src/cpu/o3/
H A Dthread_context.hh105 int cpuId() const override { return cpu->cpuId(); }

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