#
14018:9d2153431f44 |
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02-May-2019 |
Gabe Black <gabeblack@google.com> |
arch, base, sim: Replace Copy(String)?(In|Out) with equivalent code.
This expands those functions into code which extracts the virt proxy and then uses the appropriate method on it. This has two benefits. First, the Copy* functions where mostly redundant wrappers around the methods the proxy port already had. Second, using them forced a particular port which might not actually be what the user wanted.
Change-Id: I62084631dd080061e3c74997125164f40da2d77c Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18575 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> Tested-by: kokoro <noreply+kokoro@google.com>
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#
13905:5cf30883255c |
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27-Apr-2019 |
Gabe Black <gabeblack@google.com> |
arch: cpu: Track kernel stats using the base ISA agnostic type.
Then cast to the ISA specific type when necessary. This removes (mostly) an ISA specific aspect to some of the interfaces. The ISA specific version of the kernel stats still needs to be constructed and stored in a few places which means that kernel_stats.hh still needs to be a switching arch header, for instance.
In the future, I'd like to make the kernel its own object like the Process objects in SE mode, and then it would be able to instantiate and maintain its own stats.
Change-Id: I8309d49019124f6bea1482aaea5b5b34e8c97433 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18429 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
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#
12158:c66cf095928d |
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27-Jul-2017 |
Andreas Sandberg <andreas.sandberg@arm.com> |
sim: Use named constants for pseudo ops
Use named constants from a shared header instead of magic values when handling pseudo ops.
Change-Id: If157060bbcd772ce7e8556482b44ca714f4319b1 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/4262 Reviewed-by: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
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#
12145:9079b93ac9d4 |
|
21-Jun-2017 |
Jose Marinho <jose.marinho@arm.com> |
sim: Prevent segfault in the wakeCpu m5op if id is invalid
Change-Id: I86229cedb206e10326cdee3f09a5c871e49c8d48 Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/3965
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#
11793:ef606668d247 |
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09-Nov-2016 |
Brandon Potter <brandon.potter@amd.com> |
style: [patch 1/22] use /r/3648/ to reorganize includes
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#
11703:08b78e0a3717 |
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26-Oct-2016 |
Michael LeBeane <michael.lebeane@amd.com> |
dev: Add m5 op to toggle synchronization for dist-gem5. This patch adds the ability for an application to request dist-gem5 to begin/ end synchronization using an m5 op. When toggling on sync, all nodes agree on the next sync point based on the maximum of all nodes' ticks. CPUs are suspended until the sync point to avoid sending network messages until sync has been enabled. Toggling off sync acts like a global execution barrier, where all CPUs are disabled until every node reaches the toggle off point. This avoids tricky situations such as one node hitting a toggle off followed by a toggle on before the other nodes hit the first toggle off.
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#
11627:fe32a5238754 |
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13-Sep-2016 |
Michael LeBeane <michael.lebeane@amd.com> |
sim: Refactor quiesce and remove FS asserts The quiesce family of magic ops can be simplified by the inclusion of quiesceTick() and quiesce() functions on ThreadContext. This patch also gets rid of the FS guards, since suspending a CPU is also a valid operation for SE mode.
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#
11567:560d7fbbddd1 |
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21-Jul-2016 |
Mitch Hayenga <mitch.hayenga@arm.com> |
cpu: Add SMT support to MinorCPU
This patch adds SMT support to the MinorCPU. Currently RoundRobin or Random thread scheduling are supported.
Change-Id: I91faf39ff881af5918cca05051829fc6261f20e3
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#
11359:b0b976a1ceda |
|
27-Nov-2015 |
Andreas Sandberg <andreas@sandberg.pp.se> |
base: Add support for changing output directories
This changeset adds support for changing the simulator output directory. This can be useful when the simulation goes through several stages (e.g., a warming phase, a simulation phase, and a verification phase) since it allows the output from each stage to be located in a different directory. Relocation is done by calling core.setOutputDir() from Python or simout.setOutputDirectory() from C++.
This change affects several parts of the design of the gem5's output subsystem. First, files returned by an OutputDirectory instance (e.g., simout) are of the type OutputStream instead of a std::ostream. This allows us to do some more book keeping and control re-opening of files when the output directory is changed. Second, new subdirectories are OutputDirectory instances, which should be used to create files in that sub-directory.
Signed-off-by: Andreas Sandberg <andreas@sandberg.pp.se> [sascha.bischoff@arm.com: Rebased patches onto a newer gem5 version] Signed-off-by: Sascha Bischoff <sascha.bischoff@arm.com> Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
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#
11320:42ecb523c64a |
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06-Feb-2016 |
Steve Reinhardt <steve.reinhardt@amd.com> |
style: remove trailing whitespace
Result of running 'hg m5style --skip-all --fix-white -a'.
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#
11290:1640dd68b0a4 |
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07-Jan-2016 |
Gabor Dozsa <gabor.dozsa@arm.com> |
dev: Distributed Ethernet link for distributed gem5 simulations
Distributed gem5 (abbreviated dist-gem5) is the result of the convergence effort between multi-gem5 and pd-gem5 (from Univ. of Wisconsin). It relies on the base multi-gem5 infrastructure for packet forwarding, synchronisation and checkpointing but combines those with the elaborated network switch model from pd-gem5.
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#
11289:ab19693da8c9 |
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07-Jan-2016 |
Gabor Dozsa <gabor.dozsa@arm.com> |
pseudo inst,util: Add optional key to initparam pseudo instruction
The key parameter can be used to read out various config parameters from within the simulated software.
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#
11270:a3b41de1c4f1 |
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14-Dec-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
sim: Add an option to forward work items to Python
There are cases where we want the Python world to handle work items instead of the C++ world. However, that's currently not possible. This changeset adds the forward_work_items option to the System class. Then it is set to True, work items will generate workbegin/workend simulation exists with the work item ID as the exit code and the old C++ handling is completely bypassed.
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#
11259:4006183015a1 |
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05-Nov-2015 |
Sascha Bischoff <sascha.bischoff@ARM.com> |
sim: Disable gzip compression for writefile pseudo instruction
The writefile pseudo instruction uses OutputDirectory::create and OutputDirectory::openFile to create the output files. However, by default these will check the file extention for .gz, and create a gzip compressed stream if the file ending matches. When writing out files, we want to write them out exactly as they are in the guest simulation, and never want to compress them with gzio. Additionally, this causes m5 writefile to fail when checking the error flags for the output steam.
With this patch we add an additional no_gz argument to OutputDirectory::create and OutputDirectory::openFile which allows us to override the gzip compression. Therefore, for m5 writefile we disable the filename check, and always create a standard ostream.
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#
11058:d0934b57735a |
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26-Aug-2015 |
Emilio Castillo <ecastill@bsc.es> |
cpu: quiesce pseudoinsts: Always do full quiesce
The O3CPU blocks the Fetch when it sees a quiesce instruction (IsQuiesce flag). When the inst. is executed, a quiesce event is created to reactivate the context and unblock the Fetch.
If the quiesceNs or quiesceCycles are called with a value of 0, the QuiesceEvent will not be created and the Fetch stage will remain blocked.
Committed by Joel Hestness <jthestness@gmail.com>
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#
10553:c1ad57c53a36 |
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23-Nov-2014 |
Alexandru Dutu <alexandru.dutu@amd.com> |
kvm, x86: Adding support for SE mode execution This patch adds methods in KvmCPU model to handle KVM exits caused by syscall instructions and page faults. These types of exits will be encountered if KvmCPU is run in SE mode.
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#
9952:7437cc334df1 |
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31-Oct-2013 |
Dam Sunwoo <dam.sunwoo@arm.com> |
sim: added option to serialize SimLoopExitEvent
SimLoopExitEvents weren't serialized by default. Some benchmarks utilize a delayed m5 exit pseudo op call to terminate the simulation and this event was lost when resuming from a checkpoint generated after the pseudo op call. This patch adds the capability to serialize the SimLoopExitEvents and enable serialization for m5_exit and m5_fail pseudo ops by default. Does not affect other generic SimLoopExitEvents.
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#
9879:5fad1d2eb314 |
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18-Sep-2013 |
Andreas Sandberg <andreas@sandberg.pp.se> |
sim: Fix undefined behavior in the pseudo-inst interface
The order between updating and using arg_num in PseudoInst::pseudoInst() is currently undefined. This changeset explicitly updates arg_num after it has been used to extract an argument.
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#
9733:9d85dfa4696c |
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03-Jun-2013 |
Andreas Sandberg <andreas@sandberg.pp.se> |
sim: Add debug output when executing pseudo-instructions
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#
9681:4597012dfa97 |
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02-May-2013 |
Andreas Sandberg <andreas@sandberg.pp.se> |
sim: Add support for m5fail in pseudoInst()
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#
9659:403a4d20799a |
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22-Apr-2013 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
sim: Add a helper function to execute pseudo instructions
All architectures execute m5 pseudo instructions by setting up arguments according to the ABI and executing a magic instruction that contains an operation number. Handling of such instructions is currently spread across the different ISA implementations. This changeset introduces the PseudoInst::pseudoInst function which handles most of this in an architecture independent way. This is function is mainly intended to be used from KVM, but can also be used from the simulated CPUs.
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#
9457:a4739b6f799d |
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08-Jan-2013 |
LluĂs Vilanova <vilanova@ac.upc.edu> |
util: add m5_fail op.
Used as a command in full-system scripts helps the user ensure the benchmarks have finished successfully.
For example, one can use:
/path/to/benchmark args || /sbin/m5 fail 1
and thus ensure gem5 will exit with an error if the benchmark fails.
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#
9180:ee8d7a51651d |
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28-Aug-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Clock: Add a Cycles wrapper class and use where applicable
This patch addresses the comments and feedback on the preceding patch that reworks the clocks and now more clearly shows where cycles (relative cycle counts) are used to express time.
Instead of bumping the existing patch I chose to make this a separate patch, merely to try and focus the discussion around a smaller set of changes. The two patches will be pushed together though.
This changes done as part of this patch are mostly following directly from the introduction of the wrapper class, and change enough code to make things compile and run again. There are definitely more places where int/uint/Tick is still used to represent cycles, and it will take some time to chase them all down. Similarly, a lot of parameters should be changed from Param.Tick and Param.Unsigned to Param.Cycles.
In addition, the use of curTick is questionable as there should not be an absolute cycle. Potential solutions can be built on top of this patch. There is a similar situation in the o3 CPU where lastRunningCycle is currently counting in Cycles, and is still an absolute time. More discussion to be had in other words.
An additional change that would be appropriate in the future is to perform a similar wrapping of Tick and probably also introduce a Ticks class along with suitable operators for all these classes.
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#
8809:bb10807da889 |
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01-Feb-2012 |
Gabe Black <gblack@eecs.umich.edu> |
Merge with head, hopefully the last time for this batch.
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#
8806:669e93d79ed9 |
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29-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
Implement Ali's review feedback.
Try to decrease indentation, and remove some redundant FullSystem checks.
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8798:adaa92be9037 |
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16-Jan-2012 |
Gabe Black <gblack@eecs.umich.edu> |
Merge yet again with the main repository.
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#
8794:e2ac2b7164dd |
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18-Nov-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Get rid of includes of config/full_system.hh.
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#
8784:05fb20d7064b |
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02-Nov-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Get rid of FULL_SYSTEM in sim.
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#
8777:dd43f1c9fa0a |
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31-Oct-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SE/FS: Make the functions available from the TC consistent between SE and FS.
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#
8734:79592b2b1d55 |
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31-Jan-2012 |
Dam Sunwoo <dam.sunwoo@arm.com> |
util: implements "writefile" gem5 op to export file from guest to host filesystem
Usage: m5 writefile <filename>
File will be created in the gem5 output folder with the identical filename. Implementation is largely based on the existing "readfile" functionality. Currently does not support exporting of folders.
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#
8666:97d873b8b13e |
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09-Jan-2012 |
Prakash Ramrakhyani <Prakash.Ramrakhyani@arm.com> |
sim: Enable sampling of run-time for code-sections marked using pseudo insts.
This patch adds a mechanism to collect run time samples for specific portions of a benchmark, using work_begin and work_end pseudo instructions.It also enhances the histogram stat to report geometric mean.
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#
8580:a32e8ce374d6 |
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22-Sep-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
pseudo_inst: clean up workbegin/workend functions Use exitSimLoop() function instead of explicitly scheduling on mainEventQueue (which won't work once we go to multiple event queues). Also introduced a local params variable to shorten a lot of expressions.
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#
8555:6fd8d0432d8d |
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19-Sep-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Pseudoinst: Add an initParam pseudo inst function.
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#
8232:b28d06a175be |
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15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help
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#
8231:51cf7f3cf9ac |
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15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
debug: create a Debug namespace
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#
8229:78bf55f23338 |
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15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
includes: sort all includes
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#
8142:e08035e1a1f6 |
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17-Mar-2011 |
Ali Saidi <Ali.Saidi@ARM.com> |
ARM: Allow conditional quiesce instructions.
This patch prevents not executed conditional instructions marked as IsQuiesce from stalling the pipeline indefinitely. If the instruction is not executed the quiesceSkip psuedoinst is called which schedules a wakes up call to the fetch stage.
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7914:eee5bb0fb8ea |
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07-Feb-2011 |
Brad Beckmann <Brad.Beckmann@amd.com> |
m5: added work completed monitoring support
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#
7823:dac01f14f20f |
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08-Jan-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
Replace curTick global variable with accessor functions. This step makes it easy to replace the accessor functions (which still access a global variable) with ones that access per-thread curTick values.
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#
7822:fc475ac7d2a4 |
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08-Jan-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
stats: rename StatEvent() function to schedStatEvent(). This follows the style rules and is more descriptive.
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#
7819:afe8476ee9e9 |
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08-Jan-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
pseudoinst: get rid of mainEventQueue references. Avoid direct references to mainEventQueue in pseudo-insts by indirecting through associated CPU object. Made exitSimLoop() more flexible to enable some of these.
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#
7811:a8fc35183c10 |
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03-Jan-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
Make commenting on close namespace brackets consistent.
Ran all the source files through 'perl -pi' with this script:
s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;
Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript.
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7064:586b0e3a12b3 |
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15-Apr-2010 |
Nathan Binkert <nate@binkert.org> |
tick: rename Clock namespace to SimClock
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#
6658:f4de76601762 |
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23-Sep-2009 |
Nathan Binkert <nate@binkert.org> |
arch: nuke arch/isa_specific.hh and move stuff to generated config/the_isa.hh
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#
6227:a17798f2a52c |
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05-Jun-2009 |
Nathan Binkert <nate@binkert.org> |
types: clean up types, especially signed vs unsigned
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#
6118:a1d388751779 |
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21-Apr-2009 |
Nathan Binkert <nate@binkert.org> |
pseudo: only include kernel stats if FULL_SYSTEM.
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#
5952:c1ee8282291d |
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26-Feb-2009 |
Ali Saidi <saidi@eecs.umich.edu> |
CPA: Add new object for gathering critical path annotations.
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#
5882:5a047c3f3795 |
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23-Feb-2009 |
Nathan Binkert <nate@binkert.org> |
debug: Move debug_break into src/base
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#
5808:baf5d5c96c68 |
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24-Jan-2009 |
Nathan Binkert <nate@binkert.org> |
pseudo inst: Add new wake cpu instruction for sending a message to wake a cpu. It's instantaneous and so it's somewhat bogus, but it's a first step.
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#
5780:50c9d48de3ca |
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17-Dec-2008 |
Steve Reinhardt <steve.reinhardt@amd.com> |
Make Alpha pseudo-insts available from SE mode.
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#
5741:323dac95e72c |
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10-Nov-2008 |
Nathan Binkert <nate@binkert.org> |
pseudo inst: Add rpns (read processor nanoseconds) instruction. This instruction basically returns the number of nanoseconds that the CPU has been running.
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#
5606:6da7a58b0bc8 |
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09-Oct-2008 |
Nathan Binkert <nate@binkert.org> |
eventq: convert all usage of events to use the new API. For now, there is still a single global event queue, but this is necessary for making the steps towards a parallelized m5.
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#
5529:9ae69b9cd7fd |
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11-Aug-2008 |
Nathan Binkert <nate@binkert.org> |
params: Convert the CPU objects to use the auto generated param structs. A whole bunch of stuff has been converted to use the new params stuff, but the CPU wasn't one of them. While we're at it, make some things a bit more stylish. Most of the work was done by Gabe, I just cleaned stuff up a bit more at the end.
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#
5505:90d6811d5ea6 |
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11-Jul-2008 |
Nathan Binkert <nate@binkert.org> |
m5ops: clean up the m5ops stuff. - insert warnings for deprecated m5ops - reserve opcodes for Ali's stuff - remove code for stuff that has been deprecated forever - simplify m5op_alpha
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5504:288b54c2fd8d |
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11-Jul-2008 |
Nathan Binkert <nate@binkert.org> |
style: fix indentation and formatting of the pseudo insts.
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#
5100:7a0180040755 |
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28-Sep-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Rename cycles() function to ticks()
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#
4437:b6e304245729 |
|
09-May-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
update for new reschedule semantics
|
#
4090:08bd6439b907 |
|
21-Feb-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
add pseduo instruction support for sparc
util/m5/Makefile.alpha: Clean up to make it a bit easier to muck with util/m5/Makefile.alpha: Make the makefile more reasonable util/m5/Makefile.alpha: Remove authors from copyright. util/m5/Makefile.alpha: Updated Authors from bk prs info util/m5/Makefile.alpha: bk cp Makefile Makefile.alpha src/arch/sparc/tlb.cc: Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate src/arch/alpha/isa/decoder.isa: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: Rename AlphaPseudo -> PseudoInst since it's all generic src/arch/sparc/isa/bitfields.isa: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/includes.isa: src/arch/sparc/isa/operands.isa: Add support for pseudo instructions in sparc util/m5/Makefile.alpha: util/m5/Makefile.sparc: split off alpha make file and sparc make file for m5 app util/m5/m5.c: ivle and ivlb aren't used anymore util/m5/m5op.h: stdint seems like a more generic better fit here util/m5/m5op_alpha.S: move the op ids into their own header file since we can share them between sparc and alpha
|
#
4078:3f73f808bbd4 |
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18-Feb-2007 |
Nathan Binkert <binkertn@umich.edu> |
Get rid of the Statistics and Statreset ParamContexts, and expose all of the relevant functionality to python. Clean up the mysql code while we're at it.
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#
3617:384e3b1eae06 |
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11-Nov-2006 |
Nathan Binkert <binkertn@umich.edu> |
Get rid of the ParamContext for pseudo instructions and move the parameters to the BaseCPU object.
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#
3565:6ad587fb7dfd |
|
07-Nov-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Put kernel_stats back into arch.
|
#
3538:76ab83131a79 |
|
06-Nov-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Got rid of obsolete ivlb and ivle psuedo instructions.
|
#
3373:999202ee312c |
|
22-Oct-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Add DPRINTF for non-timed quiesce.
|
#
3368:3342dd3f5248 |
|
22-Oct-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Add Quiesce trace flag to track CPU quiesce/wakeup events.
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#
3144:b6e9e1811d71 |
|
06-Oct-2006 |
Lisa Hsu <hsul@eecs.umich.edu> |
there are two main thrusts of this changeset.
1) return the periodicity of checkpoints back into the code (i.e. make m5 checkpoint n m meaningful again). 2) to do this, i had to much around with being able to repeatedly schedule and SimLoopExitEvent, which led to changes in how exit simloop events are handled to make this easier.
src/arch/alpha/isa/decoder.isa: src/mem/cache/cache_impl.hh: modify arg. order for new calling convention of exitSimLoop. src/cpu/base.cc: src/sim/main.cc: src/sim/pseudo_inst.cc: src/sim/root.cc: now, instead of creating a new SimLoopExitEvent, call a wrapper schedExitSimLoop which handles all the default args. src/sim/sim_events.cc: src/sim/sim_events.hh: src/sim/sim_exit.hh: add the periodicity of checkpointing back into the code.
to facilitate this, there are now two wrappers (instead of just overloading exitSimLoop). exitSimLoop is only for exiting NOW (i.e. at curTick), while schedExitSimLoop schedules and exit event for the future.
|
#
3126:756092c6383c |
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02-Oct-2006 |
Kevin Lim <ktlim@umich.edu> |
Updates to fix merge issues and bring almost everything up to working speed. Ozone CPU remains untested, but everything else compiles and runs.
src/arch/alpha/isa_traits.hh: This got changed to the wrong version by accident. src/cpu/base.cc: Fix up progress event to not schedule itself if the interval is set to 0. src/cpu/base.hh: Fix up the CPU Progress Event to not print itself if it's set to 0. Also remove stats_reset_inst (something I added to m5 but isn't necessary here). src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.hh: Remove float variable of instResult; it's always held within the double part now. src/cpu/checker/cpu_impl.hh: Use thread and not cpuXC. src/cpu/o3/alpha/cpu_builder.cc: src/cpu/o3/checker_builder.cc: src/cpu/ozone/checker_builder.cc: src/cpu/ozone/cpu_builder.cc: src/python/m5/objects/BaseCPU.py: Remove stats_reset_inst. src/cpu/o3/commit_impl.hh: src/cpu/ozone/lw_back_end_impl.hh: Get TC, not XCProxy. src/cpu/o3/cpu.cc: Switch out updates from the version of m5 I have. Also remove serialize code that got added twice. src/cpu/o3/iew_impl.hh: src/cpu/o3/lsq_impl.hh: src/cpu/thread_state.hh: Remove code that was added twice. src/cpu/o3/lsq_unit.hh: Add back in stats that got lost in the merge. src/cpu/o3/lsq_unit_impl.hh: Use proper method to get flags. Also wake CPU if we're coming back from a cache miss. src/cpu/o3/thread_context_impl.hh: src/cpu/o3/thread_state.hh: Support profiling. src/cpu/ozone/cpu.hh: Update to use proper typename. src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/dyn_inst_impl.hh: Updates for newmem. src/cpu/ozone/lw_lsq_impl.hh: Get flags correctly. src/cpu/ozone/thread_state.hh: Reorder constructor initialization, use tc. src/sim/pseudo_inst.cc: Allow for loading of symbol file. Be sure to use ThreadContext and not ExecContext.
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3125:febd811bccc6 |
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30-Sep-2006 |
Kevin Lim <ktlim@umich.edu> |
Merge ktlim@zamp:./local/clean/o3-merge/m5 into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
configs/boot/micro_memlat.rcS: configs/boot/micro_tlblat.rcS: src/arch/alpha/ev5.cc: src/arch/alpha/isa/decoder.isa: src/arch/alpha/isa_traits.hh: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.hh: src/cpu/checker/cpu_impl.hh: src/cpu/o3/alpha/cpu_impl.hh: src/cpu/o3/alpha/params.hh: src/cpu/o3/checker_builder.cc: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_impl.hh: src/cpu/o3/lsq_unit.hh: src/cpu/o3/lsq_unit_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/checker_builder.cc: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/thread_state.hh: src/cpu/simple/base.cc: src/cpu/simple_thread.cc: src/cpu/simple_thread.hh: src/cpu/thread_state.hh: src/dev/ide_disk.cc: src/python/m5/objects/O3CPU.py: src/python/m5/objects/Root.py: src/python/m5/objects/System.py: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: src/sim/system.hh: util/m5/m5.c: Hand merge.
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3089:0ea2eb13c4de |
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11-Sep-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
add annotation code to m5
configs/common/Benchmarks.py: add annotate test app src/SConscript: add annotate.cc to lis src/arch/alpha/isa/decoder.isa: add annotate instructions src/base/traceflags.py: Add annotate trace flag src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: add annotate pseudo ops util/m5/m5op.S: util/m5/m5op.h: add anotate ops
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2861:0265b505b50a |
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06-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Two minor FS compile fixes.
src/dev/tsunami_pchip.hh: Need ULL() for 32-bit hosts. src/sim/pseudo_inst.cc: Forgot to remove sampler include from here.
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2841:d874ac38161c |
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05-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
For now using the checkpoint or switchcpu pseudo instructions will return control to Python, returning the cause to be the instruction name. The user's script must then interpret the reason for exiting the simulation loop and handle the action accordingly. This may change in the future.
src/sim/pseudo_inst.cc: Exit sim loop with a specific string to indicate to Python what caused the exit. The user's script needs to interpret the exit events and handle them as desired.
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2840:227f7c4f8c81 |
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05-Jul-2006 |
Kevin Lim <ktlim@umich.edu> |
Remove sampler and serializer. Now they are handled through C++ interacting with Python.
src/SConscript: src/cpu/base.cc: src/cpu/base.hh: src/cpu/checker/cpu.hh: src/cpu/checker/cpu_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/sim/pseudo_inst.cc: Remove sampler. src/sim/sim_object.cc: Remove serializer.
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2799:1c93aed5aa4a |
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29-Jun-2006 |
Kevin Lim <ktlim@umich.edu> |
Remove function that no longer can be used. We should figure out if we want to allow the m5checkpoint pseudoinstruction or not.
src/sim/pseudo_inst.cc: Remove the setup function from Checkpoint. I'm not sure what we want to do with this pseudoinst. src/sim/serialize.hh: Remove setup function.
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2708:c4157b162e7b |
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09-Jun-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Merge vm1.(none):/home/stever/bk/newmem into vm1.(none):/home/stever/bk/newmem-py
src/python/m5/__init__.py: src/sim/syscall_emul.cc: Hand merge.
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2680:246e7104f744 |
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06-Jun-2006 |
Kevin Lim <ktlim@umich.edu> |
Change ExecContext to ThreadContext. This is being renamed to differentiate between the interface used objects outside of the CPU, and the interface used by the ISA. ThreadContext is used by objects outside of the CPU and is specifically defined in thread_context.hh. ExecContext is more implicit, and is defined by files such as base_dyn_inst.hh or cpu/simple/base.hh.
Further renames/reorganization will be coming shortly; what is currently CPUExecContext (the old ExecContext from m5) will be renamed to SimpleThread or something similar.
src/arch/alpha/arguments.cc: src/arch/alpha/arguments.hh: src/arch/alpha/ev5.cc: src/arch/alpha/faults.cc: src/arch/alpha/faults.hh: src/arch/alpha/freebsd/system.cc: src/arch/alpha/freebsd/system.hh: src/arch/alpha/isa/branch.isa: src/arch/alpha/isa/decoder.isa: src/arch/alpha/isa/main.isa: src/arch/alpha/linux/process.cc: src/arch/alpha/linux/system.cc: src/arch/alpha/linux/system.hh: src/arch/alpha/linux/threadinfo.hh: src/arch/alpha/process.cc: src/arch/alpha/regfile.hh: src/arch/alpha/stacktrace.cc: src/arch/alpha/stacktrace.hh: src/arch/alpha/tlb.cc: src/arch/alpha/tlb.hh: src/arch/alpha/tru64/process.cc: src/arch/alpha/tru64/system.cc: src/arch/alpha/tru64/system.hh: src/arch/alpha/utility.hh: src/arch/alpha/vtophys.cc: src/arch/alpha/vtophys.hh: src/arch/mips/faults.cc: src/arch/mips/faults.hh: src/arch/mips/isa_traits.cc: src/arch/mips/isa_traits.hh: src/arch/mips/linux/process.cc: src/arch/mips/process.cc: src/arch/mips/regfile/float_regfile.hh: src/arch/mips/regfile/int_regfile.hh: src/arch/mips/regfile/misc_regfile.hh: src/arch/mips/regfile/regfile.hh: src/arch/mips/stacktrace.hh: src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: src/arch/sparc/isa_traits.hh: src/arch/sparc/linux/process.cc: src/arch/sparc/linux/process.hh: src/arch/sparc/process.cc: src/arch/sparc/regfile.hh: src/arch/sparc/solaris/process.cc: src/arch/sparc/stacktrace.hh: src/arch/sparc/ua2005.cc: src/arch/sparc/utility.hh: src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: src/base/remote_gdb.cc: src/base/remote_gdb.hh: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.hh: src/cpu/checker/cpu.cc: src/cpu/checker/cpu.hh: src/cpu/checker/exec_context.hh: src/cpu/cpu_exec_context.cc: src/cpu/cpu_exec_context.hh: src/cpu/cpuevent.cc: src/cpu/cpuevent.hh: src/cpu/exetrace.hh: src/cpu/intr_control.cc: src/cpu/memtest/memtest.hh: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/regfile.hh: src/cpu/o3/thread_state.hh: src/cpu/ozone/back_end.hh: src/cpu/ozone/cpu.hh: src/cpu/ozone/cpu_impl.hh: src/cpu/ozone/front_end.hh: src/cpu/ozone/front_end_impl.hh: src/cpu/ozone/inorder_back_end.hh: src/cpu/ozone/lw_back_end.hh: src/cpu/ozone/lw_back_end_impl.hh: src/cpu/ozone/lw_lsq.hh: src/cpu/ozone/lw_lsq_impl.hh: src/cpu/ozone/thread_state.hh: src/cpu/pc_event.cc: src/cpu/pc_event.hh: src/cpu/profile.cc: src/cpu/profile.hh: src/cpu/quiesce_event.cc: src/cpu/quiesce_event.hh: src/cpu/simple/atomic.cc: src/cpu/simple/base.cc: src/cpu/simple/base.hh: src/cpu/simple/timing.cc: src/cpu/static_inst.cc: src/cpu/static_inst.hh: src/cpu/thread_state.hh: src/dev/alpha_console.cc: src/dev/ns_gige.cc: src/dev/sinic.cc: src/dev/tsunami_cchip.cc: src/kern/kernel_stats.cc: src/kern/kernel_stats.hh: src/kern/linux/events.cc: src/kern/linux/events.hh: src/kern/system_events.cc: src/kern/system_events.hh: src/kern/tru64/dump_mbuf.cc: src/kern/tru64/tru64.hh: src/kern/tru64/tru64_events.cc: src/kern/tru64/tru64_events.hh: src/mem/vport.cc: src/mem/vport.hh: src/sim/faults.cc: src/sim/faults.hh: src/sim/process.cc: src/sim/process.hh: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: src/sim/syscall_emul.cc: src/sim/syscall_emul.hh: src/sim/system.cc: src/cpu/thread_context.hh: src/sim/system.hh: src/sim/vptr.hh: Change ExecContext to ThreadContext.
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2670:9107b8bd08cd |
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02-Jun-2006 |
Kevin Lim <ktlim@umich.edu> |
Merge ktlim@zizzer:/bk/newmem into zizzer.eecs.umich.edu:/.automount/zamp/z/ktlim2/clean/newmem
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2667:fe64b8353b1c |
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09-Jun-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
Move main control from C++ into Python. User script now invokes initialization and simulation loop after building configuration. These functions are exported from C++ to Python using SWIG.
SConstruct: Set up SWIG builder & scanner. Set up symlinking of source files into build directory (by not disabling the default behavior). configs/test/test.py: Rewrite to use new script-driven interface. Include a sample option. src/SConscript: Set up symlinking of source files into build directory (by not disabling the default behavior). Add SWIG-generated main_wrap.cc to source list. src/arch/SConscript: Set up symlinking of source files into build directory (by not disabling the default behavior). src/arch/alpha/ev5.cc: src/arch/alpha/isa/decoder.isa: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/trace/opt_cpu.cc: src/cpu/trace/trace_cpu.cc: src/sim/pseudo_inst.cc: src/sim/root.cc: src/sim/serialize.cc: src/sim/syscall_emul.cc: SimExit() is now exitSimLoop(). src/cpu/base.cc: SimExitEvent is now SimLoopExitEvent src/python/SConscript: Add SWIG build command for main.i. Use python/m5 in build dir as source for zip archive... easy now with file duplication enabled. src/python/m5/__init__.py: - Move copyright notice back to C++ so we can print it right away, even for interactive sessions. - Get rid of argument parsing code; just provide default option descriptors for user script to call optparse with. - Don't clutter m5 namespace by sucking in all of m5.config and m5.objects. - Move instantiate() function here from config.py. src/python/m5/config.py: - Move instantiate() function to __init__.py. - Param.Foo deferred type lookups must use m5.objects namespace now (not m5). src/python/m5/objects/AlphaConsole.py: src/python/m5/objects/AlphaFullCPU.py: src/python/m5/objects/AlphaTLB.py: src/python/m5/objects/BadDevice.py: src/python/m5/objects/BaseCPU.py: src/python/m5/objects/BaseCache.py: src/python/m5/objects/Bridge.py: src/python/m5/objects/Bus.py: src/python/m5/objects/CoherenceProtocol.py: src/python/m5/objects/Device.py: src/python/m5/objects/DiskImage.py: src/python/m5/objects/Ethernet.py: src/python/m5/objects/Ide.py: src/python/m5/objects/IntrControl.py: src/python/m5/objects/MemObject.py: src/python/m5/objects/MemTest.py: src/python/m5/objects/Pci.py: src/python/m5/objects/PhysicalMemory.py: src/python/m5/objects/Platform.py: src/python/m5/objects/Process.py: src/python/m5/objects/Repl.py: src/python/m5/objects/Root.py: src/python/m5/objects/SimConsole.py: src/python/m5/objects/SimpleDisk.py: src/python/m5/objects/System.py: src/python/m5/objects/Tsunami.py: src/python/m5/objects/Uart.py: Fix up imports (m5 namespace no longer includes m5.config). src/sim/eventq.cc: src/sim/eventq.hh: Support for Python-called simulate() function: - Use IsExitEvent flag to signal events that want to exit the simulation loop gracefully (instead of calling exit() to terminate the process). - Modify interface to hand exit event object back to caller so it can be inspected for cause. src/sim/host.hh: Add MaxTick constant. src/sim/main.cc: Move copyright notice back to C++ so we can print it right away, even for interactive sessions. Use PYTHONPATH environment var to set module path (instead of clunky code injection method). Move main control from here into Python: - Separate initialization code and simulation loop into separate functions callable from Python. - Make Python interpreter invocation more pure (more like directly invoking interpreter). Add -i and -p flags (only options on binary itself; other options processed by Python). Import readline package when using interactive mode. src/sim/sim_events.cc: SimExitEvent is now SimLoopExitEvent, and uses IsSimExit flag to terminate loop (instead of exiting simulator process). src/sim/sim_events.hh: SimExitEvent is now SimLoopExitEvent, and uses IsSimExit flag to terminate loop (instead of exiting simulator process). Get rid of a few unused constructors. src/sim/sim_exit.hh: SimExit() is now exitSimLoop(). Get rid of unused functions. Add comments.
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2665:a124942bacb8 |
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31-May-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Updated Authors from bk prs info
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2654:9559cfa91b9d |
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30-May-2006 |
Kevin Lim <ktlim@umich.edu> |
Merge ktlim@zizzer:/bk/m5 into zamp.eecs.umich.edu:/z/ktlim2/clean/newmem
SConstruct: src/SConscript: src/arch/SConscript: src/arch/alpha/faults.cc: src/arch/alpha/tlb.cc: src/base/traceflags.py: src/cpu/SConscript: src/cpu/base.cc: src/cpu/base.hh: src/cpu/base_dyn_inst.cc: src/cpu/cpu_exec_context.cc: src/cpu/cpu_exec_context.hh: src/cpu/exec_context.hh: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_impl.hh: src/cpu/o3/alpha_dyn_inst.hh: src/cpu/o3/cpu.cc: src/cpu/o3/cpu.hh: src/cpu/o3/regfile.hh: src/cpu/ozone/cpu.hh: src/cpu/simple/base.cc: src/cpu/base_dyn_inst.hh: src/cpu/o3/2bit_local_pred.cc: src/cpu/o3/2bit_local_pred.hh: src/cpu/o3/alpha_cpu.cc: src/cpu/o3/alpha_cpu_builder.cc: src/cpu/o3/alpha_dyn_inst.cc: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/alpha_impl.hh: src/cpu/o3/alpha_params.hh: src/cpu/o3/bpred_unit.cc: src/cpu/o3/bpred_unit.hh: src/cpu/o3/bpred_unit_impl.hh: src/cpu/o3/btb.cc: src/cpu/o3/btb.hh: src/cpu/o3/comm.hh: src/cpu/o3/commit.cc: src/cpu/o3/commit.hh: src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu_policy.hh: src/cpu/o3/decode.cc: src/cpu/o3/decode.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch.cc: src/cpu/o3/fetch.hh: src/cpu/o3/fetch_impl.hh: src/cpu/o3/free_list.cc: src/cpu/o3/free_list.hh: src/cpu/o3/iew.cc: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.cc: src/cpu/o3/inst_queue.hh: src/cpu/o3/inst_queue_impl.hh: src/cpu/o3/mem_dep_unit.cc: src/cpu/o3/mem_dep_unit.hh: src/cpu/o3/mem_dep_unit_impl.hh: src/cpu/o3/ras.cc: src/cpu/o3/ras.hh: src/cpu/o3/rename.cc: src/cpu/o3/rename.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/rename_map.cc: src/cpu/o3/rename_map.hh: src/cpu/o3/rob.cc: src/cpu/o3/rob.hh: src/cpu/o3/rob_impl.hh: src/cpu/o3/sat_counter.cc: src/cpu/o3/sat_counter.hh: src/cpu/o3/store_set.cc: src/cpu/o3/store_set.hh: src/cpu/o3/tournament_pred.cc: src/cpu/o3/tournament_pred.hh: Hand merges.
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2632:1bb2f91485ea |
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22-May-2006 |
Steve Reinhardt <stever@eecs.umich.edu> |
New directory structure: - simulator source now in 'src' subdirectory - imported files from 'ext' repository - support building in arbitrary places, including outside of the source tree. See comment at top of SConstruct file for more details. Regression tests are temporarily disabled; that syetem needs more extensive revisions.
SConstruct: Update for new directory structure. Modify to support build trees that are not subdirectories of the source tree. See comment at top of file for more details. Regression tests are temporarily disabled. src/arch/SConscript: src/arch/isa_parser.py: src/python/SConscript: Update for new directory structure.
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