| /gem5/src/mem/ruby/structures/ |
| H A D | ReplacementPolicy.py | 39 block_size = Param.Int(Parent.cache_line_size, "block size in bytes")
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| /gem5/src/mem/cache/compressors/ |
| H A D | Compressors.py | 38 block_size = Param.Int(Parent.cache_line_size, "Block size in bytes")
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| /gem5/src/mem/probes/ |
| H A D | StackDistProbe.py | 51 line_size = Param.Unsigned(Parent.cache_line_size,
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| /gem5/src/mem/cache/tags/ |
| H A D | Tags.py | 55 block_size = Param.Int(Parent.cache_line_size, "block size in bytes")
73 entry_size = Param.Int(Parent.cache_line_size,
98 entry_size = Parent.cache_line_size * Self.num_blocks_per_sector
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| /gem5/src/sim/ |
| H A D | System.py | 84 cache_line_size = Param.Unsigned(64, "Cache line size in bytes") variable in class:System
|
| H A D | system.cc | 96 physProxy(_systemPort, p->cache_line_size),
108 _cacheLineSize(p->cache_line_size),
|
| /gem5/util/tlm/conf/ |
| H A D | tlm_elastic_slave.py | 73 cache_line_size = 64) variable
|
| /gem5/util/tlm/examples/ |
| H A D | tlm_elastic_slave_with_l2.py | 80 cache_line_size = 64) variable
|
| /gem5/configs/example/ |
| H A D | etrace_replay.py | 86 cache_line_size = options.cacheline_size) variable
|
| H A D | memtest.py | 227 cache_line_size = block_size) variable
|
| H A D | se.py | 179 cache_line_size = options.cacheline_size) variable
|
| H A D | fs.py | 109 test_sys.cache_line_size = options.cacheline_size
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| H A D | apu_se.py | 423 cache_line_size = options.cacheline_size, variable
|
| /gem5/src/mem/cache/ |
| H A D | Cache.py | 72 block_size = Param.Int(Parent.cache_line_size, "block size in bytes")
|
| /gem5/src/arch/alpha/ |
| H A D | system.cc | 49 : System(p), intrFreq(0), virtProxy(getSystemPort(), p->cache_line_size)
|
| /gem5/configs/learning_gem5/part3/ |
| H A D | msi_caches.py | 147 bits = int(math.log(system.cache_line_size, 2))
148 if 2**bits != system.cache_line_size.value:
|
| H A D | ruby_caches_MI_example.py | 144 bits = int(math.log(system.cache_line_size, 2))
145 if 2**bits != system.cache_line_size.value:
|
| /gem5/configs/example/arm/ |
| H A D | starter_se.py | 87 cache_line_size = 64 variable in class:SimpleSeSystem
|
| H A D | devices.py | 188 cache_line_size = 64 variable in class:SimpleSystem
|
| /gem5/configs/common/ |
| H A D | FileSystemConfig.py | 116 cacheline_size=system.cache_line_size.getValue())
|
| H A D | MemConfig.py | 214 intlv_size = max(128, system.cache_line_size.value)
|
| H A D | CacheConfig.py | 88 system.cache_line_size = options.cacheline_size
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| /gem5/configs/dram/ |
| H A D | lat_mem_rd.py | 142 system.cache_line_size = burst_size
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| /gem5/src/mem/cache/prefetch/ |
| H A D | Prefetcher.py | 73 block_size = Param.Int(Parent.cache_line_size, "Block size in bytes")
|