111251Sradhika.jagtap@ARM.com# Copyright (c) 2015 ARM Limited 211251Sradhika.jagtap@ARM.com# All rights reserved. 311251Sradhika.jagtap@ARM.com# 411251Sradhika.jagtap@ARM.com# The license below extends only to copyright in the software and shall 511251Sradhika.jagtap@ARM.com# not be construed as granting a license to any other intellectual 611251Sradhika.jagtap@ARM.com# property including but not limited to intellectual property relating 711251Sradhika.jagtap@ARM.com# to a hardware implementation of the functionality of the software 811251Sradhika.jagtap@ARM.com# licensed hereunder. You may use the software subject to the license 911251Sradhika.jagtap@ARM.com# terms below provided that you ensure that this notice is replicated 1011251Sradhika.jagtap@ARM.com# unmodified and in its entirety in all distributions of the software, 1111251Sradhika.jagtap@ARM.com# modified or unmodified, in source code or in binary form. 1211251Sradhika.jagtap@ARM.com# 1311251Sradhika.jagtap@ARM.com# Redistribution and use in source and binary forms, with or without 1411251Sradhika.jagtap@ARM.com# modification, are permitted provided that the following conditions are 1511251Sradhika.jagtap@ARM.com# met: redistributions of source code must retain the above copyright 1611251Sradhika.jagtap@ARM.com# notice, this list of conditions and the following disclaimer; 1711251Sradhika.jagtap@ARM.com# redistributions in binary form must reproduce the above copyright 1811251Sradhika.jagtap@ARM.com# notice, this list of conditions and the following disclaimer in the 1911251Sradhika.jagtap@ARM.com# documentation and/or other materials provided with the distribution; 2011251Sradhika.jagtap@ARM.com# neither the name of the copyright holders nor the names of its 2111251Sradhika.jagtap@ARM.com# contributors may be used to endorse or promote products derived from 2211251Sradhika.jagtap@ARM.com# this software without specific prior written permission. 2311251Sradhika.jagtap@ARM.com# 2411251Sradhika.jagtap@ARM.com# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2511251Sradhika.jagtap@ARM.com# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2611251Sradhika.jagtap@ARM.com# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2711251Sradhika.jagtap@ARM.com# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2811251Sradhika.jagtap@ARM.com# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2911251Sradhika.jagtap@ARM.com# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3011251Sradhika.jagtap@ARM.com# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3111251Sradhika.jagtap@ARM.com# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3211251Sradhika.jagtap@ARM.com# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3311251Sradhika.jagtap@ARM.com# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3411251Sradhika.jagtap@ARM.com# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3511251Sradhika.jagtap@ARM.com# 3611251Sradhika.jagtap@ARM.com# Authors: Radhika Jagtap 3711251Sradhika.jagtap@ARM.com 3811251Sradhika.jagtap@ARM.com# Basic elastic traces replay script that configures a Trace CPU 3911251Sradhika.jagtap@ARM.com 4012564Sgabeblack@google.comfrom __future__ import print_function 4113774Sandreas.sandberg@arm.comfrom __future__ import absolute_import 4212564Sgabeblack@google.com 4311251Sradhika.jagtap@ARM.comimport optparse 4411251Sradhika.jagtap@ARM.com 4511251Sradhika.jagtap@ARM.comfrom m5.util import addToPath, fatal 4611251Sradhika.jagtap@ARM.com 4711682Sandreas.hansson@arm.comaddToPath('../') 4811251Sradhika.jagtap@ARM.com 4911682Sandreas.hansson@arm.comfrom common import Options 5011682Sandreas.hansson@arm.comfrom common import Simulation 5111682Sandreas.hansson@arm.comfrom common import CacheConfig 5211682Sandreas.hansson@arm.comfrom common import MemConfig 5311682Sandreas.hansson@arm.comfrom common.Caches import * 5411251Sradhika.jagtap@ARM.com 5511251Sradhika.jagtap@ARM.comparser = optparse.OptionParser() 5611251Sradhika.jagtap@ARM.comOptions.addCommonOptions(parser) 5711251Sradhika.jagtap@ARM.com 5811251Sradhika.jagtap@ARM.comif '--ruby' in sys.argv: 5912564Sgabeblack@google.com print("This script does not support Ruby configuration, mainly" 6012564Sgabeblack@google.com " because Trace CPU has been tested only with classic memory system") 6111251Sradhika.jagtap@ARM.com sys.exit(1) 6211251Sradhika.jagtap@ARM.com 6311251Sradhika.jagtap@ARM.com(options, args) = parser.parse_args() 6411251Sradhika.jagtap@ARM.com 6511251Sradhika.jagtap@ARM.comif args: 6612564Sgabeblack@google.com print("Error: script doesn't take any positional arguments") 6711251Sradhika.jagtap@ARM.com sys.exit(1) 6811251Sradhika.jagtap@ARM.com 6911251Sradhika.jagtap@ARM.comnumThreads = 1 7011251Sradhika.jagtap@ARM.com 7112014Sgabeblack@google.comif options.cpu_type != "TraceCPU": 7211251Sradhika.jagtap@ARM.com fatal("This is a script for elastic trace replay simulation, use "\ 7312014Sgabeblack@google.com "--cpu-type=TraceCPU\n"); 7411251Sradhika.jagtap@ARM.com 7511251Sradhika.jagtap@ARM.comif options.num_cpus > 1: 7611251Sradhika.jagtap@ARM.com fatal("This script does not support multi-processor trace replay.\n") 7711251Sradhika.jagtap@ARM.com 7811251Sradhika.jagtap@ARM.com# In this case FutureClass will be None as there is not fast forwarding or 7911251Sradhika.jagtap@ARM.com# switching 8011251Sradhika.jagtap@ARM.com(CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 8111251Sradhika.jagtap@ARM.comCPUClass.numThreads = numThreads 8211251Sradhika.jagtap@ARM.com 8311251Sradhika.jagtap@ARM.comsystem = System(cpu = CPUClass(cpu_id=0), 8411251Sradhika.jagtap@ARM.com mem_mode = test_mem_mode, 8511251Sradhika.jagtap@ARM.com mem_ranges = [AddrRange(options.mem_size)], 8611251Sradhika.jagtap@ARM.com cache_line_size = options.cacheline_size) 8711251Sradhika.jagtap@ARM.com 8811251Sradhika.jagtap@ARM.com# Create a top-level voltage domain 8911251Sradhika.jagtap@ARM.comsystem.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 9011251Sradhika.jagtap@ARM.com 9111251Sradhika.jagtap@ARM.com# Create a source clock for the system. This is used as the clock period for 9211251Sradhika.jagtap@ARM.com# xbar and memory 9311251Sradhika.jagtap@ARM.comsystem.clk_domain = SrcClockDomain(clock = options.sys_clock, 9411251Sradhika.jagtap@ARM.com voltage_domain = system.voltage_domain) 9511251Sradhika.jagtap@ARM.com 9611251Sradhika.jagtap@ARM.com# Create a CPU voltage domain 9711251Sradhika.jagtap@ARM.comsystem.cpu_voltage_domain = VoltageDomain() 9811251Sradhika.jagtap@ARM.com 9911251Sradhika.jagtap@ARM.com# Create a separate clock domain for the CPUs. In case of Trace CPUs this clock 10011251Sradhika.jagtap@ARM.com# is actually used only by the caches connected to the CPU. 10111251Sradhika.jagtap@ARM.comsystem.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 10211251Sradhika.jagtap@ARM.com voltage_domain = 10311251Sradhika.jagtap@ARM.com system.cpu_voltage_domain) 10411251Sradhika.jagtap@ARM.com 10511251Sradhika.jagtap@ARM.com# All cpus belong to a common cpu_clk_domain, therefore running at a common 10611251Sradhika.jagtap@ARM.com# frequency. 10711251Sradhika.jagtap@ARM.comfor cpu in system.cpu: 10811251Sradhika.jagtap@ARM.com cpu.clk_domain = system.cpu_clk_domain 10911251Sradhika.jagtap@ARM.com 11012430Schenzou@uchicago.edu# BaseCPU no longer has default values for the BaseCPU.isa 11112430Schenzou@uchicago.edu# createThreads() is needed to fill in the cpu.isa 11212430Schenzou@uchicago.edufor cpu in system.cpu: 11312430Schenzou@uchicago.edu cpu.createThreads() 11412430Schenzou@uchicago.edu 11511251Sradhika.jagtap@ARM.com# Assign input trace files to the Trace CPU 11611251Sradhika.jagtap@ARM.comsystem.cpu.instTraceFile=options.inst_trace_file 11711251Sradhika.jagtap@ARM.comsystem.cpu.dataTraceFile=options.data_trace_file 11811251Sradhika.jagtap@ARM.com 11911251Sradhika.jagtap@ARM.com# Configure the classic memory system options 12011251Sradhika.jagtap@ARM.comMemClass = Simulation.setMemClass(options) 12111251Sradhika.jagtap@ARM.comsystem.membus = SystemXBar() 12211251Sradhika.jagtap@ARM.comsystem.system_port = system.membus.slave 12311251Sradhika.jagtap@ARM.comCacheConfig.config_cache(options, system) 12411251Sradhika.jagtap@ARM.comMemConfig.config_mem(options, system) 12511251Sradhika.jagtap@ARM.com 12611251Sradhika.jagtap@ARM.comroot = Root(full_system = False, system = system) 12711251Sradhika.jagtap@ARM.comSimulation.run(options, root, system, FutureClass) 128