Searched refs:ULL (Results 1 - 25 of 93) sorted by relevance

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/gem5/src/arch/mips/
H A Disa_traits.hh51 const Addr PageBytes = ULL(1) << PageShift;
63 const Addr NPtePage = ULL(1) << NPtePageShift;
70 const Addr USegBase = ULL(0x0);
71 const Addr USegEnd = ULL(0x7FFFFFFF);
74 const Addr KSeg0End = ULL(0x9FFFFFFF);
75 const Addr KSeg0Base = ULL(0x80000000);
76 const Addr KSeg0Mask = ULL(0x1FFFFFFF);
79 const Addr KSeg1End = ULL(0xBFFFFFFF);
80 const Addr KSeg1Base = ULL(0xA0000000);
81 const Addr KSeg1Mask = ULL(
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H A Ddsp.hh105 const uint64_t FIXED_L_SMAX = ULL(0x7fffffffffffffff);
106 const uint64_t FIXED_W_SMAX = ULL(0x000000007fffffff);
107 const uint64_t FIXED_H_SMAX = ULL(0x0000000000007fff);
108 const uint64_t FIXED_B_SMAX = ULL(0x000000000000007f);
109 const uint64_t FIXED_L_UMAX = ULL(0xffffffffffffffff);
110 const uint64_t FIXED_W_UMAX = ULL(0x00000000ffffffff);
111 const uint64_t FIXED_H_UMAX = ULL(0x000000000000ffff);
112 const uint64_t FIXED_B_UMAX = ULL(0x00000000000000ff);
119 const uint64_t FIXED_L_SMIN = ULL(0x8000000000000000);
120 const uint64_t FIXED_W_SMIN = ULL(
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/gem5/src/arch/null/
H A Disa_traits.hh48 const Addr PageBytes = ULL(1) << PageShift;
/gem5/src/systemc/core/
H A Dtime.cc65 [::sc_core::SC_FS] = 1ULL * 1000 * 1000 * 1000 * 1000 * 1000,
66 [::sc_core::SC_PS] = 1ULL * 1000 * 1000 * 1000 * 1000,
67 [::sc_core::SC_NS] = 1ULL * 1000 * 1000 * 1000,
68 [::sc_core::SC_US] = 1ULL * 1000 * 1000,
69 [::sc_core::SC_MS] = 1ULL * 1000,
70 [::sc_core::SC_SEC] = 1ULL
/gem5/src/arch/riscv/
H A Disa_traits.hh61 const Addr PageBytes = ULL(1) << PageShift;
H A Dregisters.hh655 const RegVal ISA_MXL_MASK = 3ULL << MXL_OFFSET;
659 const RegVal STATUS_SD_MASK = 1ULL << ((sizeof(uint64_t) * 8) - 1);
660 const RegVal STATUS_SXL_MASK = 3ULL << SXL_OFFSET;
661 const RegVal STATUS_UXL_MASK = 3ULL << UXL_OFFSET;
662 const RegVal STATUS_TSR_MASK = 1ULL << 22;
663 const RegVal STATUS_TW_MASK = 1ULL << 21;
664 const RegVal STATUS_TVM_MASK = 1ULL << 20;
665 const RegVal STATUS_MXR_MASK = 1ULL << 19;
666 const RegVal STATUS_SUM_MASK = 1ULL << 18;
667 const RegVal STATUS_MPRV_MASK = 1ULL << 1
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/gem5/src/arch/x86/
H A Disa_traits.hh57 const Addr PageBytes = ULL(1) << PageShift;
H A Dx86_traits.hh67 const Addr IntAddrPrefixMask = ULL(0xffffffff00000000);
68 const Addr IntAddrPrefixCPUID = ULL(0x100000000);
69 const Addr IntAddrPrefixMSR = ULL(0x200000000);
70 const Addr IntAddrPrefixIO = ULL(0x300000000);
72 const Addr PhysAddrPrefixIO = ULL(0x8000000000000000);
73 const Addr PhysAddrPrefixPciConfig = ULL(0xC000000000000000);
74 const Addr PhysAddrPrefixLocalAPIC = ULL(0x2000000000000000);
75 const Addr PhysAddrPrefixInterrupts = ULL(0xA000000000000000);
/gem5/src/arch/alpha/
H A Disa_traits.hh49 const Addr PageBytes = ULL(1) << PageShift;
60 const Addr NPtePage = ULL(1) << NPtePageShift;
64 const Addr USegBase = ULL(0x0);
65 const Addr USegEnd = ULL(0x000003ffffffffff);
68 const Addr K0SegBase = ULL(0xfffffc0000000000);
69 const Addr K0SegEnd = ULL(0xfffffdffffffffff);
72 const Addr K1SegBase = ULL(0xfffffe0000000000);
73 const Addr K1SegEnd = ULL(0xffffffffffffffff);
H A Dev5.hh42 const uint64_t AsnMask = ULL(0xff);
44 const Addr VAddrImplMask = (ULL(1) << VAddrImplBits) - 1;
52 inline bool PAddrIprSpace(Addr a) { return a >= ULL(0xFFFFFF00000); }
54 const Addr PAddrImplMask = (ULL(1) << PAddrImplBits) - 1;
55 const Addr PAddrUncachedBit39 = ULL(0x8000000000);
56 const Addr PAddrUncachedBit40 = ULL(0x10000000000);
57 const Addr PAddrUncachedBit43 = ULL(0x80000000000);
58 const Addr PAddrUncachedMask = ULL(0x807ffffffff); // Clear PA<42:35>
72 { return reg >> 32 & ((ULL(1) << (PAddrImplBits - PageShift)) - 1); }
82 { return reg >> 32 & ((ULL(
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H A Dinterrupts.hh95 intstatus |= (ULL(1) << int_num);
111 intstatus &= ~(ULL(1) << int_num);
155 if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
158 summary |= (ULL(1) << i);
165 if (intstatus & (ULL(1) << i)) {
168 summary |= (ULL(1) << i);
185 if (tc->readMiscRegNoEffect(IPR_SIRR) & (ULL(1) << i)) {
188 summary |= (ULL(1) << i);
195 if (intstatus & (ULL(1) << i)) {
198 summary |= (ULL(
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H A Dev5.cc164 retval |= ipr[idx] & ULL(0xffffffff00000000);
165 retval |= tc->getCpuPtr()->curCycle() & ULL(0x00000000ffffffff);
184 retval |= ((uint64_t)entry.ppn & ULL(0x7ffffff)) << 32;
185 retval |= ((uint64_t)entry.xre & ULL(0xf)) << 8;
186 retval |= ((uint64_t)entry.xwe & ULL(0xf)) << 12;
187 retval |= ((uint64_t)entry.fonr & ULL(0x1)) << 1;
188 retval |= ((uint64_t)entry.fonw & ULL(0x1))<< 2;
189 retval |= ((uint64_t)entry.asma & ULL(0x1)) << 4;
190 retval |= ((uint64_t)entry.asn & ULL(0x7f)) << 57;
332 ipr[idx] = val & ULL(
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/gem5/src/arch/sparc/
H A Disa_traits.hh48 const Addr PageBytes = ULL(1) << PageShift;
H A Dpagetable.hh238 entry |= 1ULL << 1; // Writable
239 entry |= 0ULL << 2; // Available in nonpriveleged mode
240 entry |= 0ULL << 3; // No side effects
242 entry |= 1ULL << 4; // Virtually cachable
243 entry |= 1ULL << 5; // Physically cachable
245 entry |= 0ULL << 6; // Not locked
247 entry |= 0ULL << 48; // size = 8k
249 entry |= 0ULL << 60; // Not no fault only
250 entry |= 0ULL << 61; // size = 8k
251 entry |= 1ULL << 6
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/gem5/ext/systemc/src/sysc/datatypes/int/
H A Dsc_nbdefs.cpp74 const uint64 UINT64_ZERO = 0ULL;
75 const uint64 UINT64_ONE = 1ULL;
/gem5/src/arch/power/
H A Disa_traits.hh52 const Addr PageBytes = ULL(1) << PageShift;
58 const Addr NPtePage = ULL(1) << NPtePageShift;
/gem5/src/arch/arm/
H A Disa_traits.hh61 const Addr PageBytes = ULL(1) << PageShift;
73 const Addr NPtePage = ULL(1) << NPtePageShift;
80 const Addr USegBase = ULL(0x0);
81 const Addr USegEnd = ULL(0x7FFFFFFF);
85 const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
91 const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
/gem5/src/dev/alpha/
H A Dtsunami_pchip.cc68 pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
250 #define DMA_ADDR_MASK ULL(0x3ffffffff)
270 windowMask = ~wsm[i] & (ULL(0xfff) << 20);
286 tbaMask = ~(((wsm[i] & (ULL(0xfff) << 20)) >> 10) |
287 ULL(0x3ff));
288 baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13);
294 dmaAddr = ((pteEntry & ~ULL(
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H A Dtsunamireg.h38 #define ALPHA_K0SEG_BASE ULL(0xfffffc0000000000)
142 #define PCHIP_PCI0_MEMORY ULL(0x00000000000)
143 #define PCHIP_PCI0_IO ULL(0x001FC000000)
144 #define TSUNAMI_UNCACHABLE_BIT ULL(0x80000000000)
/gem5/src/base/
H A Dintmath.hh123 if (x & ULL(0xffffffff00000000)) { y += 32; x >>= 32; }
141 if (x & ULL(0xffffffff00000000)) { y += 32; x >>= 32; }
142 if (x & ULL(0x00000000ffff0000)) { y += 16; x >>= 16; }
143 if (x & ULL(0x000000000000ff00)) { y += 8; x >>= 8; }
144 if (x & ULL(0x00000000000000f0)) { y += 4; x >>= 4; }
145 if (x & ULL(0x000000000000000c)) { y += 2; x >>= 2; }
146 if (x & ULL(0x0000000000000002)) { y += 1; }
H A Daddr_range.hh132 fatal_if(!masks.empty() && _intlv_match >= ULL(1) << masks.size(),
167 fatal_if(_intlv_bits && _intlv_match >= ULL(1) << _intlv_bits,
189 Addr mask = (1ULL << bit1);
192 mask |= (1ULL << bit2);
222 if (ranges.size() != (ULL(1) << masks.size()))
263 return ULL(1) << lowest_bit;
275 uint32_t stripes() const { return ULL(1) << masks.size(); }
316 mask &= ~(1ULL << bit);
/gem5/src/unittest/
H A Dstattest.cc386 f2 = (-s1) / (-s2) * (-s3 + ULL(100) + s4);
423 curEventQueue()->setCurTick(curTick() + ULL(1000000));
498 curEventQueue()->setCurTick(curTick() + ULL(1000000));
500 curEventQueue()->setCurTick(curTick() + ULL(1000000));
502 curEventQueue()->setCurTick(curTick() + ULL(1000000));
504 curEventQueue()->setCurTick(curTick() + ULL(1000000));
506 curEventQueue()->setCurTick(curTick() + ULL(1000000));
513 curEventQueue()->setCurTick(curTick() + ULL(1000000));
515 curEventQueue()->setCurTick(curTick() + ULL(1000000));
517 curEventQueue()->setCurTick(curTick() + ULL(100000
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/gem5/src/dev/mips/
H A Dmaltareg.h40 #define ALPHA_K0SEG_BASE ULL(0xfffffc0000000000)
153 #define PCHIP_PCI0_MEMORY ULL(0x00000000000)
154 #define PCHIP_PCI0_IO ULL(0x001FC000000)
155 #define TSUNAMI_UNCACHABLE_BIT ULL(0x80000000000)
/gem5/util/tlm/examples/slave_port/
H A Dmain.cc69 unsigned long long int memorySize = 512*1024*1024ULL;
/gem5/src/systemc/ext/dt/int/
H A Dsc_nbdefs.hh175 static const uint64 UINT64_ZERO = 0ULL;
176 static const uint64 UINT64_ONE = 1ULL;

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