arch/riscv/registers.hh

655 const RegVal ISA_MXL_MASK = 3ULL << MXL_OFFSET;
659 const RegVal STATUS_SD_MASK = 1ULL << ((sizeof(uint64_t) * 8) - 1);
660 const RegVal STATUS_SXL_MASK = 3ULL << SXL_OFFSET;
661 const RegVal STATUS_UXL_MASK = 3ULL << UXL_OFFSET;
662 const RegVal STATUS_TSR_MASK = 1ULL << 22;
663 const RegVal STATUS_TW_MASK = 1ULL << 21;
664 const RegVal STATUS_TVM_MASK = 1ULL << 20;
665 const RegVal STATUS_MXR_MASK = 1ULL << 19;
666 const RegVal STATUS_SUM_MASK = 1ULL << 18;
667 const RegVal STATUS_MPRV_MASK = 1ULL << 17;
668 const RegVal STATUS_XS_MASK = 3ULL << 15;
669 const RegVal STATUS_FS_MASK = 3ULL << FS_OFFSET;
670 const RegVal STATUS_MPP_MASK = 3ULL << 11;
671 const RegVal STATUS_SPP_MASK = 1ULL << 8;
672 const RegVal STATUS_MPIE_MASK = 1ULL << 7;
673 const RegVal STATUS_SPIE_MASK = 1ULL << 5;
674 const RegVal STATUS_UPIE_MASK = 1ULL << 4;
675 const RegVal STATUS_MIE_MASK = 1ULL << 3;
676 const RegVal STATUS_SIE_MASK = 1ULL << 1;
677 const RegVal STATUS_UIE_MASK = 1ULL << 0;
699 const RegVal MEI_MASK = 1ULL << 11;
700 const RegVal SEI_MASK = 1ULL << 9;
701 const RegVal UEI_MASK = 1ULL << 8;
702 const RegVal MTI_MASK = 1ULL << 7;
703 const RegVal STI_MASK = 1ULL << 5;
704 const RegVal UTI_MASK = 1ULL << 4;
705 const RegVal MSI_MASK = 1ULL << 3;
706 const RegVal SSI_MASK = 1ULL << 1;
707 const RegVal USI_MASK = 1ULL << 0;