1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 *          Andrew Schultz
30 */
31
32/** @file
33 * Tsunami PChip (pci)
34 */
35#include "dev/alpha/tsunami_pchip.hh"
36
37#include <deque>
38#include <string>
39#include <vector>
40
41#include "base/trace.hh"
42#include "config/the_isa.hh"
43#include "debug/Tsunami.hh"
44#include "dev/alpha/tsunami.hh"
45#include "dev/alpha/tsunami_cchip.hh"
46#include "dev/alpha/tsunamireg.h"
47#include "dev/pci/device.hh"
48#include "mem/packet.hh"
49#include "mem/packet_access.hh"
50#include "sim/system.hh"
51
52using namespace std;
53//Should this be AlphaISA?
54using namespace TheISA;
55
56TsunamiPChip::TsunamiPChip(const Params *p)
57    : GenericPciHost(p),
58      pioRange(RangeSize(p->pio_addr, 0x1000)),
59      pioDelay(p->pio_latency)
60{
61    for (int i = 0; i < 4; i++) {
62        wsba[i] = 0;
63        wsm[i] = 0;
64        tba[i] = 0;
65    }
66
67    // initialize pchip control register
68    pctl = (ULL(0x1) << 20) | (ULL(0x1) << 32) | (ULL(0x2) << 36);
69
70    //Set back pointer in tsunami
71    p->tsunami->pchip = this;
72}
73
74Tick
75TsunamiPChip::read(PacketPtr pkt)
76{
77    // We only need to handle our own configuration registers, pass
78    // unknown addresses to the generic code.
79    if (!pioRange.contains(pkt->getAddr()))
80        return GenericPciHost::read(pkt);
81
82    Addr daddr = (pkt->getAddr() - pioRange.start()) >> 6;;
83    assert(pkt->getSize() == sizeof(uint64_t));
84
85
86    DPRINTF(Tsunami, "read  va=%#x size=%d\n", pkt->getAddr(), pkt->getSize());
87
88    switch(daddr) {
89      case TSDEV_PC_WSBA0:
90            pkt->setLE(wsba[0]);
91            break;
92      case TSDEV_PC_WSBA1:
93            pkt->setLE(wsba[1]);
94            break;
95      case TSDEV_PC_WSBA2:
96            pkt->setLE(wsba[2]);
97            break;
98      case TSDEV_PC_WSBA3:
99            pkt->setLE(wsba[3]);
100            break;
101      case TSDEV_PC_WSM0:
102            pkt->setLE(wsm[0]);
103            break;
104      case TSDEV_PC_WSM1:
105            pkt->setLE(wsm[1]);
106            break;
107      case TSDEV_PC_WSM2:
108            pkt->setLE(wsm[2]);
109            break;
110      case TSDEV_PC_WSM3:
111            pkt->setLE(wsm[3]);
112            break;
113      case TSDEV_PC_TBA0:
114            pkt->setLE(tba[0]);
115            break;
116      case TSDEV_PC_TBA1:
117            pkt->setLE(tba[1]);
118            break;
119      case TSDEV_PC_TBA2:
120            pkt->setLE(tba[2]);
121            break;
122      case TSDEV_PC_TBA3:
123            pkt->setLE(tba[3]);
124            break;
125      case TSDEV_PC_PCTL:
126            pkt->setLE(pctl);
127            break;
128      case TSDEV_PC_PLAT:
129            panic("PC_PLAT not implemented\n");
130      case TSDEV_PC_RES:
131            panic("PC_RES not implemented\n");
132      case TSDEV_PC_PERROR:
133            pkt->setLE((uint64_t)0x00);
134            break;
135      case TSDEV_PC_PERRMASK:
136            pkt->setLE((uint64_t)0x00);
137            break;
138      case TSDEV_PC_PERRSET:
139            panic("PC_PERRSET not implemented\n");
140      case TSDEV_PC_TLBIV:
141            panic("PC_TLBIV not implemented\n");
142      case TSDEV_PC_TLBIA:
143            pkt->setLE((uint64_t)0x00); // shouldn't be readable, but linux
144            break;
145      case TSDEV_PC_PMONCTL:
146            panic("PC_PMONCTL not implemented\n");
147      case TSDEV_PC_PMONCNT:
148            panic("PC_PMONCTN not implemented\n");
149      default:
150          panic("Default in PChip Read reached reading 0x%x\n", daddr);
151    }
152
153    pkt->makeAtomicResponse();
154    return pioDelay;
155
156}
157
158Tick
159TsunamiPChip::write(PacketPtr pkt)
160{
161    // We only need to handle our own configuration registers, pass
162    // unknown addresses to the generic code.
163    if (!pioRange.contains(pkt->getAddr()))
164        return GenericPciHost::write(pkt);
165
166    Addr daddr = (pkt->getAddr() - pioRange.start()) >> 6;
167
168    assert(pkt->getSize() == sizeof(uint64_t));
169
170    DPRINTF(Tsunami, "write - va=%#x size=%d \n", pkt->getAddr(), pkt->getSize());
171
172    switch(daddr) {
173        case TSDEV_PC_WSBA0:
174              wsba[0] = pkt->getLE<uint64_t>();
175              break;
176        case TSDEV_PC_WSBA1:
177              wsba[1] = pkt->getLE<uint64_t>();
178              break;
179        case TSDEV_PC_WSBA2:
180              wsba[2] = pkt->getLE<uint64_t>();
181              break;
182        case TSDEV_PC_WSBA3:
183              wsba[3] = pkt->getLE<uint64_t>();
184              break;
185        case TSDEV_PC_WSM0:
186              wsm[0] = pkt->getLE<uint64_t>();
187              break;
188        case TSDEV_PC_WSM1:
189              wsm[1] = pkt->getLE<uint64_t>();
190              break;
191        case TSDEV_PC_WSM2:
192              wsm[2] = pkt->getLE<uint64_t>();
193              break;
194        case TSDEV_PC_WSM3:
195              wsm[3] = pkt->getLE<uint64_t>();
196              break;
197        case TSDEV_PC_TBA0:
198              tba[0] = pkt->getLE<uint64_t>();
199              break;
200        case TSDEV_PC_TBA1:
201              tba[1] = pkt->getLE<uint64_t>();
202              break;
203        case TSDEV_PC_TBA2:
204              tba[2] = pkt->getLE<uint64_t>();
205              break;
206        case TSDEV_PC_TBA3:
207              tba[3] = pkt->getLE<uint64_t>();
208              break;
209        case TSDEV_PC_PCTL:
210              pctl = pkt->getLE<uint64_t>();
211              break;
212        case TSDEV_PC_PLAT:
213              panic("PC_PLAT not implemented\n");
214        case TSDEV_PC_RES:
215              panic("PC_RES not implemented\n");
216        case TSDEV_PC_PERROR:
217              break;
218        case TSDEV_PC_PERRMASK:
219              panic("PC_PERRMASK not implemented\n");
220        case TSDEV_PC_PERRSET:
221              panic("PC_PERRSET not implemented\n");
222        case TSDEV_PC_TLBIV:
223              panic("PC_TLBIV not implemented\n");
224        case TSDEV_PC_TLBIA:
225              break; // value ignored, supposted to invalidate SG TLB
226        case TSDEV_PC_PMONCTL:
227              panic("PC_PMONCTL not implemented\n");
228        case TSDEV_PC_PMONCNT:
229              panic("PC_PMONCTN not implemented\n");
230        default:
231            panic("Default in PChip write reached reading 0x%x\n", daddr);
232
233    } // uint64_t
234
235    pkt->makeAtomicResponse();
236    return pioDelay;
237}
238
239
240AddrRangeList
241TsunamiPChip::getAddrRanges() const
242{
243    return AddrRangeList({
244            RangeSize(confBase, confSize),
245            pioRange
246        });
247}
248
249
250#define DMA_ADDR_MASK ULL(0x3ffffffff)
251
252Addr
253TsunamiPChip::dmaAddr(const PciBusAddr &dev, Addr busAddr) const
254{
255    // compare the address to the window base registers
256    uint64_t tbaMask = 0;
257    uint64_t baMask = 0;
258
259    uint64_t windowMask = 0;
260    uint64_t windowBase = 0;
261
262    uint64_t pteEntry = 0;
263
264    Addr pteAddr;
265    Addr dmaAddr;
266
267    for (int i = 0; i < 4; i++) {
268
269        windowBase = wsba[i];
270        windowMask = ~wsm[i] & (ULL(0xfff) << 20);
271
272        if ((busAddr & windowMask) == (windowBase & windowMask)) {
273
274            if (wsba[i] & 0x1) {   // see if enabled
275                if (wsba[i] & 0x2) { // see if SG bit is set
276                    /** @todo
277                        This currently is faked by just doing a direct
278                        read from memory, however, to be realistic, this
279                        needs to actually do a bus transaction.  The process
280                        is explained in the tsunami documentation on page
281                        10-12 and basically munges the address to look up a
282                        PTE from a table in memory and then uses that mapping
283                        to create an address for the SG page
284                    */
285
286                    tbaMask = ~(((wsm[i] & (ULL(0xfff) << 20)) >> 10) |
287                                ULL(0x3ff));
288                    baMask = (wsm[i] & (ULL(0xfff) << 20)) | (ULL(0x7f) << 13);
289                    pteAddr = (tba[i] & tbaMask) | ((busAddr & baMask) >> 10);
290
291                    sys->physProxy.readBlob(pteAddr, &pteEntry,
292                                            sizeof(uint64_t));
293
294                    dmaAddr = ((pteEntry & ~ULL(0x1)) << 12) |
295                              (busAddr & ULL(0x1fff));
296
297                } else {
298                    baMask = (wsm[i] & (ULL(0xfff) << 20)) | ULL(0xfffff);
299                    tbaMask = ~baMask;
300                    dmaAddr = (tba[i] & tbaMask) | (busAddr & baMask);
301                }
302
303                return (dmaAddr & DMA_ADDR_MASK);
304            }
305        }
306    }
307
308    // if no match was found, then return the original address
309    return busAddr;
310}
311
312void
313TsunamiPChip::serialize(CheckpointOut &cp) const
314{
315    SERIALIZE_SCALAR(pctl);
316    SERIALIZE_ARRAY(wsba, 4);
317    SERIALIZE_ARRAY(wsm, 4);
318    SERIALIZE_ARRAY(tba, 4);
319}
320
321void
322TsunamiPChip::unserialize(CheckpointIn &cp)
323{
324    UNSERIALIZE_SCALAR(pctl);
325    UNSERIALIZE_ARRAY(wsba, 4);
326    UNSERIALIZE_ARRAY(wsm, 4);
327    UNSERIALIZE_ARRAY(tba, 4);
328}
329
330
331TsunamiPChip *
332TsunamiPChipParams::create()
333{
334    return new TsunamiPChip(this);
335}
336