1/*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer;
10 * redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution;
13 * neither the name of the copyright holders nor the names of its
14 * contributors may be used to endorse or promote products derived from
15 * this software without specific prior written permission.
16 *
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
20 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
21 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 *
29 * Authors: Gabe Black
30 *          Korey Sewell
31 *          Jaidev Patwardhan
32 */
33
34#ifndef __ARCH_MIPS_ISA_TRAITS_HH__
35#define __ARCH_MIPS_ISA_TRAITS_HH__
36
37#include "arch/mips/types.hh"
38#include "base/types.hh"
39#include "cpu/static_inst_fwd.hh"
40
41namespace LittleEndianGuest {}
42
43namespace MipsISA
44{
45
46using namespace LittleEndianGuest;
47
48StaticInstPtr decodeInst(ExtMachInst);
49
50const Addr PageShift = 13;
51const Addr PageBytes = ULL(1) << PageShift;
52const Addr Page_Mask = ~(PageBytes - 1);
53const Addr PageOffset = PageBytes - 1;
54
55
56////////////////////////////////////////////////////////////////////////
57//
58//  Translation stuff
59//
60
61const Addr PteShift = 3;
62const Addr NPtePageShift = PageShift - PteShift;
63const Addr NPtePage = ULL(1) << NPtePageShift;
64const Addr PteMask = NPtePage - 1;
65
66//// All 'Mapped' segments go through the TLB
67//// All other segments are translated by dropping the MSB, to give
68//// the corresponding physical address
69// User Segment - Mapped
70const Addr USegBase = ULL(0x0);
71const Addr USegEnd = ULL(0x7FFFFFFF);
72
73// Kernel Segment 0 - Unmapped
74const Addr KSeg0End = ULL(0x9FFFFFFF);
75const Addr KSeg0Base =  ULL(0x80000000);
76const Addr KSeg0Mask = ULL(0x1FFFFFFF);
77
78// Kernel Segment 1 - Unmapped, Uncached
79const Addr KSeg1End = ULL(0xBFFFFFFF);
80const Addr KSeg1Base = ULL(0xA0000000);
81const Addr KSeg1Mask = ULL(0x1FFFFFFF);
82
83// Kernel/Supervisor Segment - Mapped
84const Addr KSSegEnd = ULL(0xDFFFFFFF);
85const Addr KSSegBase = ULL(0xC0000000);
86
87// Kernel Segment 3 - Mapped
88const Addr KSeg3End = ULL(0xFFFFFFFF);
89const Addr KSeg3Base = ULL(0xE0000000);
90
91
92inline Addr Phys2K0Seg(Addr addr)
93{
94    return addr | KSeg0Base;
95}
96
97
98const unsigned VABits = 32;
99const unsigned PABits = 32; // Is this correct?
100const Addr VAddrImplMask = (ULL(1) << VABits) - 1;
101const Addr VAddrUnImplMask = ~VAddrImplMask;
102inline Addr VAddrImpl(Addr a) { return a & VAddrImplMask; }
103inline Addr VAddrVPN(Addr a) { return a >> MipsISA::PageShift; }
104inline Addr VAddrOffset(Addr a) { return a & MipsISA::PageOffset; }
105
106const Addr PAddrImplMask = (ULL(1) << PABits) - 1;
107
108////////////////////////////////////////////////////////////////////////
109//
110//  Interrupt levels
111//
112enum InterruptLevels
113{
114    INTLEVEL_SOFTWARE_MIN = 4,
115    INTLEVEL_SOFTWARE_MAX = 19,
116
117    INTLEVEL_EXTERNAL_MIN = 20,
118    INTLEVEL_EXTERNAL_MAX = 34,
119
120    INTLEVEL_IRQ0 = 20,
121    INTLEVEL_IRQ1 = 21,
122    INTINDEX_ETHERNET = 0,
123    INTINDEX_SCSI = 1,
124    INTLEVEL_IRQ2 = 22,
125    INTLEVEL_IRQ3 = 23,
126
127    INTLEVEL_SERIAL = 33,
128
129    NumInterruptLevels = INTLEVEL_EXTERNAL_MAX
130};
131
132// MIPS modes
133enum mode_type
134{
135    mode_kernel = 0,        // kernel
136    mode_supervisor = 1,    // supervisor
137    mode_user = 2,          // user mode
138    mode_debug = 3,         // debug mode
139    mode_number             // number of modes
140};
141
142const int ANNOTE_NONE = 0;
143const uint32_t ITOUCH_ANNOTE = 0xffffffff;
144
145const bool HasUnalignedMemAcc = true;
146
147const bool CurThreadInfoImplemented = false;
148const int CurThreadInfoReg = -1;
149
150} // namespace MipsISA
151
152#endif // __ARCH_MIPS_ISA_TRAITS_HH__
153