1892SN/A/*
21762SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
3892SN/A * All rights reserved.
4892SN/A *
5892SN/A * Redistribution and use in source and binary forms, with or without
6892SN/A * modification, are permitted provided that the following conditions are
7892SN/A * met: redistributions of source code must retain the above copyright
8892SN/A * notice, this list of conditions and the following disclaimer;
9892SN/A * redistributions in binary form must reproduce the above copyright
10892SN/A * notice, this list of conditions and the following disclaimer in the
11892SN/A * documentation and/or other materials provided with the distribution;
12892SN/A * neither the name of the copyright holders nor the names of its
13892SN/A * contributors may be used to endorse or promote products derived from
14892SN/A * this software without specific prior written permission.
15892SN/A *
16892SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17892SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18892SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19892SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20892SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21892SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22892SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23892SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24892SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25892SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26892SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272665SN/A *
282665SN/A * Authors: Ali Saidi
29892SN/A */
30767SN/A
311730SN/A/** @file
321730SN/A * List of Tsunami CSRs
331730SN/A */
341730SN/A
35767SN/A#ifndef __TSUNAMIREG_H__
36767SN/A#define __TSUNAMIREG_H__
37767SN/A
38892SN/A#define ALPHA_K0SEG_BASE  ULL(0xfffffc0000000000)
39801SN/A
40768SN/A// CChip Registers
41767SN/A#define TSDEV_CC_CSR    0x00
42767SN/A#define TSDEV_CC_MTR    0x01
43767SN/A#define TSDEV_CC_MISC   0x02
44767SN/A
45767SN/A#define TSDEV_CC_AAR0   0x04
46767SN/A#define TSDEV_CC_AAR1   0x05
47767SN/A#define TSDEV_CC_AAR2   0x06
48767SN/A#define TSDEV_CC_AAR3   0x07
49767SN/A#define TSDEV_CC_DIM0   0x08
50767SN/A#define TSDEV_CC_DIM1   0x09
51767SN/A#define TSDEV_CC_DIR0   0x0A
52767SN/A#define TSDEV_CC_DIR1   0x0B
53767SN/A#define TSDEV_CC_DRIR   0x0C
54767SN/A#define TSDEV_CC_PRBEN  0x0D
55767SN/A#define TSDEV_CC_IIC0   0x0E
56767SN/A#define TSDEV_CC_IIC1   0x0F
57767SN/A#define TSDEV_CC_MPR0   0x10
58767SN/A#define TSDEV_CC_MPR1   0x11
59767SN/A#define TSDEV_CC_MPR2   0x12
60767SN/A#define TSDEV_CC_MPR3   0x13
61767SN/A
62767SN/A#define TSDEV_CC_DIM2   0x18
63767SN/A#define TSDEV_CC_DIM3   0x19
64767SN/A#define TSDEV_CC_DIR2   0x1A
65767SN/A#define TSDEV_CC_DIR3   0x1B
66767SN/A#define TSDEV_CC_IIC2   0x1C
67767SN/A#define TSDEV_CC_IIC3   0x1D
68767SN/A
691290SN/A// BigTsunami Registers
701290SN/A#define TSDEV_CC_BDIMS  0x1000000
711290SN/A#define TSDEV_CC_BDIRS  0x2000000
721290SN/A#define TSDEV_CC_IPIQ   0x20  //0xf01a000800
731290SN/A#define TSDEV_CC_IPIR   0x21  //0xf01a000840
741290SN/A#define TSDEV_CC_ITIR   0x22  //0xf01a000880
751290SN/A
76768SN/A
77768SN/A// PChip Registers
78768SN/A#define TSDEV_PC_WSBA0      0x00
79768SN/A#define TSDEV_PC_WSBA1      0x01
80768SN/A#define TSDEV_PC_WSBA2      0x02
81768SN/A#define TSDEV_PC_WSBA3      0x03
82768SN/A#define TSDEV_PC_WSM0       0x04
83768SN/A#define TSDEV_PC_WSM1       0x05
84768SN/A#define TSDEV_PC_WSM2       0x06
85768SN/A#define TSDEV_PC_WSM3       0x07
86768SN/A#define TSDEV_PC_TBA0       0x08
87768SN/A#define TSDEV_PC_TBA1       0x09
88768SN/A#define TSDEV_PC_TBA2       0x0A
89768SN/A#define TSDEV_PC_TBA3       0x0B
90768SN/A#define TSDEV_PC_PCTL       0x0C
91768SN/A#define TSDEV_PC_PLAT       0x0D
92768SN/A#define TSDEV_PC_RES        0x0E
93768SN/A#define TSDEV_PC_PERROR     0x0F
94768SN/A#define TSDEV_PC_PERRMASK   0x10
95768SN/A#define TSDEV_PC_PERRSET    0x11
96768SN/A#define TSDEV_PC_TLBIV      0x12
97768SN/A#define TSDEV_PC_TLBIA      0x13
98768SN/A#define TSDEV_PC_PMONCTL    0x14
99768SN/A#define TSDEV_PC_PMONCNT    0x15
100768SN/A
101768SN/A#define TSDEV_PC_SPST       0x20
102768SN/A
103768SN/A
104768SN/A// DChip Registers
105768SN/A#define TSDEV_DC_DSC        0x20
106768SN/A#define TSDEV_DC_STR        0x21
107768SN/A#define TSDEV_DC_DREV       0x22
108768SN/A#define TSDEV_DC_DSC2       0x23
109768SN/A
110769SN/A// I/O Ports
111769SN/A#define TSDEV_PIC1_MASK     0x21
112769SN/A#define TSDEV_PIC2_MASK     0xA1
113865SN/A#define TSDEV_PIC1_ISR      0x20
114865SN/A#define TSDEV_PIC2_ISR      0xA0
115865SN/A#define TSDEV_PIC1_ACK      0x20
116865SN/A#define TSDEV_PIC2_ACK      0xA0
117769SN/A#define TSDEV_DMA1_RESET    0x0D
118769SN/A#define TSDEV_DMA2_RESET    0xDA
119769SN/A#define TSDEV_DMA1_MODE     0x0B
120769SN/A#define TSDEV_DMA2_MODE     0xD6
121769SN/A#define TSDEV_DMA1_MASK     0x0A
122769SN/A#define TSDEV_DMA2_MASK     0xD4
1231817SN/A#define TSDEV_CTRL_PORTB    0x61
1241817SN/A#define TSDEV_TMR0_DATA     0x40
1251817SN/A#define TSDEV_TMR1_DATA     0x41
126771SN/A#define TSDEV_TMR2_DATA     0x42
1271817SN/A#define TSDEV_TMR_CTRL      0x43
1281817SN/A#define TSDEV_KBD           0x64
1291817SN/A#define TSDEV_DMA1_CMND     0x08
1301817SN/A#define TSDEV_DMA1_STAT     TSDEV_DMA1_CMND
1311817SN/A#define TSDEV_DMA2_CMND     0xD0
1321817SN/A#define TSDEV_DMA2_STAT     TSDEV_DMA2_CMND
1331817SN/A#define TSDEV_DMA1_MMASK    0x0F
1341817SN/A#define TSDEV_DMA2_MMASK    0xDE
135773SN/A
1361781SN/A/* Added for keyboard accesses */
1371781SN/A#define TSDEV_KBD           0x64
1381781SN/A
139773SN/A#define TSDEV_RTC_ADDR      0x70
140773SN/A#define TSDEV_RTC_DATA      0x71
141773SN/A
142909SN/A#define PCHIP_PCI0_MEMORY       ULL(0x00000000000)
143909SN/A#define PCHIP_PCI0_IO           ULL(0x001FC000000)
144909SN/A#define TSUNAMI_UNCACHABLE_BIT  ULL(0x80000000000)
145909SN/A#define TSUNAMI_PCI0_MEMORY     TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_MEMORY
146909SN/A#define TSUNAMI_PCI0_IO         TSUNAMI_UNCACHABLE_BIT + PCHIP_PCI0_IO
147801SN/A
148773SN/A
1491817SN/A// System Control PortB Status Bits
1501817SN/A#define PORTB_SPKR_HIGH 0x20
1511817SN/A
152767SN/A#endif // __TSUNAMIREG_H__
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