Searched refs:NumVecElemPerVecReg (Results 1 - 18 of 18) sorted by relevance
| /gem5/src/arch/arm/ |
| H A D | registers.hh | 68 constexpr unsigned NumVecElemPerVecReg = MaxSveVecLenInWords; member in namespace:ArmISA
71 using VecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, false>;
72 using ConstVecReg = ::VecRegT<VecElem, NumVecElemPerVecReg, true>;
75 using VecPredReg = ::VecPredRegT<VecElem, NumVecElemPerVecReg,
77 using ConstVecPredReg = ::VecPredRegT<VecElem, NumVecElemPerVecReg,
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| H A D | utility.cc | 160 for (auto elem_idx = 0; elem_idx < NumVecElemPerVecReg; elem_idx++)
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| /gem5/src/arch/null/ |
| H A D | registers.hh | 57 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg; member in namespace:NullISA
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| /gem5/src/arch/sparc/ |
| H A D | registers.hh | 54 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg; member in namespace:SparcISA
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| /gem5/src/cpu/o3/ |
| H A D | regfile.cc | 67 NumVecElemPerVecReg),
73 + _numPhysicalVecRegs * NumVecElemPerVecReg
109 for (ElemIndex eIdx = 0; eIdx < NumVecElemPerVecReg; eIdx++) {
157 for (ElemIndex elemIdx = 0; elemIdx < NumVecElemPerVecReg; elemIdx++) {
158 assert(vecElemIds[reg_idx * NumVecElemPerVecReg +
160 assert(vecElemIds[reg_idx * NumVecElemPerVecReg +
194 vecElemIds.begin() + idx * NumVecElemPerVecReg,
195 vecElemIds.begin() + (idx+1) * NumVecElemPerVecReg);
230 return &vecElemIds[reg->index() * NumVecElemPerVecReg +
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| H A D | regfile.hh | 76 static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg; member in class:PhysRegFile
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| H A D | rename_map.cc | 162 TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg,
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| H A D | dyn_inst.hh | 71 static constexpr auto NumVecElemPerVecReg = TheISA::NumVecElemPerVecReg; member in class:BaseO3DynInst
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| H A D | rename_map.hh | 173 static constexpr uint32_t NVecElems = TheISA::NumVecElemPerVecReg;
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| H A D | inst_queue_impl.hh | 106 params->numPhysVecRegs * TheISA::NumVecElemPerVecReg +
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| H A D | cpu.cc | 273 for (ElemIndex ldx = 0; ldx < TheISA::NumVecElemPerVecReg;
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| /gem5/src/arch/power/ |
| H A D | registers.hh | 54 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg; member in namespace:PowerISA
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| /gem5/src/arch/x86/ |
| H A D | registers.hh | 104 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg; member in namespace:X86ISA
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| /gem5/src/arch/alpha/ |
| H A D | registers.hh | 54 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg; member in namespace:AlphaISA
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| /gem5/src/cpu/minor/ |
| H A D | scoreboard.hh | 98 (TheISA::NumVecRegs * TheISA::NumVecElemPerVecReg) +
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| /gem5/src/arch/mips/ |
| H A D | registers.hh | 291 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg; member in namespace:MipsISA
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| /gem5/src/cpu/ |
| H A D | reg_class.hh | 85 static constexpr size_t Scale = TheISA::NumVecElemPerVecReg;
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| /gem5/src/arch/riscv/ |
| H A D | registers.hh | 77 constexpr unsigned NumVecElemPerVecReg = ::DummyNumVecElemPerVecReg; member in namespace:RiscvISA
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