Searched refs:NumMiscRegs (Results 1 - 20 of 20) sorted by relevance

/gem5/src/arch/x86/
H A Dregisters.hh57 const int NumMiscRegs = NUM_MISCREGS; member in namespace:X86ISA
78 Max_Reg_Index = Misc_Reg_Base + NumMiscRegs
H A Disa.cc110 memset(regVal, 0, NumMiscRegs * sizeof(RegVal));
400 SERIALIZE_ARRAY(regVal, NumMiscRegs);
406 UNSERIALIZE_ARRAY(regVal, NumMiscRegs);
/gem5/src/arch/sparc/
H A Dregisters.hh83 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
H A Dmiscregs.hh158 const int NumMiscRegs = MISCREG_NUMMISCREGS; member in namespace:SparcISA
H A Dua2005.cc74 static string miscRegName[NumMiscRegs] =
/gem5/src/arch/alpha/
H A Dregisters.hh100 const int NumMiscRegs = NUM_MISCREGS; member in namespace:AlphaISA
103 NumIntRegs + NumFloatRegs + NumMiscRegs;
/gem5/src/arch/arm/
H A Dregisters.hh100 const int NumMiscRegs = NUM_MISCREGS; member in namespace:ArmISA
109 NumVecPredRegs + NumMiscRegs;
H A Dutility.cc178 for (int i = 0; i < NumMiscRegs; i++)
H A Disa.hh377 RegVal miscRegs[NumMiscRegs];
H A Disa.cc430 assert(misc_reg < NumMiscRegs);
755 assert(misc_reg < NumMiscRegs);
/gem5/src/arch/power/
H A Dregisters.hh81 const int NumMiscRegs = NUM_MISCREGS; member in namespace:PowerISA
H A Disa.hh54 RegVal miscRegs[NumMiscRegs];
/gem5/src/arch/riscv/
H A Disa.cc50 miscRegFile.resize(NumMiscRegs);
101 if (misc_reg > NumMiscRegs || misc_reg < 0) {
171 if (misc_reg > NumMiscRegs || misc_reg < 0) {
H A Dregisters.hh264 const int NumMiscRegs = NUM_MISCREGS; member in namespace:RiscvISA
/gem5/src/arch/mips/
H A Dregisters.hh282 const int NumMiscRegs = MISCREG_NUMREGS; member in namespace:MipsISA
284 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
H A Disa.hh129 static std::string miscRegNames[NumMiscRegs];
H A Disa.cc46 ISA::miscRegNames[NumMiscRegs] =
95 miscRegFile.resize(NumMiscRegs);
96 bankType.resize(NumMiscRegs);
98 for (int i=0; i < NumMiscRegs; i++) {
103 miscRegFile_WriteMask.resize(NumMiscRegs);
105 for (int i = 0; i < NumMiscRegs; i++) {
154 for (int i = 0; i < NumMiscRegs; i++) {
H A Dutility.cc256 for (int i = 0; i < NumMiscRegs; i++)
/gem5/src/cpu/o3/
H A Dregfile.cc128 for (phys_reg = 0; phys_reg < TheISA::NumMiscRegs; phys_reg++) {
/gem5/src/cpu/
H A Dthread_context.cc101 for (int i = 0; i < TheISA::NumMiscRegs; ++i) {

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