Searched refs:NumIntRegs (Results 1 - 23 of 23) sorted by relevance

/gem5/src/arch/alpha/
H A Dregredir.cc37 const int reg_redir[NumIntRegs] = {
H A Dregredir.hh39 extern const int reg_redir[NumIntRegs];
H A Dregisters.hh93 const int NumIntRegs = NumIntArchRegs + NumPALShadowRegs; member in namespace:AlphaISA
103 NumIntRegs + NumFloatRegs + NumMiscRegs;
H A Dutility.cc68 for (int i = 0; i < NumIntRegs; ++i)
/gem5/src/arch/sparc/
H A Dregisters.hh76 const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs; member in namespace:SparcISA
83 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
H A Disa.hh215 assert(flatIndex < NumIntRegs);
H A Disa.cc96 assert(offset >= 0 && offset + NumWindowedRegs <= NumIntRegs);
106 assert(offset >= 0 && offset + NumGlobalRegs <= NumIntRegs);
/gem5/src/arch/power/
H A Dregisters.hh74 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; member in namespace:PowerISA
94 const int ZeroReg = NumIntRegs - 1;
H A Dutility.cc45 for (int i = 0; i < NumIntRegs; ++i)
/gem5/src/arch/arm/
H A Dregisters.hh92 const int NumIntRegs = NUM_INTREGS; member in namespace:ArmISA
108 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs +
H A Dutility.cc169 for (int i = 0; i < NumIntRegs; i++)
/gem5/src/cpu/
H A Dthread_context.cc64 for (int i = 0; i < TheISA::NumIntRegs; ++i) {
189 RegVal intRegs[NumIntRegs];
190 for (int i = 0; i < NumIntRegs; ++i)
192 SERIALIZE_ARRAY(intRegs, NumIntRegs);
230 RegVal intRegs[NumIntRegs];
231 UNSERIALIZE_ARRAY(intRegs, NumIntRegs);
232 for (int i = 0; i < NumIntRegs; ++i)
H A Dsimple_thread.hh107 RegVal intRegs[TheISA::NumIntRegs];
288 assert(flatIndex < TheISA::NumIntRegs);
462 assert(flatIndex < TheISA::NumIntRegs);
/gem5/src/arch/x86/
H A Dregisters.hh60 const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs + NumImplicitIntRegs; member in namespace:X86ISA
H A Dutility.cc238 for (int i = 0; i < NumIntRegs; ++i)
/gem5/src/cpu/minor/
H A Dscoreboard.cc66 scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs +
71 scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs +
76 scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs +
81 scoreboard_index = TheISA::NumIntRegs + TheISA::NumCCRegs +
86 scoreboard_index = TheISA::NumIntRegs + reg.index();
H A Dscoreboard.hh64 * together with integer regs in the range [0,NumIntRegs-1],
65 * CC regs in the range [NumIntRegs, NumIntRegs+NumCCRegs-1]
67 * [NumIntRegs+NumCCRegs, NumFloatRegs+NumIntRegs+NumCCRegs-1] */
96 numRegs(TheISA::NumIntRegs + TheISA::NumCCRegs +
/gem5/src/arch/mips/
H A Dregisters.hh57 const int NumIntRegs = NumIntArchRegs + NumIntSpecialRegs; //HI & LO Regs member in namespace:MipsISA
284 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
H A Dutility.cc245 for (int i = 0; i < NumIntRegs; i++)
/gem5/src/arch/riscv/
H A Dutility.hh129 for (int i = 0; i < NumIntRegs; ++i)
H A Dregisters.hh89 const int NumIntRegs = NumIntArchRegs + NumMicroIntRegs; member in namespace:RiscvISA
/gem5/src/cpu/o3/
H A Drename_map.cc121 intMap.init(TheISA::NumIntRegs, &(freeList->intList), _intZeroReg);
H A Dcpu.cc212 assert(params->numPhysIntRegs >= numThreads * TheISA::NumIntRegs);
244 for (RegIndex ridx = 0; ridx < TheISA::NumIntRegs; ++ridx) {
785 for (RegId reg_id(IntRegClass, 0); reg_id.index() < TheISA::NumIntRegs;

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