Searched refs:NumFloatRegs (Results 1 - 20 of 20) sorted by relevance

/gem5/src/arch/sparc/
H A Dsparc_traits.hh50 const int NumFloatRegs = 64; member in namespace:SparcISA
51 const int NumFloatArchRegs = NumFloatRegs;
H A Dregisters.hh83 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
/gem5/src/arch/x86/
H A Dregisters.hh67 const int NumFloatRegs = member in namespace:X86ISA
76 CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
H A Dutility.cc241 for (int i = 0; i < NumFloatRegs; ++i)
/gem5/src/arch/power/
H A Dutility.cc49 for (int i = 0; i < NumFloatRegs; ++i)
H A Dregisters.hh75 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; member in namespace:PowerISA
/gem5/src/arch/alpha/
H A Dregisters.hh94 const int NumFloatRegs = NumFloatArchRegs; member in namespace:AlphaISA
103 NumIntRegs + NumFloatRegs + NumMiscRegs;
H A Dutility.cc72 for (int i = 0; i < NumFloatRegs; ++i)
/gem5/src/arch/arm/
H A Dregisters.hh93 const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs; member in namespace:ArmISA
108 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs +
H A Dutility.cc172 for (int i = 0; i < NumFloatRegs; i++)
/gem5/src/cpu/
H A Dthread_context.cc73 for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
170 RegVal floatRegs[NumFloatRegs];
171 for (int i = 0; i < NumFloatRegs; ++i)
175 arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs);
211 RegVal floatRegs[NumFloatRegs];
214 arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs);
215 for (int i = 0; i < NumFloatRegs; ++i)
H A Dsimple_thread.hh106 RegVal floatRegs[TheISA::NumFloatRegs];
299 assert(flatIndex < TheISA::NumFloatRegs);
472 assert(flatIndex < TheISA::NumFloatRegs);
475 if (flatIndex < TheISA::NumFloatRegs)
/gem5/src/arch/mips/
H A Dregisters.hh58 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// member in namespace:MipsISA
284 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
H A Dutility.cc249 for (int i = 0; i < NumFloatRegs; i++)
/gem5/src/cpu/minor/
H A Dscoreboard.hh67 * [NumIntRegs+NumCCRegs, NumFloatRegs+NumIntRegs+NumCCRegs-1] */
97 TheISA::NumFloatRegs +
H A Dscoreboard.cc72 TheISA::NumFloatRegs + reg.index();
77 TheISA::NumFloatRegs + reg.flatIndex();
82 TheISA::NumFloatRegs + TheISA::NumVecRegs + reg.index();
/gem5/src/arch/riscv/
H A Dutility.hh156 if (reg.index() >= NumFloatRegs) {
H A Dregisters.hh90 const int NumFloatRegs = 32; member in namespace:RiscvISA
/gem5/src/cpu/o3/
H A Drename_map.cc123 floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg);
H A Dcpu.cc213 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs);
229 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1;
252 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) {
793 for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs;

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