Searched refs:NumFloatRegs (Results 1 - 20 of 20) sorted by relevance
/gem5/src/arch/sparc/ |
H A D | sparc_traits.hh | 50 const int NumFloatRegs = 64; member in namespace:SparcISA 51 const int NumFloatArchRegs = NumFloatRegs;
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H A D | registers.hh | 83 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
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/gem5/src/arch/x86/ |
H A D | registers.hh | 67 const int NumFloatRegs = member in namespace:X86ISA 76 CC_Reg_Base = FP_Reg_Base + NumFloatRegs,
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H A D | utility.cc | 241 for (int i = 0; i < NumFloatRegs; ++i)
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/gem5/src/arch/power/ |
H A D | utility.cc | 49 for (int i = 0; i < NumFloatRegs; ++i)
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H A D | registers.hh | 75 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs; member in namespace:PowerISA
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/gem5/src/arch/alpha/ |
H A D | registers.hh | 94 const int NumFloatRegs = NumFloatArchRegs; member in namespace:AlphaISA 103 NumIntRegs + NumFloatRegs + NumMiscRegs;
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H A D | utility.cc | 72 for (int i = 0; i < NumFloatRegs; ++i)
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/gem5/src/arch/arm/ |
H A D | registers.hh | 93 const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs; member in namespace:ArmISA 108 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumVecRegs +
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H A D | utility.cc | 172 for (int i = 0; i < NumFloatRegs; i++)
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/gem5/src/cpu/ |
H A D | thread_context.cc | 73 for (int i = 0; i < TheISA::NumFloatRegs; ++i) { 170 RegVal floatRegs[NumFloatRegs]; 171 for (int i = 0; i < NumFloatRegs; ++i) 175 arrayParamOut(cp, "floatRegs.i", floatRegs, NumFloatRegs); 211 RegVal floatRegs[NumFloatRegs]; 214 arrayParamIn(cp, "floatRegs.i", floatRegs, NumFloatRegs); 215 for (int i = 0; i < NumFloatRegs; ++i)
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H A D | simple_thread.hh | 106 RegVal floatRegs[TheISA::NumFloatRegs]; 299 assert(flatIndex < TheISA::NumFloatRegs); 472 assert(flatIndex < TheISA::NumFloatRegs); 475 if (flatIndex < TheISA::NumFloatRegs)
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/gem5/src/arch/mips/ |
H A D | registers.hh | 58 const int NumFloatRegs = NumFloatArchRegs + NumFloatSpecialRegs;// member in namespace:MipsISA 284 const int TotalNumRegs = NumIntRegs + NumFloatRegs + NumMiscRegs;
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H A D | utility.cc | 249 for (int i = 0; i < NumFloatRegs; i++)
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/gem5/src/cpu/minor/ |
H A D | scoreboard.hh | 67 * [NumIntRegs+NumCCRegs, NumFloatRegs+NumIntRegs+NumCCRegs-1] */ 97 TheISA::NumFloatRegs +
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H A D | scoreboard.cc | 72 TheISA::NumFloatRegs + reg.index(); 77 TheISA::NumFloatRegs + reg.flatIndex(); 82 TheISA::NumFloatRegs + TheISA::NumVecRegs + reg.index();
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/gem5/src/arch/riscv/ |
H A D | utility.hh | 156 if (reg.index() >= NumFloatRegs) {
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H A D | registers.hh | 90 const int NumFloatRegs = 32; member in namespace:RiscvISA
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/gem5/src/cpu/o3/ |
H A D | rename_map.cc | 123 floatMap.init(TheISA::NumFloatRegs, &(freeList->floatList), _floatZeroReg);
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H A D | cpu.cc | 213 assert(params->numPhysFloatRegs >= numThreads * TheISA::NumFloatRegs); 229 RegIndex invalidFPReg = TheISA::NumFloatRegs + 1; 252 for (RegIndex ridx = 0; ridx < TheISA::NumFloatRegs; ++ridx) { 793 for (RegId reg_id(FloatRegClass, 0); reg_id.index() < TheISA::NumFloatRegs;
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