| /gem5/src/arch/arm/ |
| H A D | microcode_rom.hh | 36 namespace ArmISA namespace
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| H A D | mmapped_ipr.hh | 46 namespace ArmISA namespace
50 } // namespace ArmISA
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| H A D | pseudo_inst.hh | 39 namespace ArmISA { namespace
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| H A D | kernel_stats.hh | 36 namespace ArmISA { namespace
46 } // namespace ArmISA::Kernel
47 } // namespace ArmISA
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| H A D | vtophys.cc | 59 using namespace ArmISA;
62 ArmISA::vtophys(Addr vaddr)
74 ArmISA::TLB *tlb;
83 tlb = static_cast<ArmISA::TLB*>(tc->getDTBPtr());
88 tlb = static_cast<ArmISA::TLB*>(tc->getITBPtr());
97 ArmISA::vtophys(ThreadContext *tc, Addr addr)
108 ArmISA::virtvalid(ThreadContext *tc, Addr vaddr)
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| H A D | ccregs.hh | 42 namespace ArmISA namespace
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| H A D | vtophys.hh | 42 namespace ArmISA { namespace
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| H A D | isa_traits.hh | 54 namespace ArmISA namespace
88 inline Addr VAddrVPN(Addr a) { return a >> ArmISA::PageShift; }
89 inline Addr VAddrOffset(Addr a) { return a & ArmISA::PageOffset; }
117 } // namespace ArmISA
119 using namespace ArmISA;
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| H A D | isa_device.cc | 44 namespace ArmISA namespace
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| H A D | decoder.hh | 55 namespace ArmISA namespace
129 * decode(ArmISA::PCState).
162 StaticInstPtr decode(ArmISA::PCState &pc);
213 } // namespace ArmISA
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| H A D | isa_device.hh | 48 namespace ArmISA namespace
56 * This class provides a well-defined interface that the ArmISA class
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| H A D | stacktrace.hh | 39 namespace ArmISA namespace
66 typedef ArmISA::MachInst MachInst;
121 } // Namespace ArmISA
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| H A D | stage2_mmu.cc | 49 using namespace ArmISA;
145 ArmISA::Stage2MMU *
148 return new ArmISA::Stage2MMU(this);
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| H A D | interrupts.cc | 44 ArmISA::Interrupts *
47 return new ArmISA::Interrupts(this);
51 ArmISA::Interrupts::takeInt(ThreadContext *tc, InterruptTypes int_type) const
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| /gem5/src/arch/arm/tracers/ |
| H A D | tarmac_base.hh | 88 ArmISA::PCState pc,
94 ArmISA::MachInst opcode;
97 ArmISA::OperatingMode mode;
104 RegEntry(ArmISA::PCState pc);
126 const StaticInstPtr _staticInst, ArmISA::PCState _pc,
138 static ISetState pcToISetState(ArmISA::PCState pc);
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| H A D | tarmac_tracer.hh | 66 ArmISA::PCState _pc)
75 ArmISA::PCState pc;
102 ArmISA::PCState pc,
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| H A D | tarmac_parser.hh | 86 ArmISA::PCState pc;
98 ArmISA::PCState _pc,
133 ArmISA::PCState pc);
136 const StaticInstPtr _staticInst, ArmISA::PCState _pc,
244 ArmISA::PCState pc,
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| H A D | tarmac_record.hh | 79 opModeToStr(ArmISA::OperatingMode opMode);
181 const StaticInstPtr _staticInst, ArmISA::PCState _pc,
233 (reg->regRel == ArmISA::MISCREG_CPSR);
243 RegId reg(MiscRegClass, ArmISA::MISCREG_CPSR);
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| H A D | tarmac_tracer.cc | 78 ArmISA::PCState pc,
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| /gem5/src/arch/arm/insts/ |
| H A D | branch64.cc | 42 namespace ArmISA namespace
45 ArmISA::PCState
46 BranchImm64::branchTarget(const ArmISA::PCState &branchPC) const
48 ArmISA::PCState pcs = branchPC;
54 ArmISA::PCState
55 BranchImmReg64::branchTarget(const ArmISA::PCState &branchPC) const
57 ArmISA::PCState pcs = branchPC;
63 ArmISA::PCState
64 BranchImmImmReg64::branchTarget(const ArmISA::PCState &branchPC) const
66 ArmISA
[all...] |
| H A D | sve_mem.hh | 46 namespace ArmISA namespace
66 memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
91 memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
117 memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
143 memAccessFlags(ArmISA::TLB::AllowUnaligned | ArmISA::TLB::MustBeOne)
151 } // namespace ArmISA
[all...] |
| H A D | branch64.hh | 44 namespace ArmISA namespace
58 ArmISA::PCState branchTarget(
59 const ArmISA::PCState &branchPC) const override;
138 ArmISA::PCState branchTarget(
139 const ArmISA::PCState &branchPC) const override;
164 ArmISA::PCState branchTarget(
165 const ArmISA::PCState &branchPC) const override;
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| H A D | mult.hh | 45 namespace ArmISA namespace
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| H A D | branch.cc | 44 namespace ArmISA { namespace
75 } // namespace ArmISA
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| /gem5/src/arch/arm/kvm/ |
| H A D | arm_cpu.hh | 107 ArmISA::MiscRegIndex decodeCoProcReg(uint64_t id) const;
109 ArmISA::MiscRegIndex decodeVFPCtrlReg(uint64_t id) const;
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