1/*
2 * Copyright (c) 2017-2018 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Giacomo Travaglini
38 */
39
40/**
41 * @file: This file declares the interface of the Tarmac Tracer:
42 *        the tracer based on the Tarmac specification.
43 */
44
45#ifndef __ARCH_ARM_TRACERS_TARMAC_TRACER_HH__
46#define __ARCH_ARM_TRACERS_TARMAC_TRACER_HH__
47
48#include "arch/arm/tracers/tarmac_record.hh"
49#include "arch/arm/tracers/tarmac_record_v8.hh"
50#include "params/TarmacTracer.hh"
51#include "sim/insttracer.hh"
52
53class ThreadContext;
54
55namespace Trace {
56
57/**
58 * This object type is encapsulating the informations needed by
59 * a Tarmac record to generate it's own entries.
60 */
61class TarmacContext
62{
63  public:
64    TarmacContext(ThreadContext* _thread,
65                  const StaticInstPtr _staticInst,
66                  ArmISA::PCState _pc)
67      : thread(_thread), staticInst(_staticInst), pc(_pc)
68    {}
69
70    std::string tarmacCpuName() const;
71
72  public:
73    ThreadContext* thread;
74    const StaticInstPtr staticInst;
75    ArmISA::PCState pc;
76};
77
78/**
79 * Tarmac Tracer: this tracer generates a new Tarmac Record for
80 * every instruction being executed in gem5.
81 * The record is made by a collection of entries which are stored
82 * in the tracer queues.
83 */
84class TarmacTracer : public InstTracer
85{
86    friend class TarmacTracerRecord;
87    friend class TarmacTracerRecordV8;
88
89  public:
90    typedef TarmacTracerParams Params;
91
92    TarmacTracer(const Params *p);
93
94    /**
95     * Generates a TarmacTracerRecord, depending on the Tarmac version.
96     * At the moment supported formats are:
97     * - Tarmac
98     * - TarmacV8
99     */
100    InstRecord* getInstRecord(Tick when, ThreadContext *tc,
101                              const StaticInstPtr staticInst,
102                              ArmISA::PCState pc,
103                              const StaticInstPtr macroStaticInst = NULL);
104
105  protected:
106    typedef std::unique_ptr<Printable> PEntryPtr;
107    typedef TarmacTracerRecord::InstPtr InstPtr;
108    typedef TarmacTracerRecord::MemPtr MemPtr;
109    typedef TarmacTracerRecord::RegPtr RegPtr;
110
111    /**
112     * startTick and endTick allow to trace a specific window of ticks
113     * rather than the entire CPU execution.
114     */
115    Tick startTick;
116    Tick endTick;
117
118    /**
119     * Collection of heterogeneous printable entries: could be
120     * representing either instructions, register or memory entries.
121     * When dealing with MacroInstructions the following separate queues
122     * will be used. micro-instruction entries will be buffered and
123     * dumped to the tracefile only at the end of the Macro.
124     */
125    std::vector<InstPtr> instQueue;
126    std::vector<MemPtr> memQueue;
127    std::vector<RegPtr> regQueue;
128};
129
130} // namespace Trace
131
132#endif // __ARCH_ARM_TRACERS_TARMAC_TRACER_HH__
133