Searched refs:readMiscRegNoEffect (Results 51 - 74 of 74) sorted by relevance

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/gem5/src/cpu/o3/
H A Dthread_context.hh385 readMiscRegNoEffect(RegIndex misc_reg) const override
387 return cpu->readMiscRegNoEffect(misc_reg, thread->threadId());
H A Dcpu.hh340 RegVal readMiscRegNoEffect(int misc_reg, ThreadID tid) const;
H A Dcpu.cc1169 FullO3CPU<Impl>::readMiscRegNoEffect(int misc_reg, ThreadID tid) const function in class:FullO3CPU
1171 return this->isa[tid]->readMiscRegNoEffect(misc_reg);
/gem5/src/arch/arm/
H A Disa.hh443 RegVal readMiscRegNoEffect(int misc_reg) const;
602 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
618 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
H A Dnativetrace.cc134 newState[STATE_FPSCR] = tc->readMiscRegNoEffect(MISCREG_FPSCR) |
H A Dutility.hh129 return inUserMode(tc->readMiscRegNoEffect(MISCREG_CPSR));
H A Dpmu.cc500 const SCR scr(pmu.isa->readMiscRegNoEffect(MISCREG_SCR));
501 const CPSR cpsr(pmu.isa->readMiscRegNoEffect(MISCREG_CPSR));
H A Dutility.cc179 dest->setMiscRegNoEffect(i, src->readMiscRegNoEffect(i));
185 dest->setMiscReg(MISCREG_CPSR, src->readMiscRegNoEffect(MISCREG_CPSR));
/gem5/src/cpu/checker/
H A Dthread_context.hh425 readMiscRegNoEffect(RegIndex misc_reg) const override
427 return actualTC->readMiscRegNoEffect(misc_reg);
H A Dcpu.hh455 readMiscRegNoEffect(int misc_reg) const function in class:CheckerCPU
457 return thread->readMiscRegNoEffect(misc_reg);
/gem5/src/cpu/minor/
H A Dexec_context.hh356 readMiscRegNoEffect(int misc_reg) const function in class:Minor::ExecContext
358 return thread.readMiscRegNoEffect(misc_reg);
/gem5/src/arch/mips/
H A Dfaults.hh183 CauseReg cause = tc->readMiscRegNoEffect(MISCREG_CAUSE);
/gem5/src/arch/alpha/
H A Dkernel_stats.cc186 Addr pcbb = tc->readMiscRegNoEffect(IPR_PALtemp23);
/gem5/src/cpu/
H A Dthread_context.hh286 virtual RegVal readMiscRegNoEffect(RegIndex misc_reg) const = 0;
H A Dsimple_thread.hh541 readMiscRegNoEffect(RegIndex misc_reg) const override
543 return isa->readMiscRegNoEffect(misc_reg);
/gem5/src/arch/sparc/
H A Disa.cc177 ISA::readMiscRegNoEffect(int miscReg) const function in class:SparcISA::ISA
382 return readMiscRegNoEffect(miscReg);
H A Dprocess.cc539 PSTATE pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
H A Dtlb.cc421 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
539 uint64_t tlbdata = tc->readMiscRegNoEffect(MISCREG_TLB_DATA);
/gem5/src/arch/arm/kvm/
H A Darm_cpu.cc536 const unsigned m5_ne(tc->readMiscRegNoEffect(idx));
544 inform("readMiscReg: %x, readMiscRegNoEffect: %x\n",
678 setOneReg(id, tc->readMiscRegNoEffect(reg));
743 tc->setMiscReg(MISCREG_CPSR, tc->readMiscRegNoEffect(MISCREG_CPSR));
/gem5/src/arch/arm/insts/
H A Dstatic_inst.cc634 const HDCR mdcr = tc->readMiscRegNoEffect(MISCREG_MDCR_EL2);
907 setend_disabled = ((SCTLR)tc->readMiscRegNoEffect(MISCREG_HSCTLR)).sed;
925 setend_disabled = ((SCTLR)tc->readMiscRegNoEffect(banked_sctlr)).sed;
/gem5/src/arch/arm/tracers/
H A Dtarmac_parser.cc685 CPSR cpsr = thread->readMiscRegNoEffect(it->index);
698 value_lo = thread->readMiscRegNoEffect(it->index);
/gem5/src/arch/x86/linux/
H A Dprocess.cc137 fsBase = tc->readMiscRegNoEffect(MISCREG_FS_BASE);
145 gsBase = tc->readMiscRegNoEffect(MISCREG_GS_BASE);
/gem5/src/arch/x86/
H A Dinterrupts.cc623 RFLAGS rflags = tc->readMiscRegNoEffect(MISCREG_RFLAGS);
/gem5/src/base/
H A Dcp_annotate.cc154 return (tc->readMiscRegNoEffect(TheISA::IPR_PALtemp23) &

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