#
14271:edb5f954d6ad |
|
11-Sep-2019 |
Gabe Black <gabeblack@google.com> |
sparc: Fix a warning/error in tlb.cc.
gcc has started to not like memseting an ojbect to zero in some cases. Cast the TlbEntry pointer to a void * before memsetting it to placate gcc.
Change-Id: Iccb3c326fdb82f1f111329ff1a80bb6719cace47 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20830 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
|
#
13912:53531772924f |
|
29-Apr-2019 |
Gabe Black <gabeblack@google.com> |
sparc: Move the interrupt types out of isa_traits.hh into interrupts.hh.
Those types aren't generic or used outside of SPARC.
Change-Id: I9bb154920a9625f12388c3d295dc933ab51fadde Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18469 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> Tested-by: kokoro <noreply+kokoro@google.com>
|
#
13231:c6c133f9e007 |
|
12-Oct-2018 |
Gabe Black <gabeblack@google.com> |
sparc: Use big endian packet accessors.
We know data is big endian, so we can use those accessors explicitly.
Change-Id: I06fe35254433b20db05f5f10d0ca29a44d47c301 Reviewed-on: https://gem5-review.googlesource.com/c/13458 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
|
#
12749:223c83ed9979 |
|
04-Jun-2018 |
Giacomo Travaglini <giacomo.travaglini@arm.com> |
misc: Using smart pointers for memory Requests
This patch is changing the underlying type for RequestPtr from Request* to shared_ptr<Request>. Having memory requests being managed by smart pointers will simplify the code; it will also prevent memory leakage and dangling pointers.
Change-Id: I7749af38a11ac8eb4d53d8df1252951e0890fde3 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/10996 Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
|
#
12620:fe5cdc0293dd |
|
27-Mar-2018 |
Gabe Black <gabeblack@google.com> |
sparc: Add some missing M5_FALLTHROUGHs and breaks.
These fix what I believe are some bugs, and also some gcc warnings.
Change-Id: I5fb2a1b2f0ef3643b25aaf0c29c096996ef98ec0 Reviewed-on: https://gem5-review.googlesource.com/9402 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabeblack@google.com>
|
#
12544:6a4c3acc4289 |
|
22-Feb-2018 |
Khalique <khalique913@gmail.com> |
sparc: Fix FS Checkpoint loading
Proposed changes to SPARC FS simulation, testing indicates that checkpoints are now loaded correctly with the following command: build/SPARC/gem5.opt configs/example/fs.py -r 1
Change-Id: Icd44f01a74c41a78828ef6fd7b661e584bdb6966 Reviewed-on: https://gem5-review.googlesource.com/8581 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com>
|
#
12406:86bde4a026b5 |
|
22-Dec-2017 |
Gabe Black <gabeblack@google.com> |
arch,cpu: "virtualize" the TLB interface.
CPUs have historically instantiated the architecture specific version of the TLBs to avoid a virtual function call, making them a little bit more dependent on what the current ISA is. Some simple performance measurement, the x86 twolf regression on the atomic CPU, shows that there isn't actually any performance benefit, and if anything the simulator goes slightly faster (although still within margin of error) when the TLB functions are virtual.
This change switches everything outside of the architectures themselves to use the generic BaseTLB type, and then inside the ISA for them to cast that to their architecture specific type to call into architecture specific interfaces.
The ARM TLB needed the most adjustment since it was using non-standard translation function signatures. Specifically, they all took an extra "type" parameter which defaulted to normal, and translateTiming returned a Fault. translateTiming actually doesn't need to return a Fault because everywhere that consumed it just stored it into a structure which it then deleted(?), and the fault is stored in the Translation object when the translation is done.
A little more work is needed to fully obviate the arch/tlb.hh header, so the TheISA::TLB type is still visible outside of the ISAs. Specifically, the TlbEntry type is used in the generic PageTable which lives in src/mem.
Change-Id: I51b68ee74411f9af778317eff222f9349d2ed575 Reviewed-on: https://gem5-review.googlesource.com/6921 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
|
#
11793:ef606668d247 |
|
09-Nov-2016 |
Brandon Potter <brandon.potter@amd.com> |
style: [patch 1/22] use /r/3648/ to reorganize includes
|
#
11150:a8a64cca231b |
|
30-Sep-2015 |
Mitch Hayenga <mitch.hayenga@arm.com> |
isa,cpu: Add support for FS SMT Interrupts
Adds per-thread interrupt controllers and thread/context logic so that interrupts properly get routed in SMT systems.
|
#
10905:a6ca6831e775 |
|
07-Jul-2015 |
Andreas Sandberg <andreas.sandberg@arm.com> |
sim: Refactor the serialization base class
Objects that are can be serialized are supposed to inherit from the Serializable class. This class is meant to provide a unified API for such objects. However, so far it has mainly been used by SimObjects due to some fundamental design limitations. This changeset redesigns to the serialization interface to make it more generic and hide the underlying checkpoint storage. Specifically:
* Add a set of APIs to serialize into a subsection of the current object. Previously, objects that needed this functionality would use ad-hoc solutions using nameOut() and section name generation. In the new world, an object that implements the interface has the methods serializeSection() and unserializeSection() that serialize into a named /subsection/ of the current object. Calling serialize() serializes an object into the current section.
* Move the name() method from Serializable to SimObject as it is no longer needed for serialization. The fully qualified section name is generated by the main serialization code on the fly as objects serialize sub-objects.
* Add a scoped ScopedCheckpointSection helper class. Some objects need to serialize data structures, that are not deriving from Serializable, into subsections. Previously, this was done using nameOut() and manual section name generation. To simplify this, this changeset introduces a ScopedCheckpointSection() helper class. When this class is instantiated, it adds a new /subsection/ and subsequent serialization calls during the lifetime of this helper class happen inside this section (or a subsection in case of nested sections).
* The serialize() call is now const which prevents accidental state manipulation during serialization. Objects that rely on modifying state can use the serializeOld() call instead. The default implementation simply calls serialize(). Note: The old-style calls need to be explicitly called using the serializeOld()/serializeSectionOld() style APIs. These are used by default when serializing SimObjects.
* Both the input and output checkpoints now use their own named types. This hides underlying checkpoint implementation from objects that need checkpointing and makes it easier to change the underlying checkpoint storage code.
|
#
10824:308771bd2647 |
|
05-May-2015 |
Andreas Sandberg <Andreas.Sandberg@ARM.com> |
mem, cpu: Add a separate flag for strictly ordered memory
The Request::UNCACHEABLE flag currently has two different functions. The first, and obvious, function is to prevent the memory system from caching data in the request. The second function is to prevent reordering and speculation in CPU models.
This changeset gives the order/speculation requirement a separate flag (Request::STRICT_ORDER). This flag prevents CPU models from doing the following optimizations:
* Speculation: CPU models are not allowed to issue speculative loads.
* Write combining: CPU models and caches are not allowed to merge writes to the same cache line.
Note: The memory system may still reorder accesses unless the UNCACHEABLE flag is set. It is therefore expected that the STRICT_ORDER flag is combined with the UNCACHEABLE flag to prevent this behavior.
|
#
10474:799c8ee4ecba |
|
16-Oct-2014 |
Andreas Hansson <andreas.hansson@arm.com> |
arch: Use shared_ptr for all Faults
This patch takes quite a large step in transitioning from the ad-hoc RefCountingPtr to the c++11 shared_ptr by adopting its use for all Faults. There are no changes in behaviour, and the code modifications are mostly just replacing "new" with "make_shared".
|
#
10231:cb2e6950956d |
|
31-May-2014 |
Steve Reinhardt <steve.reinhardt@amd.com> |
style: eliminate equality tests with true and false
Using '== true' in a boolean expression is totally redundant, and using '== false' is pretty verbose (and arguably less readable in most cases) compared to '!'.
It's somewhat of a pet peeve, perhaps, but I had some time waiting for some tests to run and decided to clean these up.
Unfortunately, SLICC appears not to have the '!' operator, so I had to leave the '== false' tests in the SLICC code.
|
#
9912:3de4393f5649 |
|
15-Oct-2013 |
Andreas Sandberg <andreas@sandberg.pp.se> |
mem: Rename the ASI_BITS flag field in Request
ASI_BITS in the Request object were originally used to store a memory request's ASI on SPARC. This is not the case any more since other ISAs use the ASI bits to store architecture-dependent information. This changeset renames the ASI_BITS to ARCH_BITS which better describes their use. Additionally, the getAsi() accessor is renamed to getArchFlags().
|
#
9738:304a37519d11 |
|
03-Jun-2013 |
Andreas Sandberg <andreas@sandberg.pp.se> |
arch: Create a method to finalize physical addresses in the TLB
Some architectures (currently only x86) require some fixing-up of physical addresses after a normal address translation. This is usually to remap devices such as the APIC, but could be used for other memory mapped devices as well. When running the CPU in a using hardware virtualization, we still need to do these address fix-ups before inserting the request into the memory system. This patch moves this patch allows that code to be used by such CPUs without doing full address translations.
|
#
9423:43caa4ca5979 |
|
07-Jan-2013 |
Andreas Sandberg <Andreas.Sandberg@arm.com> |
arch: Add support for invalidating TLBs when draining
This patch adds support for the memInvalidate() drain method. TLB flushing is requested by calling the virtual flushAll() method on the TLB.
Note: This patch renames invalidateAll() to flushAll() on x86 and SPARC to make the interface consistent across all supported architectures.
|
#
9180:ee8d7a51651d |
|
28-Aug-2012 |
Andreas Hansson <andreas.hansson@arm.com> |
Clock: Add a Cycles wrapper class and use where applicable
This patch addresses the comments and feedback on the preceding patch that reworks the clocks and now more clearly shows where cycles (relative cycle counts) are used to express time.
Instead of bumping the existing patch I chose to make this a separate patch, merely to try and focus the discussion around a smaller set of changes. The two patches will be pushed together though.
This changes done as part of this patch are mostly following directly from the introduction of the wrapper class, and change enough code to make things compile and run again. There are definitely more places where int/uint/Tick is still used to represent cycles, and it will take some time to chase them all down. Similarly, a lot of parameters should be changed from Param.Tick and Param.Unsigned to Param.Cycles.
In addition, the use of curTick is questionable as there should not be an absolute cycle. Potential solutions can be built on top of this patch. There is a similar situation in the o3 CPU where lastRunningCycle is currently counting in Cycles, and is still an absolute time. More discussion to be had in other words.
An additional change that would be appropriate in the future is to perform a similar wrapping of Tick and probably also introduce a Ticks class along with suitable operators for all these classes.
|
#
8888:befcf4d79fc1 |
|
09-Mar-2012 |
Geoffrey Blake <geoffrey.blake@arm.com> |
CheckerCPU: Add function stubs to non-ARM ISA source to compile with CheckerCPU
Making the CheckerCPU a runtime time option requires the code to be compatible with ISAs other than ARM. This patch adds the appropriate function stubs to allow compilation.
|
#
8751:a6c772fef2f1 |
|
13-Oct-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SPARC: Remove the last checks of FULL_SYSTEM.
|
#
8748:01be402c5bf1 |
|
10-Oct-2011 |
Gabe Black <gblack@eecs.umich.edu> |
SPARC: Turn on handleIprRead and handleIprWrite in SE in SPARC.
|
#
8374:18173b099ed1 |
|
19-Jun-2011 |
Korey Sewell <ksewell@umich.edu> |
sparc: init. cache state in TLB valgrind complains and its a potential source of instability, so go ahead and set it to 0 to start
|
#
8232:b28d06a175be |
|
15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
trace: reimplement the DTRACE function so it doesn't use a vector At the same time, rename the trace flags to debug flags since they have broader usage than simply tracing. This means that --trace-flags is now --debug-flags and --trace-help is now --debug-help
|
#
8229:78bf55f23338 |
|
15-Apr-2011 |
Nathan Binkert <nate@binkert.org> |
includes: sort all includes
|
#
8105:906864dd0937 |
|
02-Mar-2011 |
Gabe Black <gblack@eecs.umich.edu> |
Spelling: Fix the a spelling error by changing mmaped to mmapped.
There may not be a formally correct spelling for the past tense of mmap, but mmapped is the spelling Google doesn't try to autocorrect. This makes sense because it mirrors the past tense of map->mapped and not the past tense of cape->caped.
|
#
7811:a8fc35183c10 |
|
03-Jan-2011 |
Steve Reinhardt <steve.reinhardt@amd.com> |
Make commenting on close namespace brackets consistent.
Ran all the source files through 'perl -pi' with this script:
s|\s*(};?\s*)?/\*\s*(end\s*)?namespace\s*(\S+)\s*\*/(\s*})?|} // namespace $3|; s|\s*};?\s*//\s*(end\s*)?namespace\s*(\S+)\s*|} // namespace $2\n|; s|\s*};?\s*//\s*(\S+)\s*namespace\s*|} // namespace $1\n|;
Also did a little manual editing on some of the arch/*/isa_traits.hh files and src/SConscript.
|
#
7741:340b6f01d69b |
|
11-Nov-2010 |
Gabe Black <gblack@eecs.umich.edu> |
SPARC: Clean up some historical style issues.
|
#
7678:f19b6a3a8cec |
|
13-Sep-2010 |
Gabe Black <gblack@eecs.umich.edu> |
Faults: Pass the StaticInst involved, if any, to a Fault's invoke method.
Also move the "Fault" reference counted pointer type into a separate file, sim/fault.hh. It would be better to name this less similarly to sim/faults.hh to reduce confusion, but fault.hh matches the name of the type. We could change Fault to FaultPtr to match other pointer types, and then changing the name of the file would make more sense.
|
#
7518:917208416d2a |
|
13-Aug-2010 |
Gabe Black <gblack@eecs.umich.edu> |
CPU: Tidy up endianness handling for mmapped "IPR"s.
|
#
6428:9e35cdc95e81 |
|
02-Aug-2009 |
Steve Reinhardt <steve.reinhardt@amd.com> |
Clean up some inconsistencies with Request flags.
|
#
6335:a08470cb53e5 |
|
09-Jul-2009 |
Gabe Black <gblack@eecs.umich.edu> |
SPARC: Fold the MiscRegFile all the way into the ISA object.
|
#
6023:47b4fcb10c11 |
|
09-Apr-2009 |
Nathan Binkert <nate@binkert.org> |
tlb: More fixing of unified TLB
|
#
6022:410194bb3049 |
|
09-Apr-2009 |
Gabe Black <gblack@eecs.umich.edu> |
tlb: Don't separate the TLB classes into an instruction TLB and a data TLB
|
#
5894:8091ac99341a |
|
25-Feb-2009 |
Gabe Black <gblack@eecs.umich.edu> |
CPU: Implement translateTiming which defers to translateAtomic, and convert the timing simple CPU to use it.
|
#
5891:73084c6bb183 |
|
25-Feb-2009 |
Gabe Black <gblack@eecs.umich.edu> |
ISA: Replace the translate functions in the TLBs with translateAtomic.
|
#
5823:9f7efe90084e |
|
30-Jan-2009 |
Ali Saidi <saidi@eecs.umich.edu> |
Errors: Use the correct panic/warn/fatal/info message in some places.
|
#
5736:426510e758ad |
|
10-Nov-2008 |
Nathan Binkert <nate@binkert.org> |
mem: update stuff for changes to Packet and Request
|
#
5704:98224505352a |
|
21-Oct-2008 |
Nathan Binkert <nate@binkert.org> |
style: Use the correct m5 style for things relating to interrupts.
|
#
5646:0a488a147fb8 |
|
12-Oct-2008 |
Gabe Black <gblack@eecs.umich.edu> |
CPU: Eliminate the get_vec function.
|
#
5570:13592d41f290 |
|
28-Sep-2008 |
Nathan Binkert <nate@binkert.org> |
gcc: Add extra parens to quell warnings. Even though we're not incorrect about operator precedence, let's add some parens in some particularly confusing places to placate GCC 4.3 so that we don't have to turn the warning off. Agreed that this is a bit of a pain for those users who get the order of operations correct, but it is likely to prevent bugs in certain cases.
|
#
5555:07c10d7dd62d |
|
23-Sep-2008 |
Nathan Binkert <nate@binkert.org> |
sparc: Fix style, create a helper function for translation. The translate function simplifies code and removes some compiler warnings in gcc 3.4
|
#
5358:e9acb84bbafb |
|
26-Feb-2008 |
Gabe Black <gblack@eecs.umich.edu> |
TLB: Make a TLB base class and put a virtual demapPage function in it.
|
#
5312:1dc4440797b6 |
|
01-Jan-2008 |
Gabe Black <gblack@eecs.umich.edu> |
SPARC: Fix a bug where the TLB would match against the wrong entries.
|
#
5288:7dd5694453b3 |
|
30-Nov-2007 |
Gabe Black <gblack@eecs.umich.edu> |
SPARC: Fixes for invalidateAll and demapAll in the SPARC TLBs.
|
#
5276:2f55b8e7f346 |
|
19-Nov-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Serialization: Serialize SPARC PTEs last so their nameOut() calls don't interfere with other serialization in the TLB.
|
#
5100:7a0180040755 |
|
28-Sep-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Rename cycles() function to ticks()
|
#
5034:6186ef720dd4 |
|
30-Aug-2007 |
Miles Kaufmann <milesck@eecs.umich.edu> |
params: Deprecate old-style constructors; update most SimObject constructors.
SimObjects not yet updated: - Process and subclasses - BaseCPU and subclasses
The SimObject(const std::string &name) constructor was removed. Subclasses that still rely on that behavior must call the parent initializer as : SimObject(makeParams(name))
|
#
4997:e7380529bd2d |
|
26-Aug-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Address Translation: Make SE mode use an actual TLB/MMU for translation like FS.
|
#
4996:e827e57a01f9 |
|
26-Aug-2007 |
Gabe Black <gblack@eecs.umich.edu> |
SPARC: Make sure unaligned access are caught on cached translations as well.
|
#
4990:38d74405ddac |
|
13-Aug-2007 |
Gabe Black <gblack@eecs.umich.edu> |
SPARC: Move tlb state into the tlb. Each "strand" may need to have a private copy of this state, but I couldn't find anywhere in the spec that said that after looking briefly. This prevents writes to the thread context in o3 which was causing the pipeline to be flushed and stopping any forward progress. The other ASI accessible state will probably need to be accessed differently if/when we get O3 full system up and running.
|
#
4989:3e9d532cf998 |
|
13-Aug-2007 |
Gabe Black <gblack@eecs.umich.edu> |
SPARC: Make the spill and fill handlers use the correct ASI, and let No_Fault ASI accesses work.
|
#
4918:3214e3694fb2 |
|
27-Jul-2007 |
Nathan Binkert <nate@binkert.org> |
Merge python and x86 changes with cache branch
|
#
4870:fcc39d001154 |
|
30-Jun-2007 |
Steve Reinhardt <stever@eecs.umich.edu> |
Get rid of Packet result field. Error responses are now encoded in cmd field.
|
#
4762:c94e103c83ad |
|
24-Jul-2007 |
Nathan Binkert <nate@binkert.org> |
Major changes to how SimObjects are created and initialized. Almost all creation and initialization now happens in python. Parameter objects are generated and initialized by python. The .ini file is now solely for debugging purposes and is not used in construction of the objects in any way.
|
#
4191:c191c1fec061 |
|
08-Mar-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Panic if any CMT registers are accessed
src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: add CMT ASI registers src/arch/sparc/tlb.cc: Panic if any of the CMT registers are being accessed
|
#
4172:141705d83494 |
|
07-Mar-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
*MiscReg->*MiscRegNoEffect, *MiscRegWithEffect->*MiscReg
|
#
4103:785279436bdd |
|
03-Mar-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Implement Niagara I/O interface and rework interrupts
configs/common/FSConfig.py: Use binaries we've compiled instead of the ones that come with Legion src/arch/alpha/interrupts.hh: get rid of post(int int_type) and add a get_vec function that gets the interrupt vector for an interrupt number src/arch/sparc/asi.cc: Add AsiIsInterrupt() to AsiIsMmu() src/arch/sparc/faults.cc: src/arch/sparc/faults.hh: Add InterruptVector type src/arch/sparc/interrupts.hh: rework interrupts. They are no longer cleared when created... A I/O or ASI read/write needs to happen before they are cleared src/arch/sparc/isa_traits.hh: Add the "interrupt" trap types to isa traits src/arch/sparc/miscregfile.cc: add names for all the misc registers and possible post an interrupt when TL is changed. src/arch/sparc/miscregfile.hh: Add a helper function to post an interrupt when pil < some set softint src/arch/sparc/regfile.cc: src/arch/sparc/regfile.hh: InterruptLevel shouldn't really live here, moved to interrupt.hh src/arch/sparc/tlb.cc: Add interrupt ASIs to TLB src/arch/sparc/ua2005.cc: Add checkSoftInt to check if a softint needs to be posted Check that a tickCompare isn't scheduled before scheduling one Post and clear interrupts on queue writes and what not src/base/bitfield.hh: Add an helper function to return the msb that is set src/cpu/base.cc: src/cpu/base.hh: get rid of post_interrupt(type) since it's no longer needed.. Add a way to see what interrupts are pending src/cpu/intr_control.cc: src/cpu/intr_control.hh: src/dev/alpha/tsunami_cchip.cc: src/python/m5/objects/IntrControl.py: Make IntrControl have a system pointer rather than using a cpu pointer to get one src/dev/sparc/SConscript: add iob to SConsscrip tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini: tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.ini: tests/quick/80.netperf-stream/ref/alpha/linux/twosys-tsunami-simple-atomic/config.out: update config.ini/out for intrcntrl not having a cpu pointer anymore
|
#
4091:e9d669b2d6b1 |
|
21-Feb-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Merge zizzer:/bk/newmem into zeep.pool:/z/saidi/work/m5.newmem
|
#
4090:08bd6439b907 |
|
21-Feb-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
add pseduo instruction support for sparc
util/m5/Makefile.alpha: Clean up to make it a bit easier to muck with util/m5/Makefile.alpha: Make the makefile more reasonable util/m5/Makefile.alpha: Remove authors from copyright. util/m5/Makefile.alpha: Updated Authors from bk prs info util/m5/Makefile.alpha: bk cp Makefile Makefile.alpha src/arch/sparc/tlb.cc: Clean up the cache code a little bit and make sure the uncacbale bit is set when appropriate src/arch/alpha/isa/decoder.isa: src/sim/pseudo_inst.cc: src/sim/pseudo_inst.hh: Rename AlphaPseudo -> PseudoInst since it's all generic src/arch/sparc/isa/bitfields.isa: src/arch/sparc/isa/decoder.isa: src/arch/sparc/isa/includes.isa: src/arch/sparc/isa/operands.isa: Add support for pseudo instructions in sparc util/m5/Makefile.alpha: util/m5/Makefile.sparc: split off alpha make file and sparc make file for m5 app util/m5/m5.c: ivle and ivlb aren't used anymore util/m5/m5op.h: stdint seems like a more generic better fit here util/m5/m5op_alpha.S: move the op ids into their own header file since we can share them between sparc and alpha
|
#
4088:a60eb44ae415 |
|
21-Feb-2007 |
Nathan Binkert <binkertn@umich.edu> |
Fix compile issues on gcc 4.1.x related to namespaces. This basically involves moving the builder code outside of any namespace. While we're at it, move a few braces outside of a couple #if/#else/#endif blocks so it's easier to match up the braces.
|
#
4070:74449a198a44 |
|
18-Feb-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
implement vtophys and 32bit gdb support
src/arch/alpha/vtophys.cc: src/arch/alpha/vtophys.hh: src/arch/sparc/arguments.hh: move Copy* to vport since it's generic for all the ISAs src/arch/sparc/isa_traits.hh: the Solaris kernel sets up a virtual-> real mapping for all memory starting at SegKPMBase src/arch/sparc/pagetable.hh: add a class for getting bits out of the TteTag src/arch/sparc/remote_gdb.cc: add 32bit support kinda.... If its 32 bit src/arch/sparc/remote_gdb.hh: Add 32bit register offsets too. src/arch/sparc/tlb.cc: cleanup generation of tsb pointers src/arch/sparc/tlb.hh: add function to return tsb pointers for an address make lookup public so vtophys can use it src/arch/sparc/vtophys.cc: src/arch/sparc/vtophys.hh: write vtophys for sparc src/base/bitfield.hh: return a mask of bits first->last src/mem/vport.cc: src/mem/vport.hh: move Copy* here since it's ISA generic
|
#
4010:52c2b6941c02 |
|
02-Feb-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
more sparc fixes
src/arch/sparc/isa/decoder.isa: fix rdgsr fault check src/arch/sparc/tlb.cc: block asis are now supported
|
#
4007:8c3bfad8bb92 |
|
31-Jan-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
make sparc fs less chatty
src/SConscript: strip doesn't take a src and dest in solaris
|
#
4000:9bf49767a9e4 |
|
30-Jan-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Make SPARC checkpointing work
src/arch/sparc/floatregfile.cc: Fix serialization for fpreg src/arch/sparc/intregfile.cc: fix serialization for intreg src/arch/sparc/miscregfile.cc: fix serialization from miscreg src/arch/sparc/pagetable.cc: fix serialization for page table src/arch/sparc/regfile.cc: need to serialize nnpc src/arch/sparc/tlb.cc: write serialization code for tlb src/cpu/base.cc: provide a way to find the thread number a context is serialize the instruction counter src/cpu/base.hh: provide a way to find the thread number a context is and given a thread number find a context pointer src/cpu/cpuevent.hh: provide method to get thread context from a cpu event for serialization src/dev/sparc/t1000.cc: src/dev/sparc/t1000.hh: nothing to serialize in t1000 src/sim/serialize.cc: src/sim/serialize.hh: Make findObj() work (it hasn't since we did the python conversion stuff)
|
#
3980:9bcb2a2e9bb8 |
|
27-Jan-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Merge zizzer:/bk/newmem into zower.eecs.umich.edu:/eecshome/m5/newmem
src/arch/sparc/isa/formats/mem/util.isa: src/arch/sparc/isa_traits.hh: src/arch/sparc/system.cc: Hand Merge
|
#
3979:3b0b08f60cdf |
|
27-Jan-2007 |
Gabe Black <gblack@eecs.umich.edu> |
Got rid of some DPRINTFs that were printing raw pointers.
|
#
3930:f96f7e258255 |
|
26-Jan-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Merge zeep.pool:/z/saidi/work/m5.newmem into zeep.pool:/z/saidi/work/m5.suncc
|
#
3929:3640569369a5 |
|
25-Jan-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
fix smul and sdiv to sign extend, and handle overflow/underflow corretly Only allow writing/reading of 32 bits of Y Only allow writing/reading 32 bits of pc when pstate.am Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation only erase a entry from the lookup table if it's valid Put in a temporary check to make sure that lookup table and tlb array stay in sync if we are interrupted in the middle of a mico-op, reset the micropc/nexpc so we start on the first part of it when we come back
src/arch/sparc/isa/decoder.isa: fix smul and sdiv to sign extend, and handle overflow/underflow corretly Only allow writing/reading of 32 bits of Y Only allow writing/reading 32 bits of pc when pstate.am Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation src/arch/sparc/isa/formats/mem/blockmem.isa: Put any loaded data on the first half of a micro-op in uReg0 so it can't overwrite the register we are using for address calculation src/arch/sparc/isa/includes.isa: Use limits for 32bit underflow/overflow detection src/arch/sparc/tlb.cc: only erase a entry from the lookup table if it's valid Put in a temporary check to make sure that lookup table and tlb array stay in sync src/arch/sparc/tlb_map.hh: add a print function to dump the tlb lookup table src/cpu/simple/base.cc: if we are interrupted in the middle of a mico-op, reset the micropc/nexpc so we start on the first part of it when we come back
|
#
3928:9486450f013f |
|
23-Jan-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
use pstate.am to mask off PC/NPC where it needs to +be check writability of tlb cache entry before using update tagaccess in places I forgot to move the tlb privileged test up since it is higher priority
src/arch/sparc/faults.cc: save only 32 bits of PC/NPC if Pstate.am is set src/arch/sparc/isa/decoder.isa: return only 32 bits of PC/NPC if Pstate.am is set increment cleanwin correctly src/arch/sparc/tlb.cc: check writability of cache entry update tagaccess in a few more places move the privileged test up since it is higher priority src/cpu/exetrace.cc: mask off upper bits of pc if pstate.am is set before comparing to legion
|
#
3926:c57925da8d38 |
|
22-Jan-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
clean up fault code a little bit simplify and make complete some asi checks implement all the twin asis and remove panic checks on their use soft int is supported, so we don't need to print writes to it
src/arch/sparc/asi.cc: make AsiIsLittle() be all the little asis. Speed up AsiIsTwin() a bit src/arch/sparc/faults.cc: clean up the do*Fault code.... Make it work like legion, in particular pstate.priv is left alone, not set to 0 like the spec says src/arch/sparc/isa/decoder.isa: implement some more twin ASIs src/arch/sparc/tlb.cc: All the twin asis are implemented, no need to say their not supported anymore src/arch/sparc/ua2005.cc: softint is supported now, no more need to
|
#
3918:1f9a98d198e8 |
|
26-Jan-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
make our code a little more standards compliant pretty close to compiling w/ suns compiler
briefly: add dummy return after panic()/fatal() split out flags by compiler vendor include cstring and cmath where appropriate use std namespace for string ops
SConstruct: Add code to detect compiler and choose cflags based on detected compiler Fix zlib check to work with suncc src/SConscript: split out flags by compiler vendor src/arch/sparc/isa/decoder.isa: use correct namespace for sqrt src/arch/sparc/isa/formats/basic.isa: add dummy return around panic src/arch/sparc/isa/formats/integerop.isa: use correct namespace for stringops src/arch/sparc/isa/includes.isa: include cstring and cmath where appropriate src/arch/sparc/isa_traits.hh: remove dangling comma src/arch/sparc/system.cc: dummy return to make sun cc front end happy src/arch/sparc/tlb.cc: src/base/compression/lzss_compression.cc: use std namespace for string ops src/arch/sparc/utility.hh: no reason to say something is unsigned unsigned int src/base/compression/null_compression.hh: dummy returns to for suncc front end src/base/cprintf.hh: use standard variadic argument syntax instead of gnuc specefic renaming src/base/hashmap.hh: don't need to define hash for suncc src/base/hostinfo.cc: need stdio.h for sprintf src/base/loader/object_file.cc: munmap is in std namespace not null src/base/misc.hh: use M5 generic noreturn macros use standard variadic macro __VA_ARGS__ src/base/pollevent.cc: we need file.h for file flags src/base/random.cc: mess with include files to make suncc happy src/base/remote_gdb.cc: malloc memory for function instead of having a non-constant in an array size src/base/statistics.hh: use std namespace for floor src/base/stats/text.cc: include math.h for rint (cmath won't work) src/base/time.cc: use suncc version of ctime_r src/base/time.hh: change macro to work with both gcc and suncc src/base/timebuf.hh: include cstring from memset and use std:: src/base/trace.hh: change variadic macros to be normal format src/cpu/SConscript: add dummy returns where appropriate src/cpu/activity.cc: include cstring for memset src/cpu/exetrace.hh: include cstring fro memcpy src/cpu/simple/base.hh: add dummy return for panic src/dev/baddev.cc: src/dev/pciconfigall.cc: src/dev/platform.cc: src/dev/sparc/t1000.cc: add dummy return where appropriate src/dev/ide_atareg.h: make define work for both gnuc and suncc src/dev/io_device.hh: add dummy returns where approirate src/dev/pcidev.hh: src/mem/cache/cache_impl.hh: src/mem/cache/miss/blocking_buffer.cc: src/mem/cache/tags/lru.hh: src/mem/cache/tags/split.hh: src/mem/cache/tags/split_lifo.hh: src/mem/cache/tags/split_lru.hh: src/mem/dram.cc: src/mem/packet.cc: src/mem/port.cc: include cstring for string ops src/dev/sparc/mm_disk.cc: add dummy return where appropriate include cstring for string ops src/mem/cache/miss/blocking_buffer.hh: src/mem/port.hh: Add dummy return where appropriate src/mem/cache/tags/iic.cc: cast hastSets to double for log() call src/mem/physical.cc: cast pmemAddr to char* for munmap src/sim/byteswap.hh: make define work for suncc and gnuc
|
#
3916:3f394f5bc533 |
|
22-Jan-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
use writeTagAccess() function to unify writing of Tag access registers Fix extracting of secondary context to shove into tag access register properly sign extend va from 59 bits to 63 (SPARC VA hole)
|
#
3915:1e183d6dea0b |
|
21-Jan-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
make sure that page bits of VA on tlb insert are 0
|
#
3912:57c18b8d9157 |
|
20-Jan-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
atually set all 64 bits of the retun value to 0
|
#
3910:bad95ceb5efe |
|
20-Jan-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Rearange tlb code to remove some duplicate Sparc error register should return ull(0) since it's 64 bits Fix PS1 pointer creation to use the ps1 page size rather than ps0
|
#
3908:0a072cce91dd |
|
17-Jan-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Allow ASI_LDTX_REAL
|
#
3907:00f18b4eedb5 |
|
17-Jan-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
do a linear search for matching tlb entries instead of using map because you could be mapping a larger page that intersects many fix for lookup table to keep it consistant with tlb on a replace of a specific entry
|
#
3906:4cf7d8d42349 |
|
17-Jan-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
Implement reading writing of sync fault status register and address register
|
#
3902:f09fe9c1e609 |
|
16-Jan-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
In the case of ASI_P or ASI_LDTX_P set primary and skip the other checks
|
#
3899:389e4ea5f98e |
|
09-Jan-2007 |
Ali Saidi <saidi@eecs.umich.edu> |
quiet/remove some warnings fix implementation of cwp manipulation implement PS0 and PS1 IMMU asis
src/arch/sparc/miscregfile.cc: get rid of some warnings fix implementation of setting cwp to saturate cwp since it appears the os sets it to a large value to see how many there actually are src/arch/sparc/tlb.cc: implement PS0 and PS1 IMMU access ASIs src/arch/sparc/ua2005.cc: make warning less verbose
|
#
3881:f06ef65cd746 |
|
27-Dec-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Bug fixes in the TLB Make our replacement algorithm same as legion (although not same as the spec) itb should be 64 entries not 48
src/arch/sparc/tlb.cc: Bug fixes in the TLB Make our replacement algorithm same as legion (although not same as the spec) src/arch/sparc/tlb.hh: Make our replacement algorithm same as legion (although not same as the spec) src/python/m5/objects/SparcTLB.py: itb should be 64 entries too
|
#
3863:adf3ddd4bcde |
|
19-Dec-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
fix twinx loads a little bit bugfixes and demap implementation in tlb ignore some more differencs for one cycle
src/arch/sparc/isa/formats/mem/blockmem.isa: twinx has 2 micro-ops src/arch/sparc/isa/formats/mem/util.isa: fix the fault check for twinx src/arch/sparc/tlb.cc: tlb bugfixes and write demapping code src/cpu/exetrace.cc: don't halt on a couple more instruction (ldx, stx) when things differ beacuse of the way tlb faults are handled in legion.
|
#
3856:8815ad4f0661 |
|
18-Dec-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
move the twinx loads to the correct opcode and add asis 0x24 and 0x27 Make the TLB ok to translate QUAD_LDD
src/arch/sparc/isa/decoder.isa: move the twinx loads to the correct opcode. src/arch/sparc/tlb.cc: Make QUAD_LDD asi ok to execute
|
#
3836:659b8c627478 |
|
15-Dec-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Optimized the TLB translations with some caching
|
#
3833:b5faabcf350e |
|
14-Dec-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
flesh out twinx asis fix TICK register reads reduce the number of readmiscreg accesses, implement tsb pointer stuff
src/arch/sparc/asi.cc: flesh out twinx asis src/arch/sparc/miscregfile.cc: fix TICK register reads src/arch/sparc/tlb.cc: reduce the number of readmiscreg accesses, implement tsb pointer stuff
|
#
3832:49c95a73e29c |
|
12-Dec-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Fix bugs in tlbmap (and thus rangemap since the code is nearly identical) Deal with block initializing stores (by doing nothing, at some point we might want to do the write hint 64 like thing) Fix tcc instruction igoner in legion-lock stuff to be correct in all cases Have console interrupts warn rather than panicing until we figure out what to do with interrupts
src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: add a magic miscreg which reads all the bits the tlb needs in one go src/arch/sparc/tlb.cc: initialized the context type and id to reasonable values and handle block init stores src/arch/sparc/tlb_map.hh: fix bug in tlb map code src/base/range_map.hh: fix bug in rangemap code and add range_multimap (these are probably useful for bus range stuff) src/cpu/exetrace.cc: fixup tcc ignore code to be correct src/dev/sparc/t1000.cc: make console interrupt stuff warn instead of panicing until we get interrupt stuff figured out src/unittest/rangemaptest.cc: fix up the rangemap unit test to catch the missing case
|
#
3826:e35adf01a285 |
|
09-Dec-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Allocate the correct number of global registers Fix fault formating and code for traps fix a couple of bugs in the decoder Cleanup/fix page table entry code Implement more mmaped iprs, fix numbered tlb insertion code, add function to dump tlb contents Don't panic if we differ from legion on a tcc instruction because of where legion prints its data and where we print our data
src/arch/sparc/faults.cc: Fix fault formating and code for traps src/arch/sparc/intregfile.hh: allocate the correct number of global registers src/arch/sparc/isa/decoder.isa: fix a couple of bugs in the decoder: wrasi should write asi not ccr, done/retry should get hpstate from htstate src/arch/sparc/pagetable.hh: cleanup/fix page table code src/arch/sparc/tlb.cc: implement more mmaped iprs, fix numbered insertion code, add function to dump tlb contents src/arch/sparc/tlb.hh: add functions to write TagAccess register on tlb miss and to dump all tlb entries for debugging src/cpu/exetrace.cc: dump tlb entries on error, don't consider differences the cycle we take a trap to be bad.
|
#
3825:9b5e6c4d3ecb |
|
07-Dec-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
get legion/m5 to first tlb miss fault
src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: add sparc error asi src/arch/sparc/faults.cc: put a panic in if TL == MaxTL src/arch/sparc/isa/decoder.isa: Hpstate needs to be updated on a done too src/arch/sparc/miscregfile.cc: warn istead of panicing of fprs/fsr accesses src/arch/sparc/tlb.cc: add sparc error register code that just does nothing fix a couple of other tlb bugs src/arch/sparc/ua2005.cc: fix implementation of HPSTATE write src/cpu/exetrace.cc: let exectrate mess up a couple of times before dying src/python/m5/objects/T1000.py: add l2 error status register fake devices
|
#
3824:8900576818d7 |
|
06-Dec-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Handle access to ASI_QUEUE Add function for interrupt ASIs add all the new MISCREGs to the copyMiscRegs() file
src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: Add function for interrupt ASIs src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: Add QUEUE asi/misc registers src/arch/sparc/regfile.cc: add all the new MISCREGs to the copyMiscRegs() file src/arch/sparc/tlb.cc: Handle access to ASI_QUEUE
|
#
3823:1c8f87aa103e |
|
06-Dec-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Many more fixes for SPARC_FS. Gets us to the point where SOFTINT starts getting touched.
configs/common/FSConfig.py: Physical memory on the T1 starts at 1MB, The first megabyte is unmapped to catch bugs src/arch/isa_parser.py: we should readmiscregwitheffect not readmiscreg src/arch/sparc/asi.cc: Fix AsiIsNucleus spelling with respect to header file Add ASI_LSU_CONTROL_REG to AsiSiMmu src/arch/sparc/asi.hh: Fix spelling of two ASIs src/arch/sparc/isa/decoder.isa: switch back to defaults letting the isa_parser insert readMiscRegWithEffect src/arch/sparc/isa/formats/mem/util.isa: Flesh out priviledgedString with hypervisor checks Make load alternate set the flags correctly src/arch/sparc/miscregfile.cc: insert some forgotten break statements src/arch/sparc/miscregfile.hh: Add some comments to make it easier to find which misc register is which number src/arch/sparc/tlb.cc: flesh out the tlb memory mapped registers a lot more src/base/traceflags.py: add an IPR traceflag src/mem/request.hh: Fix a bad assert() in request
|
#
3811:ee71d61347f1 |
|
29-Nov-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Add TLB Dprintfs fix addr alignment problem
|
#
3806:65ae5388c059 |
|
29-Nov-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
Add support for mmapped iprs to atomic cpu
src/arch/SConscript: add mmaped_ipr.hh to switch headers src/arch/sparc/asi.hh: make ASI_IMPLICT=0 so by default nothing needs to be done src/arch/sparc/miscregfile.hh: miscregfile no longer needs to include asi.hh src/arch/sparc/tlb.cc: src/arch/sparc/tlb.hh: implement panic instructions for mmaped ipr reads src/cpu/simple/atomic.cc: add check for mmaped iprs and handle them if it exists src/mem/request.hh: allocate space in the flags for mmaped iprs. Put in in the first 8 bits so that by default its fast. Move the other flags up 8 bits
|
#
3804:fa7a01dddc7a |
|
23-Nov-2006 |
Ali Saidi <saidi@eecs.umich.edu> |
first cut at a sparc tlb
src/arch/sparc/SConscript: Add code to serialize/unserialze tlb entries src/arch/sparc/asi.cc: src/arch/sparc/asi.hh: update asi names for how they're listed in the supplement add asis add more asi functions src/arch/sparc/isa_traits.hh: move the interrupt stuff and some basic address space stuff into isa traits src/arch/sparc/miscregfile.cc: src/arch/sparc/miscregfile.hh: add mmu registers to tlb get rid of implicit asi stuff... the tlb will handle it src/arch/sparc/regfile.hh: make isnt/dataAsid return ints not asis src/arch/sparc/tlb.cc: src/arch/sparc/tlb.hh: first cut at sparc tlb src/arch/sparc/vtophys.hh: pagatable nedes to be included here src/mem/request.hh: add asi and if the request is a memory mapped register to the requset object src/sim/host.hh: fix incorrect definition of LL
|
#
3569:ef68c162610f |
|
08-Nov-2006 |
Gabe Black <gblack@eecs.umich.edu> |
Stubs for SPARC's tlbs
|