tlb.cc revision 3979:3b0b08f60cdf
1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30 31#include "arch/sparc/asi.hh" 32#include "arch/sparc/miscregfile.hh" 33#include "arch/sparc/tlb.hh" 34#include "base/bitfield.hh" 35#include "base/trace.hh" 36#include "cpu/thread_context.hh" 37#include "cpu/base.hh" 38#include "mem/packet_access.hh" 39#include "mem/request.hh" 40#include "sim/builder.hh" 41 42/* @todo remove some of the magic constants. -- ali 43 * */ 44namespace SparcISA 45{ 46 47TLB::TLB(const std::string &name, int s) 48 : SimObject(name), size(s), usedEntries(0), lastReplaced(0), 49 cacheValid(false) 50{ 51 // To make this work you'll have to change the hypervisor and OS 52 if (size > 64) 53 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 54 55 tlb = new TlbEntry[size]; 56 memset(tlb, 0, sizeof(TlbEntry) * size); 57 58 for (int x = 0; x < size; x++) 59 freeList.push_back(&tlb[x]); 60} 61 62void 63TLB::clearUsedBits() 64{ 65 MapIter i; 66 for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 67 TlbEntry *t = i->second; 68 if (!t->pte.locked()) { 69 t->used = false; 70 usedEntries--; 71 } 72 } 73} 74 75 76void 77TLB::insert(Addr va, int partition_id, int context_id, bool real, 78 const PageTableEntry& PTE, int entry) 79{ 80 81 82 MapIter i; 83 TlbEntry *new_entry = NULL; 84// TlbRange tr; 85 int x; 86 87 cacheValid = false; 88 va &= ~(PTE.size()-1); 89 /* tr.va = va; 90 tr.size = PTE.size() - 1; 91 tr.contextId = context_id; 92 tr.partitionId = partition_id; 93 tr.real = real; 94*/ 95 96 DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 97 va, PTE.paddr(), partition_id, context_id, (int)real, entry); 98 99 // Demap any entry that conflicts 100 for (x = 0; x < size; x++) { 101 if (tlb[x].range.real == real && 102 tlb[x].range.partitionId == partition_id && 103 tlb[x].range.va < va + PTE.size() - 1 && 104 tlb[x].range.va + tlb[x].range.size >= va && 105 (real || tlb[x].range.contextId == context_id )) 106 { 107 if (tlb[x].valid) { 108 freeList.push_front(&tlb[x]); 109 DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 110 111 tlb[x].valid = false; 112 if (tlb[x].used) { 113 tlb[x].used = false; 114 usedEntries--; 115 } 116 lookupTable.erase(tlb[x].range); 117 } 118 } 119 } 120 121 122/* 123 i = lookupTable.find(tr); 124 if (i != lookupTable.end()) { 125 i->second->valid = false; 126 if (i->second->used) { 127 i->second->used = false; 128 usedEntries--; 129 } 130 freeList.push_front(i->second); 131 DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n", 132 i->second); 133 lookupTable.erase(i); 134 } 135*/ 136 137 if (entry != -1) { 138 assert(entry < size && entry >= 0); 139 new_entry = &tlb[entry]; 140 } else { 141 if (!freeList.empty()) { 142 new_entry = freeList.front(); 143 } else { 144 x = lastReplaced; 145 do { 146 ++x; 147 if (x == size) 148 x = 0; 149 if (x == lastReplaced) 150 goto insertAllLocked; 151 } while (tlb[x].pte.locked()); 152 lastReplaced = x; 153 new_entry = &tlb[x]; 154 } 155 /* 156 for (x = 0; x < size; x++) { 157 if (!tlb[x].valid || !tlb[x].used) { 158 new_entry = &tlb[x]; 159 break; 160 } 161 }*/ 162 } 163 164insertAllLocked: 165 // Update the last ently if their all locked 166 if (!new_entry) { 167 new_entry = &tlb[size-1]; 168 } 169 170 freeList.remove(new_entry); 171 if (new_entry->valid && new_entry->used) 172 usedEntries--; 173 174 lookupTable.erase(new_entry->range); 175 176 177 assert(PTE.valid()); 178 new_entry->range.va = va; 179 new_entry->range.size = PTE.size() - 1; 180 new_entry->range.partitionId = partition_id; 181 new_entry->range.contextId = context_id; 182 new_entry->range.real = real; 183 new_entry->pte = PTE; 184 new_entry->used = true;; 185 new_entry->valid = true; 186 usedEntries++; 187 188 189 190 i = lookupTable.insert(new_entry->range, new_entry); 191 assert(i != lookupTable.end()); 192 193 // If all entries have there used bit set, clear it on them all, but the 194 // one we just inserted 195 if (usedEntries == size) { 196 clearUsedBits(); 197 new_entry->used = true; 198 usedEntries++; 199 } 200 201} 202 203 204TlbEntry* 205TLB::lookup(Addr va, int partition_id, bool real, int context_id) 206{ 207 MapIter i; 208 TlbRange tr; 209 TlbEntry *t; 210 211 DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 212 va, partition_id, context_id, real); 213 // Assemble full address structure 214 tr.va = va; 215 tr.size = MachineBytes; 216 tr.contextId = context_id; 217 tr.partitionId = partition_id; 218 tr.real = real; 219 220 // Try to find the entry 221 i = lookupTable.find(tr); 222 if (i == lookupTable.end()) { 223 DPRINTF(TLB, "TLB: No valid entry found\n"); 224 return NULL; 225 } 226 227 // Mark the entries used bit and clear other used bits in needed 228 t = i->second; 229 DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 230 t->pte.size()); 231 if (!t->used) { 232 t->used = true; 233 usedEntries++; 234 if (usedEntries == size) { 235 clearUsedBits(); 236 t->used = true; 237 usedEntries++; 238 } 239 } 240 241 return t; 242} 243 244void 245TLB::dumpAll() 246{ 247 MapIter i; 248 for (int x = 0; x < size; x++) { 249 if (tlb[x].valid) { 250 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 251 x, tlb[x].range.partitionId, tlb[x].range.contextId, 252 tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 253 tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 254 } 255 } 256} 257 258void 259TLB::demapPage(Addr va, int partition_id, bool real, int context_id) 260{ 261 TlbRange tr; 262 MapIter i; 263 264 DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 265 va, partition_id, context_id, real); 266 267 cacheValid = false; 268 269 // Assemble full address structure 270 tr.va = va; 271 tr.size = MachineBytes; 272 tr.contextId = context_id; 273 tr.partitionId = partition_id; 274 tr.real = real; 275 276 // Demap any entry that conflicts 277 i = lookupTable.find(tr); 278 if (i != lookupTable.end()) { 279 DPRINTF(IPR, "TLB: Demapped page\n"); 280 i->second->valid = false; 281 if (i->second->used) { 282 i->second->used = false; 283 usedEntries--; 284 } 285 freeList.push_front(i->second); 286 lookupTable.erase(i); 287 } 288} 289 290void 291TLB::demapContext(int partition_id, int context_id) 292{ 293 int x; 294 DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 295 partition_id, context_id); 296 cacheValid = false; 297 for (x = 0; x < size; x++) { 298 if (tlb[x].range.contextId == context_id && 299 tlb[x].range.partitionId == partition_id) { 300 if (tlb[x].valid == true) { 301 freeList.push_front(&tlb[x]); 302 } 303 tlb[x].valid = false; 304 if (tlb[x].used) { 305 tlb[x].used = false; 306 usedEntries--; 307 } 308 lookupTable.erase(tlb[x].range); 309 } 310 } 311} 312 313void 314TLB::demapAll(int partition_id) 315{ 316 int x; 317 DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 318 cacheValid = false; 319 for (x = 0; x < size; x++) { 320 if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) { 321 if (tlb[x].valid == true){ 322 freeList.push_front(&tlb[x]); 323 } 324 tlb[x].valid = false; 325 if (tlb[x].used) { 326 tlb[x].used = false; 327 usedEntries--; 328 } 329 lookupTable.erase(tlb[x].range); 330 } 331 } 332} 333 334void 335TLB::invalidateAll() 336{ 337 int x; 338 cacheValid = false; 339 340 freeList.clear(); 341 lookupTable.clear(); 342 for (x = 0; x < size; x++) { 343 if (tlb[x].valid == true) 344 freeList.push_back(&tlb[x]); 345 tlb[x].valid = false; 346 tlb[x].used = false; 347 } 348 usedEntries = 0; 349} 350 351uint64_t 352TLB::TteRead(int entry) { 353 if (entry >= size) 354 panic("entry: %d\n", entry); 355 356 assert(entry < size); 357 if (tlb[entry].valid) 358 return tlb[entry].pte(); 359 else 360 return (uint64_t)-1ll; 361} 362 363uint64_t 364TLB::TagRead(int entry) { 365 assert(entry < size); 366 uint64_t tag; 367 if (!tlb[entry].valid) 368 return (uint64_t)-1ll; 369 370 tag = tlb[entry].range.contextId; 371 tag |= tlb[entry].range.va; 372 tag |= (uint64_t)tlb[entry].range.partitionId << 61; 373 tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 374 tag |= (uint64_t)~tlb[entry].pte._size() << 56; 375 return tag; 376} 377 378bool 379TLB::validVirtualAddress(Addr va, bool am) 380{ 381 if (am) 382 return true; 383 if (va >= StartVAddrHole && va <= EndVAddrHole) 384 return false; 385 return true; 386} 387 388void 389TLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, 390 bool se, FaultTypes ft, int asi) 391{ 392 uint64_t sfsr; 393 sfsr = tc->readMiscReg(reg); 394 395 if (sfsr & 0x1) 396 sfsr = 0x3; 397 else 398 sfsr = 1; 399 400 if (write) 401 sfsr |= 1 << 2; 402 sfsr |= ct << 4; 403 if (se) 404 sfsr |= 1 << 6; 405 sfsr |= ft << 7; 406 sfsr |= asi << 16; 407 tc->setMiscRegWithEffect(reg, sfsr); 408} 409 410void 411TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context) 412{ 413 DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 414 va, context, mbits(va, 63,13) | mbits(context,12,0)); 415 416 tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0)); 417} 418 419void 420ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, 421 bool se, FaultTypes ft, int asi) 422{ 423 DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 424 (int)write, ct, ft, asi); 425 TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi); 426} 427 428void 429ITB::writeTagAccess(ThreadContext *tc, Addr va, int context) 430{ 431 TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context); 432} 433 434void 435DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, 436 bool se, FaultTypes ft, int asi) 437{ 438 DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 439 a, (int)write, ct, ft, asi); 440 TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); 441 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a); 442} 443 444void 445DTB::writeTagAccess(ThreadContext *tc, Addr va, int context) 446{ 447 TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context); 448} 449 450 451 452Fault 453ITB::translate(RequestPtr &req, ThreadContext *tc) 454{ 455 uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 456 457 Addr vaddr = req->getVaddr(); 458 TlbEntry *e; 459 460 assert(req->getAsi() == ASI_IMPLICIT); 461 462 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 463 vaddr, req->getSize()); 464 465 // Be fast if we can! 466 if (cacheValid && cacheState == tlbdata) { 467 if (cacheEntry) { 468 if (cacheEntry->range.va < vaddr + sizeof(MachInst) && 469 cacheEntry->range.va + cacheEntry->range.size >= vaddr) { 470 req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) | 471 vaddr & cacheEntry->pte.size()-1 ); 472 return NoFault; 473 } 474 } else { 475 req->setPaddr(vaddr & PAddrImplMask); 476 return NoFault; 477 } 478 } 479 480 bool hpriv = bits(tlbdata,0,0); 481 bool red = bits(tlbdata,1,1); 482 bool priv = bits(tlbdata,2,2); 483 bool addr_mask = bits(tlbdata,3,3); 484 bool lsu_im = bits(tlbdata,4,4); 485 486 int part_id = bits(tlbdata,15,8); 487 int tl = bits(tlbdata,18,16); 488 int pri_context = bits(tlbdata,47,32); 489 int context; 490 ContextType ct; 491 int asi; 492 bool real = false; 493 494 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 495 priv, hpriv, red, lsu_im, part_id); 496 497 if (tl > 0) { 498 asi = ASI_N; 499 ct = Nucleus; 500 context = 0; 501 } else { 502 asi = ASI_P; 503 ct = Primary; 504 context = pri_context; 505 } 506 507 if ( hpriv || red ) { 508 cacheValid = true; 509 cacheState = tlbdata; 510 cacheEntry = NULL; 511 req->setPaddr(vaddr & PAddrImplMask); 512 return NoFault; 513 } 514 515 // If the access is unaligned trap 516 if (vaddr & 0x3) { 517 writeSfsr(tc, false, ct, false, OtherFault, asi); 518 return new MemAddressNotAligned; 519 } 520 521 if (addr_mask) 522 vaddr = vaddr & VAddrAMask; 523 524 if (!validVirtualAddress(vaddr, addr_mask)) { 525 writeSfsr(tc, false, ct, false, VaOutOfRange, asi); 526 return new InstructionAccessException; 527 } 528 529 if (!lsu_im) { 530 e = lookup(vaddr, part_id, true); 531 real = true; 532 context = 0; 533 } else { 534 e = lookup(vaddr, part_id, false, context); 535 } 536 537 if (e == NULL || !e->valid) { 538 writeTagAccess(tc, vaddr, context); 539 if (real) 540 return new InstructionRealTranslationMiss; 541 else 542 return new FastInstructionAccessMMUMiss; 543 } 544 545 // were not priviledged accesing priv page 546 if (!priv && e->pte.priv()) { 547 writeTagAccess(tc, vaddr, context); 548 writeSfsr(tc, false, ct, false, PrivViolation, asi); 549 return new InstructionAccessException; 550 } 551 552 // cache translation date for next translation 553 cacheValid = true; 554 cacheState = tlbdata; 555 cacheEntry = e; 556 557 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 558 vaddr & e->pte.size()-1 ); 559 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 560 return NoFault; 561} 562 563 564 565Fault 566DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 567{ 568 /* @todo this could really use some profiling and fixing to make it faster! */ 569 uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 570 Addr vaddr = req->getVaddr(); 571 Addr size = req->getSize(); 572 ASI asi; 573 asi = (ASI)req->getAsi(); 574 bool implicit = false; 575 bool hpriv = bits(tlbdata,0,0); 576 577 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 578 vaddr, size, asi); 579 580 if (asi == ASI_IMPLICIT) 581 implicit = true; 582 583 if (hpriv && implicit) { 584 req->setPaddr(vaddr & PAddrImplMask); 585 return NoFault; 586 } 587 588 // Be fast if we can! 589 if (cacheValid && cacheState == tlbdata) { 590 if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size && 591 cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr && 592 (!write || cacheEntry[0]->pte.writable())) { 593 req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) | 594 vaddr & cacheEntry[0]->pte.size()-1 ); 595 return NoFault; 596 } 597 if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size && 598 cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr && 599 (!write || cacheEntry[1]->pte.writable())) { 600 req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) | 601 vaddr & cacheEntry[1]->pte.size()-1 ); 602 return NoFault; 603 } 604 } 605 606 bool red = bits(tlbdata,1,1); 607 bool priv = bits(tlbdata,2,2); 608 bool addr_mask = bits(tlbdata,3,3); 609 bool lsu_dm = bits(tlbdata,5,5); 610 611 int part_id = bits(tlbdata,15,8); 612 int tl = bits(tlbdata,18,16); 613 int pri_context = bits(tlbdata,47,32); 614 int sec_context = bits(tlbdata,63,48); 615 616 bool real = false; 617 ContextType ct = Primary; 618 int context = 0; 619 620 TlbEntry *e; 621 622 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 623 priv, hpriv, red, lsu_dm, part_id); 624 625 if (implicit) { 626 if (tl > 0) { 627 asi = ASI_N; 628 ct = Nucleus; 629 context = 0; 630 } else { 631 asi = ASI_P; 632 ct = Primary; 633 context = pri_context; 634 } 635 } else { 636 // We need to check for priv level/asi priv 637 if (!priv && !hpriv && !AsiIsUnPriv(asi)) { 638 // It appears that context should be Nucleus in these cases? 639 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 640 return new PrivilegedAction; 641 } 642 643 if (!hpriv && AsiIsHPriv(asi)) { 644 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 645 return new DataAccessException; 646 } 647 648 if (AsiIsPrimary(asi)) { 649 context = pri_context; 650 ct = Primary; 651 } else if (AsiIsSecondary(asi)) { 652 context = sec_context; 653 ct = Secondary; 654 } else if (AsiIsNucleus(asi)) { 655 ct = Nucleus; 656 context = 0; 657 } else { // ???? 658 ct = Primary; 659 context = pri_context; 660 } 661 } 662 663 if (!implicit && asi != ASI_P && asi != ASI_S) { 664 if (AsiIsLittle(asi)) 665 panic("Little Endian ASIs not supported\n"); 666 if (AsiIsBlock(asi)) 667 panic("Block ASIs not supported\n"); 668 if (AsiIsNoFault(asi)) 669 panic("No Fault ASIs not supported\n"); 670 671 if (AsiIsPartialStore(asi)) 672 panic("Partial Store ASIs not supported\n"); 673 if (AsiIsInterrupt(asi)) 674 panic("Interrupt ASIs not supported\n"); 675 676 if (AsiIsMmu(asi)) 677 goto handleMmuRegAccess; 678 if (AsiIsScratchPad(asi)) 679 goto handleScratchRegAccess; 680 if (AsiIsQueue(asi)) 681 goto handleQueueRegAccess; 682 if (AsiIsSparcError(asi)) 683 goto handleSparcErrorRegAccess; 684 685 if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) && 686 !AsiIsTwin(asi)) 687 panic("Accessing ASI %#X. Should we?\n", asi); 688 } 689 690 // If the asi is unaligned trap 691 if (vaddr & size-1) { 692 writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); 693 return new MemAddressNotAligned; 694 } 695 696 if (addr_mask) 697 vaddr = vaddr & VAddrAMask; 698 699 if (!validVirtualAddress(vaddr, addr_mask)) { 700 writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi); 701 return new DataAccessException; 702 } 703 704 705 if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) { 706 real = true; 707 context = 0; 708 }; 709 710 if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 711 req->setPaddr(vaddr & PAddrImplMask); 712 return NoFault; 713 } 714 715 e = lookup(vaddr, part_id, real, context); 716 717 if (e == NULL || !e->valid) { 718 writeTagAccess(tc, vaddr, context); 719 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 720 if (real) 721 return new DataRealTranslationMiss; 722 else 723 return new FastDataAccessMMUMiss; 724 725 } 726 727 if (!priv && e->pte.priv()) { 728 writeTagAccess(tc, vaddr, context); 729 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 730 return new DataAccessException; 731 } 732 733 if (write && !e->pte.writable()) { 734 writeTagAccess(tc, vaddr, context); 735 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 736 return new FastDataAccessProtection; 737 } 738 739 if (e->pte.nofault() && !AsiIsNoFault(asi)) { 740 writeTagAccess(tc, vaddr, context); 741 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 742 return new DataAccessException; 743 } 744 745 if (e->pte.sideffect() && AsiIsNoFault(asi)) { 746 writeTagAccess(tc, vaddr, context); 747 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 748 return new DataAccessException; 749 } 750 751 752 if (e->pte.sideffect()) 753 req->setFlags(req->getFlags() | UNCACHEABLE); 754 755 // cache translation date for next translation 756 cacheState = tlbdata; 757 if (!cacheValid) { 758 cacheEntry[1] = NULL; 759 cacheEntry[0] = NULL; 760 } 761 762 if (cacheEntry[0] != e && cacheEntry[1] != e) { 763 cacheEntry[1] = cacheEntry[0]; 764 cacheEntry[0] = e; 765 cacheAsi[1] = cacheAsi[0]; 766 cacheAsi[0] = asi; 767 if (implicit) 768 cacheAsi[0] = (ASI)0; 769 } 770 cacheValid = true; 771 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 772 vaddr & e->pte.size()-1); 773 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 774 return NoFault; 775 /** Normal flow ends here. */ 776 777handleScratchRegAccess: 778 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 779 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 780 return new DataAccessException; 781 } 782 goto regAccessOk; 783 784handleQueueRegAccess: 785 if (!priv && !hpriv) { 786 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 787 return new PrivilegedAction; 788 } 789 if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) { 790 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 791 return new DataAccessException; 792 } 793 goto regAccessOk; 794 795handleSparcErrorRegAccess: 796 if (!hpriv) { 797 if (priv) { 798 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 799 return new DataAccessException; 800 } else { 801 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 802 return new PrivilegedAction; 803 } 804 } 805 goto regAccessOk; 806 807 808regAccessOk: 809handleMmuRegAccess: 810 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 811 req->setMmapedIpr(true); 812 req->setPaddr(req->getVaddr()); 813 return NoFault; 814}; 815 816Tick 817DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 818{ 819 Addr va = pkt->getAddr(); 820 ASI asi = (ASI)pkt->req->getAsi(); 821 uint64_t temp, data; 822 uint64_t tsbtemp, cnftemp; 823 824 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 825 (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 826 827 switch (asi) { 828 case ASI_LSU_CONTROL_REG: 829 assert(va == 0); 830 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL)); 831 break; 832 case ASI_MMU: 833 switch (va) { 834 case 0x8: 835 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT)); 836 break; 837 case 0x10: 838 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT)); 839 break; 840 default: 841 goto doMmuReadError; 842 } 843 break; 844 case ASI_QUEUE: 845 pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 846 (va >> 4) - 0x3c)); 847 break; 848 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 849 assert(va == 0); 850 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0)); 851 break; 852 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 853 assert(va == 0); 854 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1)); 855 break; 856 case ASI_DMMU_CTXT_ZERO_CONFIG: 857 assert(va == 0); 858 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG)); 859 break; 860 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 861 assert(va == 0); 862 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0)); 863 break; 864 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 865 assert(va == 0); 866 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1)); 867 break; 868 case ASI_IMMU_CTXT_ZERO_CONFIG: 869 assert(va == 0); 870 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG)); 871 break; 872 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 873 assert(va == 0); 874 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0)); 875 break; 876 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 877 assert(va == 0); 878 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1)); 879 break; 880 case ASI_DMMU_CTXT_NONZERO_CONFIG: 881 assert(va == 0); 882 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); 883 break; 884 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 885 assert(va == 0); 886 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0)); 887 break; 888 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 889 assert(va == 0); 890 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1)); 891 break; 892 case ASI_IMMU_CTXT_NONZERO_CONFIG: 893 assert(va == 0); 894 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); 895 break; 896 case ASI_SPARC_ERROR_STATUS_REG: 897 warn("returning 0 for SPARC ERROR regsiter read\n"); 898 pkt->set((uint64_t)0); 899 break; 900 case ASI_HYP_SCRATCHPAD: 901 case ASI_SCRATCHPAD: 902 pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 903 break; 904 case ASI_IMMU: 905 switch (va) { 906 case 0x0: 907 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 908 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 909 break; 910 case 0x18: 911 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR)); 912 break; 913 case 0x30: 914 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS)); 915 break; 916 default: 917 goto doMmuReadError; 918 } 919 break; 920 case ASI_DMMU: 921 switch (va) { 922 case 0x0: 923 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 924 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 925 break; 926 case 0x18: 927 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR)); 928 break; 929 case 0x20: 930 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR)); 931 break; 932 case 0x30: 933 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS)); 934 break; 935 case 0x80: 936 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID)); 937 break; 938 default: 939 goto doMmuReadError; 940 } 941 break; 942 case ASI_DMMU_TSB_PS0_PTR_REG: 943 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 944 if (bits(temp,12,0) == 0) { 945 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0); 946 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG); 947 } else { 948 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0); 949 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG); 950 } 951 data = mbits(tsbtemp,63,13); 952 data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 953 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 954 pkt->set(data); 955 break; 956 case ASI_DMMU_TSB_PS1_PTR_REG: 957 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 958 if (bits(temp,12,0) == 0) { 959 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1); 960 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG); 961 } else { 962 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1); 963 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG); 964 } 965 data = mbits(tsbtemp,63,13); 966 if (bits(tsbtemp,12,12)) 967 data |= ULL(1) << (13+bits(tsbtemp,3,0)); 968 data |= temp >> (9 + bits(cnftemp,10,8) * 3) & 969 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 970 pkt->set(data); 971 break; 972 case ASI_IMMU_TSB_PS0_PTR_REG: 973 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 974 if (bits(temp,12,0) == 0) { 975 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0); 976 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG); 977 } else { 978 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0); 979 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG); 980 } 981 data = mbits(tsbtemp,63,13); 982 data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 983 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 984 pkt->set(data); 985 break; 986 case ASI_IMMU_TSB_PS1_PTR_REG: 987 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 988 if (bits(temp,12,0) == 0) { 989 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1); 990 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG); 991 } else { 992 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1); 993 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG); 994 } 995 data = mbits(tsbtemp,63,13); 996 if (bits(tsbtemp,12,12)) 997 data |= ULL(1) << (13+bits(tsbtemp,3,0)); 998 data |= temp >> (9 + bits(cnftemp,10,8) * 3) & 999 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 1000 pkt->set(data); 1001 break; 1002 1003 default: 1004doMmuReadError: 1005 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 1006 (uint32_t)asi, va); 1007 } 1008 pkt->result = Packet::Success; 1009 return tc->getCpuPtr()->cycles(1); 1010} 1011 1012Tick 1013DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 1014{ 1015 uint64_t data = gtoh(pkt->get<uint64_t>()); 1016 Addr va = pkt->getAddr(); 1017 ASI asi = (ASI)pkt->req->getAsi(); 1018 1019 Addr ta_insert; 1020 Addr va_insert; 1021 Addr ct_insert; 1022 int part_insert; 1023 int entry_insert = -1; 1024 bool real_insert; 1025 bool ignore; 1026 int part_id; 1027 int ctx_id; 1028 PageTableEntry pte; 1029 1030 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 1031 (uint32_t)asi, va, data); 1032 1033 switch (asi) { 1034 case ASI_LSU_CONTROL_REG: 1035 assert(va == 0); 1036 tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data); 1037 break; 1038 case ASI_MMU: 1039 switch (va) { 1040 case 0x8: 1041 tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data); 1042 break; 1043 case 0x10: 1044 tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data); 1045 break; 1046 default: 1047 goto doMmuWriteError; 1048 } 1049 break; 1050 case ASI_QUEUE: 1051 assert(mbits(data,13,6) == data); 1052 tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 1053 (va >> 4) - 0x3c, data); 1054 break; 1055 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 1056 assert(va == 0); 1057 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data); 1058 break; 1059 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 1060 assert(va == 0); 1061 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data); 1062 break; 1063 case ASI_DMMU_CTXT_ZERO_CONFIG: 1064 assert(va == 0); 1065 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data); 1066 break; 1067 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 1068 assert(va == 0); 1069 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data); 1070 break; 1071 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 1072 assert(va == 0); 1073 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data); 1074 break; 1075 case ASI_IMMU_CTXT_ZERO_CONFIG: 1076 assert(va == 0); 1077 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data); 1078 break; 1079 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 1080 assert(va == 0); 1081 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data); 1082 break; 1083 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 1084 assert(va == 0); 1085 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data); 1086 break; 1087 case ASI_DMMU_CTXT_NONZERO_CONFIG: 1088 assert(va == 0); 1089 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data); 1090 break; 1091 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 1092 assert(va == 0); 1093 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data); 1094 break; 1095 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 1096 assert(va == 0); 1097 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data); 1098 break; 1099 case ASI_IMMU_CTXT_NONZERO_CONFIG: 1100 assert(va == 0); 1101 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data); 1102 break; 1103 case ASI_SPARC_ERROR_EN_REG: 1104 case ASI_SPARC_ERROR_STATUS_REG: 1105 warn("Ignoring write to SPARC ERROR regsiter\n"); 1106 break; 1107 case ASI_HYP_SCRATCHPAD: 1108 case ASI_SCRATCHPAD: 1109 tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 1110 break; 1111 case ASI_IMMU: 1112 switch (va) { 1113 case 0x18: 1114 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data); 1115 break; 1116 case 0x30: 1117 sext<59>(bits(data, 59,0)); 1118 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data); 1119 break; 1120 default: 1121 goto doMmuWriteError; 1122 } 1123 break; 1124 case ASI_ITLB_DATA_ACCESS_REG: 1125 entry_insert = bits(va, 8,3); 1126 case ASI_ITLB_DATA_IN_REG: 1127 assert(entry_insert != -1 || mbits(va,10,9) == va); 1128 ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 1129 va_insert = mbits(ta_insert, 63,13); 1130 ct_insert = mbits(ta_insert, 12,0); 1131 part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 1132 real_insert = bits(va, 9,9); 1133 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 1134 PageTableEntry::sun4u); 1135 tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 1136 pte, entry_insert); 1137 break; 1138 case ASI_DTLB_DATA_ACCESS_REG: 1139 entry_insert = bits(va, 8,3); 1140 case ASI_DTLB_DATA_IN_REG: 1141 assert(entry_insert != -1 || mbits(va,10,9) == va); 1142 ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 1143 va_insert = mbits(ta_insert, 63,13); 1144 ct_insert = mbits(ta_insert, 12,0); 1145 part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 1146 real_insert = bits(va, 9,9); 1147 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 1148 PageTableEntry::sun4u); 1149 insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert); 1150 break; 1151 case ASI_IMMU_DEMAP: 1152 ignore = false; 1153 ctx_id = -1; 1154 part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 1155 switch (bits(va,5,4)) { 1156 case 0: 1157 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT); 1158 break; 1159 case 1: 1160 ignore = true; 1161 break; 1162 case 3: 1163 ctx_id = 0; 1164 break; 1165 default: 1166 ignore = true; 1167 } 1168 1169 switch(bits(va,7,6)) { 1170 case 0: // demap page 1171 if (!ignore) 1172 tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 1173 bits(va,9,9), ctx_id); 1174 break; 1175 case 1: //demap context 1176 if (!ignore) 1177 tc->getITBPtr()->demapContext(part_id, ctx_id); 1178 break; 1179 case 2: 1180 tc->getITBPtr()->demapAll(part_id); 1181 break; 1182 default: 1183 panic("Invalid type for IMMU demap\n"); 1184 } 1185 break; 1186 case ASI_DMMU: 1187 switch (va) { 1188 case 0x18: 1189 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data); 1190 break; 1191 case 0x30: 1192 sext<59>(bits(data, 59,0)); 1193 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data); 1194 break; 1195 case 0x80: 1196 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data); 1197 break; 1198 default: 1199 goto doMmuWriteError; 1200 } 1201 break; 1202 case ASI_DMMU_DEMAP: 1203 ignore = false; 1204 ctx_id = -1; 1205 part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 1206 switch (bits(va,5,4)) { 1207 case 0: 1208 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT); 1209 break; 1210 case 1: 1211 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT); 1212 break; 1213 case 3: 1214 ctx_id = 0; 1215 break; 1216 default: 1217 ignore = true; 1218 } 1219 1220 switch(bits(va,7,6)) { 1221 case 0: // demap page 1222 if (!ignore) 1223 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 1224 break; 1225 case 1: //demap context 1226 if (!ignore) 1227 demapContext(part_id, ctx_id); 1228 break; 1229 case 2: 1230 demapAll(part_id); 1231 break; 1232 default: 1233 panic("Invalid type for IMMU demap\n"); 1234 } 1235 break; 1236 default: 1237doMmuWriteError: 1238 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 1239 (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 1240 } 1241 pkt->result = Packet::Success; 1242 return tc->getCpuPtr()->cycles(1); 1243} 1244 1245void 1246TLB::serialize(std::ostream &os) 1247{ 1248 panic("Need to implement serialize tlb for SPARC\n"); 1249} 1250 1251void 1252TLB::unserialize(Checkpoint *cp, const std::string §ion) 1253{ 1254 panic("Need to implement unserialize tlb for SPARC\n"); 1255} 1256 1257 1258DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) 1259 1260BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 1261 1262 Param<int> size; 1263 1264END_DECLARE_SIM_OBJECT_PARAMS(ITB) 1265 1266BEGIN_INIT_SIM_OBJECT_PARAMS(ITB) 1267 1268 INIT_PARAM_DFLT(size, "TLB size", 48) 1269 1270END_INIT_SIM_OBJECT_PARAMS(ITB) 1271 1272 1273CREATE_SIM_OBJECT(ITB) 1274{ 1275 return new ITB(getInstanceName(), size); 1276} 1277 1278REGISTER_SIM_OBJECT("SparcITB", ITB) 1279 1280BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) 1281 1282 Param<int> size; 1283 1284END_DECLARE_SIM_OBJECT_PARAMS(DTB) 1285 1286BEGIN_INIT_SIM_OBJECT_PARAMS(DTB) 1287 1288 INIT_PARAM_DFLT(size, "TLB size", 64) 1289 1290END_INIT_SIM_OBJECT_PARAMS(DTB) 1291 1292 1293CREATE_SIM_OBJECT(DTB) 1294{ 1295 return new DTB(getInstanceName(), size); 1296} 1297 1298REGISTER_SIM_OBJECT("SparcDTB", DTB) 1299} 1300