tlb.cc revision 3929:3640569369a5 
1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Ali Saidi
29 */
30
31#include "arch/sparc/asi.hh"
32#include "arch/sparc/miscregfile.hh"
33#include "arch/sparc/tlb.hh"
34#include "base/bitfield.hh"
35#include "base/trace.hh"
36#include "cpu/thread_context.hh"
37#include "cpu/base.hh"
38#include "mem/packet_access.hh"
39#include "mem/request.hh"
40#include "sim/builder.hh"
41
42/* @todo remove some of the magic constants.  -- ali
43 * */
44namespace SparcISA
45{
46
47TLB::TLB(const std::string &name, int s)
48    : SimObject(name), size(s), usedEntries(0), lastReplaced(0),
49      cacheValid(false)
50{
51    // To make this work you'll have to change the hypervisor and OS
52    if (size > 64)
53        fatal("SPARC T1 TLB registers don't support more than 64 TLB entries.");
54
55    tlb = new TlbEntry[size];
56    memset(tlb, 0, sizeof(TlbEntry) * size);
57
58    for (int x = 0; x < size; x++)
59        freeList.push_back(&tlb[x]);
60}
61
62void
63TLB::clearUsedBits()
64{
65    MapIter i;
66    for (i = lookupTable.begin(); i != lookupTable.end(); i++) {
67        TlbEntry *t = i->second;
68        if (!t->pte.locked()) {
69            t->used = false;
70            usedEntries--;
71        }
72    }
73}
74
75
76void
77TLB::insert(Addr va, int partition_id, int context_id, bool real,
78        const PageTableEntry& PTE, int entry)
79{
80
81
82    MapIter i;
83    TlbEntry *new_entry = NULL;
84//    TlbRange tr;
85    int x;
86
87    cacheValid = false;
88    va &= ~(PTE.size()-1);
89 /*   tr.va = va;
90    tr.size = PTE.size() - 1;
91    tr.contextId = context_id;
92    tr.partitionId = partition_id;
93    tr.real = real;
94*/
95
96    DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n",
97            va, PTE.paddr(), partition_id, context_id, (int)real, entry);
98
99    // Demap any entry that conflicts
100    for (x = 0; x < size; x++) {
101        if (tlb[x].range.real == real &&
102            tlb[x].range.partitionId == partition_id &&
103            tlb[x].range.va < va + PTE.size() - 1 &&
104            tlb[x].range.va + tlb[x].range.size >= va &&
105            (real || tlb[x].range.contextId == context_id ))
106        {
107            if (tlb[x].valid) {
108                freeList.push_front(&tlb[x]);
109                DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x);
110
111                tlb[x].valid = false;
112                if (tlb[x].used) {
113                    tlb[x].used = false;
114                    usedEntries--;
115                }
116                lookupTable.erase(tlb[x].range);
117            }
118        }
119    }
120
121
122/*
123    i = lookupTable.find(tr);
124    if (i != lookupTable.end()) {
125        i->second->valid = false;
126        if (i->second->used) {
127            i->second->used = false;
128            usedEntries--;
129        }
130        freeList.push_front(i->second);
131        DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n",
132                i->second);
133        lookupTable.erase(i);
134    }
135*/
136
137    if (entry != -1) {
138        assert(entry < size && entry >= 0);
139        new_entry = &tlb[entry];
140    } else {
141        if (!freeList.empty()) {
142            new_entry = freeList.front();
143        } else {
144            x = lastReplaced;
145            do {
146                ++x;
147                if (x == size)
148                    x = 0;
149                if (x == lastReplaced)
150                    goto insertAllLocked;
151            } while (tlb[x].pte.locked());
152            lastReplaced = x;
153            new_entry = &tlb[x];
154        }
155        /*
156        for (x = 0; x < size; x++) {
157            if (!tlb[x].valid || !tlb[x].used)  {
158                new_entry = &tlb[x];
159                break;
160            }
161        }*/
162    }
163
164insertAllLocked:
165    // Update the last ently if their all locked
166    if (!new_entry) {
167        new_entry = &tlb[size-1];
168    }
169
170    freeList.remove(new_entry);
171    if (new_entry->valid && new_entry->used)
172        usedEntries--;
173    if (new_entry->valid)
174        lookupTable.erase(new_entry->range);
175
176
177    DPRINTF(TLB, "Using entry: %#X\n", new_entry);
178
179    assert(PTE.valid());
180    new_entry->range.va = va;
181    new_entry->range.size = PTE.size() - 1;
182    new_entry->range.partitionId = partition_id;
183    new_entry->range.contextId = context_id;
184    new_entry->range.real = real;
185    new_entry->pte = PTE;
186    new_entry->used = true;;
187    new_entry->valid = true;
188    usedEntries++;
189
190
191
192    i = lookupTable.insert(new_entry->range, new_entry);
193    assert(i != lookupTable.end());
194
195    // If all entries have there used bit set, clear it on them all, but the
196    // one we just inserted
197    if (usedEntries == size) {
198        clearUsedBits();
199        new_entry->used = true;
200        usedEntries++;
201    }
202
203}
204
205
206TlbEntry*
207TLB::lookup(Addr va, int partition_id, bool real, int context_id)
208{
209    MapIter i;
210    TlbRange tr;
211    TlbEntry *t;
212
213    DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n",
214            va, partition_id, context_id, real);
215    // Assemble full address structure
216    tr.va = va;
217    tr.size = MachineBytes;
218    tr.contextId = context_id;
219    tr.partitionId = partition_id;
220    tr.real = real;
221
222    // Try to find the entry
223    i = lookupTable.find(tr);
224    if (i == lookupTable.end()) {
225        DPRINTF(TLB, "TLB: No valid entry found\n");
226        return NULL;
227    }
228
229    // Mark the entries used bit and clear other used bits in needed
230    t = i->second;
231    DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(),
232            t->pte.size());
233    if (!t->used) {
234        t->used = true;
235        usedEntries++;
236        if (usedEntries == size) {
237            clearUsedBits();
238            t->used = true;
239            usedEntries++;
240        }
241    }
242
243    return t;
244}
245
246void
247TLB::dumpAll()
248{
249    MapIter i;
250    for (int x = 0; x < size; x++) {
251        if (tlb[x].valid) {
252           DPRINTFN("%4d:  %#2x:%#2x %c %#4x %#8x %#8x %#16x\n",
253                   x, tlb[x].range.partitionId, tlb[x].range.contextId,
254                   tlb[x].range.real ? 'R' : ' ', tlb[x].range.size,
255                   tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte());
256        }
257    }
258}
259
260void
261TLB::demapPage(Addr va, int partition_id, bool real, int context_id)
262{
263    TlbRange tr;
264    MapIter i;
265
266    DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n",
267            va, partition_id, context_id, real);
268
269    cacheValid = false;
270
271    // Assemble full address structure
272    tr.va = va;
273    tr.size = MachineBytes;
274    tr.contextId = context_id;
275    tr.partitionId = partition_id;
276    tr.real = real;
277
278    // Demap any entry that conflicts
279    i = lookupTable.find(tr);
280    if (i != lookupTable.end()) {
281        DPRINTF(IPR, "TLB: Demapped page\n");
282        i->second->valid = false;
283        if (i->second->used) {
284            i->second->used = false;
285            usedEntries--;
286        }
287        freeList.push_front(i->second);
288        DPRINTF(TLB, "Freeing TLB entry : %#X\n", i->second);
289        lookupTable.erase(i);
290    }
291}
292
293void
294TLB::demapContext(int partition_id, int context_id)
295{
296    int x;
297    DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n",
298            partition_id, context_id);
299    cacheValid = false;
300    for (x = 0; x < size; x++) {
301        if (tlb[x].range.contextId == context_id &&
302            tlb[x].range.partitionId == partition_id) {
303            if (tlb[x].valid == true) {
304                freeList.push_front(&tlb[x]);
305                DPRINTF(TLB, "Freeing TLB entry : %#X\n", &tlb[x]);
306            }
307            tlb[x].valid = false;
308            if (tlb[x].used) {
309                tlb[x].used = false;
310                usedEntries--;
311            }
312            lookupTable.erase(tlb[x].range);
313        }
314    }
315}
316
317void
318TLB::demapAll(int partition_id)
319{
320    int x;
321    DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id);
322    cacheValid = false;
323    for (x = 0; x < size; x++) {
324        if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) {
325            if (tlb[x].valid == true){
326                freeList.push_front(&tlb[x]);
327                DPRINTF(TLB, "Freeing TLB entry : %#X\n", &tlb[x]);
328            }
329            tlb[x].valid = false;
330            if (tlb[x].used) {
331                tlb[x].used = false;
332                usedEntries--;
333            }
334            lookupTable.erase(tlb[x].range);
335        }
336    }
337}
338
339void
340TLB::invalidateAll()
341{
342    int x;
343    cacheValid = false;
344
345    freeList.clear();
346    lookupTable.clear();
347    for (x = 0; x < size; x++) {
348        if (tlb[x].valid == true)
349            freeList.push_back(&tlb[x]);
350        tlb[x].valid = false;
351        tlb[x].used = false;
352    }
353    usedEntries = 0;
354}
355
356uint64_t
357TLB::TteRead(int entry) {
358    if (entry >= size)
359        panic("entry: %d\n", entry);
360
361    assert(entry < size);
362    if (tlb[entry].valid)
363        return tlb[entry].pte();
364    else
365        return (uint64_t)-1ll;
366}
367
368uint64_t
369TLB::TagRead(int entry) {
370    assert(entry < size);
371    uint64_t tag;
372    if (!tlb[entry].valid)
373        return (uint64_t)-1ll;
374
375    tag = tlb[entry].range.contextId;
376    tag |= tlb[entry].range.va;
377    tag |= (uint64_t)tlb[entry].range.partitionId << 61;
378    tag |= tlb[entry].range.real ? ULL(1) << 60 : 0;
379    tag |= (uint64_t)~tlb[entry].pte._size() << 56;
380    return tag;
381}
382
383bool
384TLB::validVirtualAddress(Addr va, bool am)
385{
386    if (am)
387        return true;
388    if (va >= StartVAddrHole && va <= EndVAddrHole)
389        return false;
390    return true;
391}
392
393void
394TLB::writeSfsr(ThreadContext *tc, int reg,  bool write, ContextType ct,
395        bool se, FaultTypes ft, int asi)
396{
397    uint64_t sfsr;
398    sfsr = tc->readMiscReg(reg);
399
400    if (sfsr & 0x1)
401        sfsr = 0x3;
402    else
403        sfsr = 1;
404
405    if (write)
406        sfsr |= 1 << 2;
407    sfsr |= ct << 4;
408    if (se)
409        sfsr |= 1 << 6;
410    sfsr |= ft << 7;
411    sfsr |= asi << 16;
412    tc->setMiscRegWithEffect(reg, sfsr);
413}
414
415void
416TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context)
417{
418    DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n",
419            va, context, mbits(va, 63,13) | mbits(context,12,0));
420
421    tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0));
422}
423
424void
425ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct,
426        bool se, FaultTypes ft, int asi)
427{
428    DPRINTF(TLB, "TLB: ITB Fault:  w=%d ct=%d ft=%d asi=%d\n",
429             (int)write, ct, ft, asi);
430    TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi);
431}
432
433void
434ITB::writeTagAccess(ThreadContext *tc, Addr va, int context)
435{
436    TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context);
437}
438
439void
440DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct,
441        bool se, FaultTypes ft, int asi)
442{
443    DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n",
444            a, (int)write, ct, ft, asi);
445    TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi);
446    tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a);
447}
448
449void
450DTB::writeTagAccess(ThreadContext *tc, Addr va, int context)
451{
452    TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context);
453}
454
455
456
457Fault
458ITB::translate(RequestPtr &req, ThreadContext *tc)
459{
460    uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
461
462    Addr vaddr = req->getVaddr();
463    TlbEntry *e;
464
465    assert(req->getAsi() == ASI_IMPLICIT);
466
467    DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n",
468            vaddr, req->getSize());
469
470    // Be fast if we can!
471    if (cacheValid && cacheState == tlbdata) {
472        if (cacheEntry) {
473            if (cacheEntry->range.va < vaddr + sizeof(MachInst) &&
474                cacheEntry->range.va + cacheEntry->range.size >= vaddr) {
475                    req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) |
476                                  vaddr & cacheEntry->pte.size()-1 );
477                    return NoFault;
478            }
479        } else {
480            req->setPaddr(vaddr & PAddrImplMask);
481            return NoFault;
482        }
483    }
484
485    bool hpriv = bits(tlbdata,0,0);
486    bool red = bits(tlbdata,1,1);
487    bool priv = bits(tlbdata,2,2);
488    bool addr_mask = bits(tlbdata,3,3);
489    bool lsu_im = bits(tlbdata,4,4);
490
491    int part_id = bits(tlbdata,15,8);
492    int tl = bits(tlbdata,18,16);
493    int pri_context = bits(tlbdata,47,32);
494    int context;
495    ContextType ct;
496    int asi;
497    bool real = false;
498
499    DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n",
500           priv, hpriv, red, lsu_im, part_id);
501
502    if (tl > 0) {
503        asi = ASI_N;
504        ct = Nucleus;
505        context = 0;
506    } else {
507        asi = ASI_P;
508        ct = Primary;
509        context = pri_context;
510    }
511
512    if ( hpriv || red ) {
513        cacheValid = true;
514        cacheState = tlbdata;
515        cacheEntry = NULL;
516        req->setPaddr(vaddr & PAddrImplMask);
517        return NoFault;
518    }
519
520    // If the access is unaligned trap
521    if (vaddr & 0x3) {
522        writeSfsr(tc, false, ct, false, OtherFault, asi);
523        return new MemAddressNotAligned;
524    }
525
526    if (addr_mask)
527        vaddr = vaddr & VAddrAMask;
528
529    if (!validVirtualAddress(vaddr, addr_mask)) {
530        writeSfsr(tc, false, ct, false, VaOutOfRange, asi);
531        return new InstructionAccessException;
532    }
533
534    if (!lsu_im) {
535        e = lookup(vaddr, part_id, true);
536        real = true;
537        context = 0;
538    } else {
539        e = lookup(vaddr, part_id, false, context);
540    }
541
542    if (e == NULL || !e->valid) {
543        writeTagAccess(tc, vaddr, context);
544        if (real)
545            return new InstructionRealTranslationMiss;
546        else
547            return new FastInstructionAccessMMUMiss;
548    }
549
550    // were not priviledged accesing priv page
551    if (!priv && e->pte.priv()) {
552        writeTagAccess(tc, vaddr, context);
553        writeSfsr(tc, false, ct, false, PrivViolation, asi);
554        return new InstructionAccessException;
555    }
556
557    // cache translation date for next translation
558    cacheValid = true;
559    cacheState = tlbdata;
560    cacheEntry = e;
561
562    req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
563                  vaddr & e->pte.size()-1 );
564    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
565    return NoFault;
566}
567
568
569
570Fault
571DTB::translate(RequestPtr &req, ThreadContext *tc, bool write)
572{
573    /* @todo this could really use some profiling and fixing to make it faster! */
574    uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA);
575    Addr vaddr = req->getVaddr();
576    Addr size = req->getSize();
577    ASI asi;
578    asi = (ASI)req->getAsi();
579    bool implicit = false;
580    bool hpriv = bits(tlbdata,0,0);
581
582    DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n",
583            vaddr, size, asi);
584
585    if (lookupTable.size() != 64 - freeList.size())
586       panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(),
587               freeList.size());
588    if (asi == ASI_IMPLICIT)
589        implicit = true;
590
591    if (hpriv && implicit) {
592        req->setPaddr(vaddr & PAddrImplMask);
593        return NoFault;
594    }
595
596    // Be fast if we can!
597    if (cacheValid &&  cacheState == tlbdata) {
598        if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size &&
599            cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr &&
600            (!write || cacheEntry[0]->pte.writable())) {
601                req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) |
602                              vaddr & cacheEntry[0]->pte.size()-1 );
603                return NoFault;
604        }
605        if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size &&
606            cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr &&
607            (!write || cacheEntry[1]->pte.writable())) {
608                req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) |
609                              vaddr & cacheEntry[1]->pte.size()-1 );
610                return NoFault;
611        }
612    }
613
614    bool red = bits(tlbdata,1,1);
615    bool priv = bits(tlbdata,2,2);
616    bool addr_mask = bits(tlbdata,3,3);
617    bool lsu_dm = bits(tlbdata,5,5);
618
619    int part_id = bits(tlbdata,15,8);
620    int tl = bits(tlbdata,18,16);
621    int pri_context = bits(tlbdata,47,32);
622    int sec_context = bits(tlbdata,63,48);
623
624    bool real = false;
625    ContextType ct = Primary;
626    int context = 0;
627
628    TlbEntry *e;
629
630    DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n",
631           priv, hpriv, red, lsu_dm, part_id);
632
633    if (implicit) {
634        if (tl > 0) {
635            asi = ASI_N;
636            ct = Nucleus;
637            context = 0;
638        } else {
639            asi = ASI_P;
640            ct = Primary;
641            context = pri_context;
642        }
643    } else {
644        // We need to check for priv level/asi priv
645        if (!priv && !hpriv && !AsiIsUnPriv(asi)) {
646            // It appears that context should be Nucleus in these cases?
647            writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
648            return new PrivilegedAction;
649        }
650
651        if (!hpriv && AsiIsHPriv(asi)) {
652            writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi);
653            return new DataAccessException;
654        }
655
656        if (AsiIsPrimary(asi)) {
657            context = pri_context;
658            ct = Primary;
659        } else if (AsiIsSecondary(asi)) {
660            context = sec_context;
661            ct = Secondary;
662        } else if (AsiIsNucleus(asi)) {
663            ct = Nucleus;
664            context = 0;
665        } else {  // ????
666            ct = Primary;
667            context = pri_context;
668        }
669    }
670
671    if (!implicit && asi != ASI_P && asi != ASI_S) {
672        if (AsiIsLittle(asi))
673            panic("Little Endian ASIs not supported\n");
674        if (AsiIsBlock(asi))
675            panic("Block ASIs not supported\n");
676        if (AsiIsNoFault(asi))
677            panic("No Fault ASIs not supported\n");
678
679        if (AsiIsPartialStore(asi))
680            panic("Partial Store ASIs not supported\n");
681        if (AsiIsInterrupt(asi))
682            panic("Interrupt ASIs not supported\n");
683
684        if (AsiIsMmu(asi))
685            goto handleMmuRegAccess;
686        if (AsiIsScratchPad(asi))
687            goto handleScratchRegAccess;
688        if (AsiIsQueue(asi))
689            goto handleQueueRegAccess;
690        if (AsiIsSparcError(asi))
691            goto handleSparcErrorRegAccess;
692
693        if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) &&
694                !AsiIsTwin(asi))
695            panic("Accessing ASI %#X. Should we?\n", asi);
696    }
697
698    // If the asi is unaligned trap
699    if (vaddr & size-1) {
700        writeSfr(tc, vaddr, false, ct, false, OtherFault, asi);
701        return new MemAddressNotAligned;
702    }
703
704    if (addr_mask)
705        vaddr = vaddr & VAddrAMask;
706
707    if (!validVirtualAddress(vaddr, addr_mask)) {
708        writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi);
709        return new DataAccessException;
710    }
711
712
713    if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) {
714        real = true;
715        context = 0;
716    };
717
718    if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) {
719        req->setPaddr(vaddr & PAddrImplMask);
720        return NoFault;
721    }
722
723    e = lookup(vaddr, part_id, real, context);
724
725    if (e == NULL || !e->valid) {
726        writeTagAccess(tc, vaddr, context);
727        DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n");
728        if (real)
729            return new DataRealTranslationMiss;
730        else
731            return new FastDataAccessMMUMiss;
732
733    }
734
735    if (!priv && e->pte.priv()) {
736        writeTagAccess(tc, vaddr, context);
737        writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi);
738        return new DataAccessException;
739    }
740
741    if (write && !e->pte.writable()) {
742        writeTagAccess(tc, vaddr, context);
743        writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi);
744        return new FastDataAccessProtection;
745    }
746
747    if (e->pte.nofault() && !AsiIsNoFault(asi)) {
748        writeTagAccess(tc, vaddr, context);
749        writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi);
750        return new DataAccessException;
751    }
752
753    if (e->pte.sideffect() && AsiIsNoFault(asi)) {
754        writeTagAccess(tc, vaddr, context);
755        writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), SideEffect, asi);
756        return new DataAccessException;
757    }
758
759
760    if (e->pte.sideffect())
761        req->setFlags(req->getFlags() | UNCACHEABLE);
762
763    // cache translation date for next translation
764    cacheState = tlbdata;
765    if (!cacheValid) {
766        cacheEntry[1] = NULL;
767        cacheEntry[0] = NULL;
768    }
769
770    if (cacheEntry[0] != e && cacheEntry[1] != e) {
771        cacheEntry[1] = cacheEntry[0];
772        cacheEntry[0] = e;
773        cacheAsi[1] = cacheAsi[0];
774        cacheAsi[0] = asi;
775        if (implicit)
776            cacheAsi[0] = (ASI)0;
777    }
778    cacheValid = true;
779    req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) |
780                  vaddr & e->pte.size()-1);
781    DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr());
782    return NoFault;
783    /** Normal flow ends here. */
784
785handleScratchRegAccess:
786    if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) {
787        writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
788        return new DataAccessException;
789    }
790    goto regAccessOk;
791
792handleQueueRegAccess:
793    if (!priv  && !hpriv) {
794        writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
795        return new PrivilegedAction;
796    }
797    if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) {
798        writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
799        return new DataAccessException;
800    }
801    goto regAccessOk;
802
803handleSparcErrorRegAccess:
804    if (!hpriv) {
805        if (priv) {
806            writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
807            return new DataAccessException;
808        } else {
809            writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi);
810            return new PrivilegedAction;
811        }
812    }
813    goto regAccessOk;
814
815
816regAccessOk:
817handleMmuRegAccess:
818    DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n");
819    req->setMmapedIpr(true);
820    req->setPaddr(req->getVaddr());
821    return NoFault;
822};
823
824Tick
825DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt)
826{
827    Addr va = pkt->getAddr();
828    ASI asi = (ASI)pkt->req->getAsi();
829    uint64_t temp, data;
830    uint64_t tsbtemp, cnftemp;
831
832    DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n",
833         (uint32_t)pkt->req->getAsi(), pkt->getAddr());
834
835    switch (asi) {
836      case ASI_LSU_CONTROL_REG:
837        assert(va == 0);
838        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL));
839        break;
840      case ASI_MMU:
841        switch (va) {
842          case 0x8:
843            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT));
844            break;
845          case 0x10:
846            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT));
847            break;
848          default:
849            goto doMmuReadError;
850        }
851        break;
852      case ASI_QUEUE:
853        pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
854                    (va >> 4) - 0x3c));
855        break;
856      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
857        assert(va == 0);
858        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0));
859        break;
860      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
861        assert(va == 0);
862        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1));
863        break;
864      case ASI_DMMU_CTXT_ZERO_CONFIG:
865        assert(va == 0);
866        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG));
867        break;
868      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
869        assert(va == 0);
870        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0));
871        break;
872      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
873        assert(va == 0);
874        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1));
875        break;
876      case ASI_IMMU_CTXT_ZERO_CONFIG:
877        assert(va == 0);
878        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG));
879        break;
880      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
881        assert(va == 0);
882        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0));
883        break;
884      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
885        assert(va == 0);
886        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1));
887        break;
888      case ASI_DMMU_CTXT_NONZERO_CONFIG:
889        assert(va == 0);
890        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG));
891        break;
892      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
893        assert(va == 0);
894        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0));
895        break;
896      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
897        assert(va == 0);
898        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1));
899        break;
900      case ASI_IMMU_CTXT_NONZERO_CONFIG:
901        assert(va == 0);
902        pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG));
903        break;
904      case ASI_SPARC_ERROR_STATUS_REG:
905        warn("returning 0 for  SPARC ERROR regsiter read\n");
906        pkt->set((uint64_t)0);
907        break;
908      case ASI_HYP_SCRATCHPAD:
909      case ASI_SCRATCHPAD:
910        pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3)));
911        break;
912      case ASI_IMMU:
913        switch (va) {
914          case 0x0:
915            temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
916            pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
917            break;
918          case 0x18:
919            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR));
920            break;
921          case 0x30:
922            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS));
923            break;
924          default:
925            goto doMmuReadError;
926        }
927        break;
928      case ASI_DMMU:
929        switch (va) {
930          case 0x0:
931            temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
932            pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48);
933            break;
934          case 0x18:
935            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR));
936            break;
937          case 0x20:
938            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR));
939            break;
940          case 0x30:
941            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS));
942            break;
943          case 0x80:
944            pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID));
945            break;
946          default:
947                goto doMmuReadError;
948        }
949        break;
950      case ASI_DMMU_TSB_PS0_PTR_REG:
951        temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
952        if (bits(temp,12,0) == 0) {
953            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0);
954            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
955        } else {
956            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0);
957            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
958        }
959        data = mbits(tsbtemp,63,13);
960        data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
961            mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
962        pkt->set(data);
963        break;
964      case ASI_DMMU_TSB_PS1_PTR_REG:
965        temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
966        if (bits(temp,12,0) == 0) {
967            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1);
968            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG);
969        } else {
970            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1);
971            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG);
972        }
973        data = mbits(tsbtemp,63,13);
974        if (bits(tsbtemp,12,12))
975            data |= ULL(1) << (13+bits(tsbtemp,3,0));
976        data |= temp >> (9 + bits(cnftemp,10,8) * 3) &
977            mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
978        pkt->set(data);
979        break;
980      case ASI_IMMU_TSB_PS0_PTR_REG:
981        temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
982        if (bits(temp,12,0) == 0) {
983            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0);
984            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
985        } else {
986            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0);
987            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
988        }
989        data = mbits(tsbtemp,63,13);
990        data |= temp >> (9 + bits(cnftemp,2,0) * 3) &
991            mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
992        pkt->set(data);
993        break;
994      case ASI_IMMU_TSB_PS1_PTR_REG:
995        temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
996        if (bits(temp,12,0) == 0) {
997            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1);
998            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG);
999        } else {
1000            tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1);
1001            cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG);
1002        }
1003        data = mbits(tsbtemp,63,13);
1004        if (bits(tsbtemp,12,12))
1005            data |= ULL(1) << (13+bits(tsbtemp,3,0));
1006        data |= temp >> (9 + bits(cnftemp,10,8) * 3) &
1007            mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4);
1008        pkt->set(data);
1009        break;
1010
1011      default:
1012doMmuReadError:
1013        panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n",
1014            (uint32_t)asi, va);
1015    }
1016    pkt->result = Packet::Success;
1017    return tc->getCpuPtr()->cycles(1);
1018}
1019
1020Tick
1021DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt)
1022{
1023    uint64_t data = gtoh(pkt->get<uint64_t>());
1024    Addr va = pkt->getAddr();
1025    ASI asi = (ASI)pkt->req->getAsi();
1026
1027    Addr ta_insert;
1028    Addr va_insert;
1029    Addr ct_insert;
1030    int part_insert;
1031    int entry_insert = -1;
1032    bool real_insert;
1033    bool ignore;
1034    int part_id;
1035    int ctx_id;
1036    PageTableEntry pte;
1037
1038    DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n",
1039         (uint32_t)asi, va, data);
1040
1041    switch (asi) {
1042      case ASI_LSU_CONTROL_REG:
1043        assert(va == 0);
1044        tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data);
1045        break;
1046      case ASI_MMU:
1047        switch (va) {
1048          case 0x8:
1049            tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data);
1050            break;
1051          case 0x10:
1052            tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data);
1053            break;
1054          default:
1055            goto doMmuWriteError;
1056        }
1057        break;
1058      case ASI_QUEUE:
1059        assert(mbits(data,13,6) == data);
1060        tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD +
1061                    (va >> 4) - 0x3c, data);
1062        break;
1063      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0:
1064        assert(va == 0);
1065        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data);
1066        break;
1067      case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1:
1068        assert(va == 0);
1069        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data);
1070        break;
1071      case ASI_DMMU_CTXT_ZERO_CONFIG:
1072        assert(va == 0);
1073        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data);
1074        break;
1075      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0:
1076        assert(va == 0);
1077        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data);
1078        break;
1079      case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1:
1080        assert(va == 0);
1081        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data);
1082        break;
1083      case ASI_IMMU_CTXT_ZERO_CONFIG:
1084        assert(va == 0);
1085        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data);
1086        break;
1087      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0:
1088        assert(va == 0);
1089        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data);
1090        break;
1091      case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1:
1092        assert(va == 0);
1093        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data);
1094        break;
1095      case ASI_DMMU_CTXT_NONZERO_CONFIG:
1096        assert(va == 0);
1097        tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data);
1098        break;
1099      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0:
1100        assert(va == 0);
1101        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data);
1102        break;
1103      case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1:
1104        assert(va == 0);
1105        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data);
1106        break;
1107      case ASI_IMMU_CTXT_NONZERO_CONFIG:
1108        assert(va == 0);
1109        tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data);
1110        break;
1111      case ASI_SPARC_ERROR_EN_REG:
1112      case ASI_SPARC_ERROR_STATUS_REG:
1113        warn("Ignoring write to SPARC ERROR regsiter\n");
1114        break;
1115      case ASI_HYP_SCRATCHPAD:
1116      case ASI_SCRATCHPAD:
1117        tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data);
1118        break;
1119      case ASI_IMMU:
1120        switch (va) {
1121          case 0x18:
1122            tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data);
1123            break;
1124          case 0x30:
1125            sext<59>(bits(data, 59,0));
1126            tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data);
1127            break;
1128          default:
1129            goto doMmuWriteError;
1130        }
1131        break;
1132      case ASI_ITLB_DATA_ACCESS_REG:
1133        entry_insert = bits(va, 8,3);
1134      case ASI_ITLB_DATA_IN_REG:
1135        assert(entry_insert != -1 || mbits(va,10,9) == va);
1136        ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS);
1137        va_insert = mbits(ta_insert, 63,13);
1138        ct_insert = mbits(ta_insert, 12,0);
1139        part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1140        real_insert = bits(va, 9,9);
1141        pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1142                PageTableEntry::sun4u);
1143        tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert,
1144                pte, entry_insert);
1145        break;
1146      case ASI_DTLB_DATA_ACCESS_REG:
1147        entry_insert = bits(va, 8,3);
1148      case ASI_DTLB_DATA_IN_REG:
1149        assert(entry_insert != -1 || mbits(va,10,9) == va);
1150        ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS);
1151        va_insert = mbits(ta_insert, 63,13);
1152        ct_insert = mbits(ta_insert, 12,0);
1153        part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1154        real_insert = bits(va, 9,9);
1155        pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v :
1156                PageTableEntry::sun4u);
1157        insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert);
1158        break;
1159      case ASI_IMMU_DEMAP:
1160        ignore = false;
1161        ctx_id = -1;
1162        part_id =  tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1163        switch (bits(va,5,4)) {
1164          case 0:
1165            ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1166            break;
1167          case 1:
1168            ignore = true;
1169            break;
1170          case 3:
1171            ctx_id = 0;
1172            break;
1173          default:
1174            ignore = true;
1175        }
1176
1177        switch(bits(va,7,6)) {
1178          case 0: // demap page
1179            if (!ignore)
1180                tc->getITBPtr()->demapPage(mbits(va,63,13), part_id,
1181                        bits(va,9,9), ctx_id);
1182            break;
1183          case 1: //demap context
1184            if (!ignore)
1185                tc->getITBPtr()->demapContext(part_id, ctx_id);
1186            break;
1187          case 2:
1188            tc->getITBPtr()->demapAll(part_id);
1189            break;
1190          default:
1191            panic("Invalid type for IMMU demap\n");
1192        }
1193        break;
1194      case ASI_DMMU:
1195        switch (va) {
1196          case 0x18:
1197            tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data);
1198            break;
1199          case 0x30:
1200            sext<59>(bits(data, 59,0));
1201            tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data);
1202            break;
1203          case 0x80:
1204            tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data);
1205            break;
1206          default:
1207            goto doMmuWriteError;
1208        }
1209        break;
1210      case ASI_DMMU_DEMAP:
1211        ignore = false;
1212        ctx_id = -1;
1213        part_id =  tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID);
1214        switch (bits(va,5,4)) {
1215          case 0:
1216            ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT);
1217            break;
1218          case 1:
1219            ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT);
1220            break;
1221          case 3:
1222            ctx_id = 0;
1223            break;
1224          default:
1225            ignore = true;
1226        }
1227
1228        switch(bits(va,7,6)) {
1229          case 0: // demap page
1230            if (!ignore)
1231                demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id);
1232            break;
1233          case 1: //demap context
1234            if (!ignore)
1235                demapContext(part_id, ctx_id);
1236            break;
1237          case 2:
1238            demapAll(part_id);
1239            break;
1240          default:
1241            panic("Invalid type for IMMU demap\n");
1242        }
1243        break;
1244      default:
1245doMmuWriteError:
1246        panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n",
1247            (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data);
1248    }
1249    pkt->result = Packet::Success;
1250    return tc->getCpuPtr()->cycles(1);
1251}
1252
1253void
1254TLB::serialize(std::ostream &os)
1255{
1256    panic("Need to implement serialize tlb for SPARC\n");
1257}
1258
1259void
1260TLB::unserialize(Checkpoint *cp, const std::string &section)
1261{
1262    panic("Need to implement unserialize tlb for SPARC\n");
1263}
1264
1265
1266DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB)
1267
1268BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB)
1269
1270    Param<int> size;
1271
1272END_DECLARE_SIM_OBJECT_PARAMS(ITB)
1273
1274BEGIN_INIT_SIM_OBJECT_PARAMS(ITB)
1275
1276    INIT_PARAM_DFLT(size, "TLB size", 48)
1277
1278END_INIT_SIM_OBJECT_PARAMS(ITB)
1279
1280
1281CREATE_SIM_OBJECT(ITB)
1282{
1283    return new ITB(getInstanceName(), size);
1284}
1285
1286REGISTER_SIM_OBJECT("SparcITB", ITB)
1287
1288BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB)
1289
1290    Param<int> size;
1291
1292END_DECLARE_SIM_OBJECT_PARAMS(DTB)
1293
1294BEGIN_INIT_SIM_OBJECT_PARAMS(DTB)
1295
1296    INIT_PARAM_DFLT(size, "TLB size", 64)
1297
1298END_INIT_SIM_OBJECT_PARAMS(DTB)
1299
1300
1301CREATE_SIM_OBJECT(DTB)
1302{
1303    return new DTB(getInstanceName(), size);
1304}
1305
1306REGISTER_SIM_OBJECT("SparcDTB", DTB)
1307}
1308