tlb.cc revision 4010:52c2b6941c02
1/* 2 * Copyright (c) 2001-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Ali Saidi 29 */ 30 31#include <cstring> 32 33#include "arch/sparc/asi.hh" 34#include "arch/sparc/miscregfile.hh" 35#include "arch/sparc/tlb.hh" 36#include "base/bitfield.hh" 37#include "base/trace.hh" 38#include "cpu/thread_context.hh" 39#include "cpu/base.hh" 40#include "mem/packet_access.hh" 41#include "mem/request.hh" 42#include "sim/builder.hh" 43 44/* @todo remove some of the magic constants. -- ali 45 * */ 46namespace SparcISA 47{ 48 49TLB::TLB(const std::string &name, int s) 50 : SimObject(name), size(s), usedEntries(0), lastReplaced(0), 51 cacheValid(false) 52{ 53 // To make this work you'll have to change the hypervisor and OS 54 if (size > 64) 55 fatal("SPARC T1 TLB registers don't support more than 64 TLB entries."); 56 57 tlb = new TlbEntry[size]; 58 std::memset(tlb, 0, sizeof(TlbEntry) * size); 59 60 for (int x = 0; x < size; x++) 61 freeList.push_back(&tlb[x]); 62} 63 64void 65TLB::clearUsedBits() 66{ 67 MapIter i; 68 for (i = lookupTable.begin(); i != lookupTable.end(); i++) { 69 TlbEntry *t = i->second; 70 if (!t->pte.locked()) { 71 t->used = false; 72 usedEntries--; 73 } 74 } 75} 76 77 78void 79TLB::insert(Addr va, int partition_id, int context_id, bool real, 80 const PageTableEntry& PTE, int entry) 81{ 82 83 84 MapIter i; 85 TlbEntry *new_entry = NULL; 86// TlbRange tr; 87 int x; 88 89 cacheValid = false; 90 va &= ~(PTE.size()-1); 91 /* tr.va = va; 92 tr.size = PTE.size() - 1; 93 tr.contextId = context_id; 94 tr.partitionId = partition_id; 95 tr.real = real; 96*/ 97 98 DPRINTF(TLB, "TLB: Inserting TLB Entry; va=%#x pa=%#x pid=%d cid=%d r=%d entryid=%d\n", 99 va, PTE.paddr(), partition_id, context_id, (int)real, entry); 100 101 // Demap any entry that conflicts 102 for (x = 0; x < size; x++) { 103 if (tlb[x].range.real == real && 104 tlb[x].range.partitionId == partition_id && 105 tlb[x].range.va < va + PTE.size() - 1 && 106 tlb[x].range.va + tlb[x].range.size >= va && 107 (real || tlb[x].range.contextId == context_id )) 108 { 109 if (tlb[x].valid) { 110 freeList.push_front(&tlb[x]); 111 DPRINTF(TLB, "TLB: Conflicting entry %#X , deleting it\n", x); 112 113 tlb[x].valid = false; 114 if (tlb[x].used) { 115 tlb[x].used = false; 116 usedEntries--; 117 } 118 lookupTable.erase(tlb[x].range); 119 } 120 } 121 } 122 123 124/* 125 i = lookupTable.find(tr); 126 if (i != lookupTable.end()) { 127 i->second->valid = false; 128 if (i->second->used) { 129 i->second->used = false; 130 usedEntries--; 131 } 132 freeList.push_front(i->second); 133 DPRINTF(TLB, "TLB: Found conflicting entry %#X , deleting it\n", 134 i->second); 135 lookupTable.erase(i); 136 } 137*/ 138 139 if (entry != -1) { 140 assert(entry < size && entry >= 0); 141 new_entry = &tlb[entry]; 142 } else { 143 if (!freeList.empty()) { 144 new_entry = freeList.front(); 145 } else { 146 x = lastReplaced; 147 do { 148 ++x; 149 if (x == size) 150 x = 0; 151 if (x == lastReplaced) 152 goto insertAllLocked; 153 } while (tlb[x].pte.locked()); 154 lastReplaced = x; 155 new_entry = &tlb[x]; 156 } 157 /* 158 for (x = 0; x < size; x++) { 159 if (!tlb[x].valid || !tlb[x].used) { 160 new_entry = &tlb[x]; 161 break; 162 } 163 }*/ 164 } 165 166insertAllLocked: 167 // Update the last ently if their all locked 168 if (!new_entry) { 169 new_entry = &tlb[size-1]; 170 } 171 172 freeList.remove(new_entry); 173 if (new_entry->valid && new_entry->used) 174 usedEntries--; 175 if (new_entry->valid) 176 lookupTable.erase(new_entry->range); 177 178 179 assert(PTE.valid()); 180 new_entry->range.va = va; 181 new_entry->range.size = PTE.size() - 1; 182 new_entry->range.partitionId = partition_id; 183 new_entry->range.contextId = context_id; 184 new_entry->range.real = real; 185 new_entry->pte = PTE; 186 new_entry->used = true;; 187 new_entry->valid = true; 188 usedEntries++; 189 190 191 192 i = lookupTable.insert(new_entry->range, new_entry); 193 assert(i != lookupTable.end()); 194 195 // If all entries have there used bit set, clear it on them all, but the 196 // one we just inserted 197 if (usedEntries == size) { 198 clearUsedBits(); 199 new_entry->used = true; 200 usedEntries++; 201 } 202 203} 204 205 206TlbEntry* 207TLB::lookup(Addr va, int partition_id, bool real, int context_id) 208{ 209 MapIter i; 210 TlbRange tr; 211 TlbEntry *t; 212 213 DPRINTF(TLB, "TLB: Looking up entry va=%#x pid=%d cid=%d r=%d\n", 214 va, partition_id, context_id, real); 215 // Assemble full address structure 216 tr.va = va; 217 tr.size = MachineBytes; 218 tr.contextId = context_id; 219 tr.partitionId = partition_id; 220 tr.real = real; 221 222 // Try to find the entry 223 i = lookupTable.find(tr); 224 if (i == lookupTable.end()) { 225 DPRINTF(TLB, "TLB: No valid entry found\n"); 226 return NULL; 227 } 228 229 // Mark the entries used bit and clear other used bits in needed 230 t = i->second; 231 DPRINTF(TLB, "TLB: Valid entry found pa: %#x size: %#x\n", t->pte.paddr(), 232 t->pte.size()); 233 if (!t->used) { 234 t->used = true; 235 usedEntries++; 236 if (usedEntries == size) { 237 clearUsedBits(); 238 t->used = true; 239 usedEntries++; 240 } 241 } 242 243 return t; 244} 245 246void 247TLB::dumpAll() 248{ 249 MapIter i; 250 for (int x = 0; x < size; x++) { 251 if (tlb[x].valid) { 252 DPRINTFN("%4d: %#2x:%#2x %c %#4x %#8x %#8x %#16x\n", 253 x, tlb[x].range.partitionId, tlb[x].range.contextId, 254 tlb[x].range.real ? 'R' : ' ', tlb[x].range.size, 255 tlb[x].range.va, tlb[x].pte.paddr(), tlb[x].pte()); 256 } 257 } 258} 259 260void 261TLB::demapPage(Addr va, int partition_id, bool real, int context_id) 262{ 263 TlbRange tr; 264 MapIter i; 265 266 DPRINTF(IPR, "TLB: Demapping Page va=%#x pid=%#d cid=%d r=%d\n", 267 va, partition_id, context_id, real); 268 269 cacheValid = false; 270 271 // Assemble full address structure 272 tr.va = va; 273 tr.size = MachineBytes; 274 tr.contextId = context_id; 275 tr.partitionId = partition_id; 276 tr.real = real; 277 278 // Demap any entry that conflicts 279 i = lookupTable.find(tr); 280 if (i != lookupTable.end()) { 281 DPRINTF(IPR, "TLB: Demapped page\n"); 282 i->second->valid = false; 283 if (i->second->used) { 284 i->second->used = false; 285 usedEntries--; 286 } 287 freeList.push_front(i->second); 288 lookupTable.erase(i); 289 } 290} 291 292void 293TLB::demapContext(int partition_id, int context_id) 294{ 295 int x; 296 DPRINTF(IPR, "TLB: Demapping Context pid=%#d cid=%d\n", 297 partition_id, context_id); 298 cacheValid = false; 299 for (x = 0; x < size; x++) { 300 if (tlb[x].range.contextId == context_id && 301 tlb[x].range.partitionId == partition_id) { 302 if (tlb[x].valid == true) { 303 freeList.push_front(&tlb[x]); 304 } 305 tlb[x].valid = false; 306 if (tlb[x].used) { 307 tlb[x].used = false; 308 usedEntries--; 309 } 310 lookupTable.erase(tlb[x].range); 311 } 312 } 313} 314 315void 316TLB::demapAll(int partition_id) 317{ 318 int x; 319 DPRINTF(TLB, "TLB: Demapping All pid=%#d\n", partition_id); 320 cacheValid = false; 321 for (x = 0; x < size; x++) { 322 if (!tlb[x].pte.locked() && tlb[x].range.partitionId == partition_id) { 323 if (tlb[x].valid == true){ 324 freeList.push_front(&tlb[x]); 325 } 326 tlb[x].valid = false; 327 if (tlb[x].used) { 328 tlb[x].used = false; 329 usedEntries--; 330 } 331 lookupTable.erase(tlb[x].range); 332 } 333 } 334} 335 336void 337TLB::invalidateAll() 338{ 339 int x; 340 cacheValid = false; 341 342 freeList.clear(); 343 lookupTable.clear(); 344 for (x = 0; x < size; x++) { 345 if (tlb[x].valid == true) 346 freeList.push_back(&tlb[x]); 347 tlb[x].valid = false; 348 tlb[x].used = false; 349 } 350 usedEntries = 0; 351} 352 353uint64_t 354TLB::TteRead(int entry) { 355 if (entry >= size) 356 panic("entry: %d\n", entry); 357 358 assert(entry < size); 359 if (tlb[entry].valid) 360 return tlb[entry].pte(); 361 else 362 return (uint64_t)-1ll; 363} 364 365uint64_t 366TLB::TagRead(int entry) { 367 assert(entry < size); 368 uint64_t tag; 369 if (!tlb[entry].valid) 370 return (uint64_t)-1ll; 371 372 tag = tlb[entry].range.contextId; 373 tag |= tlb[entry].range.va; 374 tag |= (uint64_t)tlb[entry].range.partitionId << 61; 375 tag |= tlb[entry].range.real ? ULL(1) << 60 : 0; 376 tag |= (uint64_t)~tlb[entry].pte._size() << 56; 377 return tag; 378} 379 380bool 381TLB::validVirtualAddress(Addr va, bool am) 382{ 383 if (am) 384 return true; 385 if (va >= StartVAddrHole && va <= EndVAddrHole) 386 return false; 387 return true; 388} 389 390void 391TLB::writeSfsr(ThreadContext *tc, int reg, bool write, ContextType ct, 392 bool se, FaultTypes ft, int asi) 393{ 394 uint64_t sfsr; 395 sfsr = tc->readMiscReg(reg); 396 397 if (sfsr & 0x1) 398 sfsr = 0x3; 399 else 400 sfsr = 1; 401 402 if (write) 403 sfsr |= 1 << 2; 404 sfsr |= ct << 4; 405 if (se) 406 sfsr |= 1 << 6; 407 sfsr |= ft << 7; 408 sfsr |= asi << 16; 409 tc->setMiscRegWithEffect(reg, sfsr); 410} 411 412void 413TLB::writeTagAccess(ThreadContext *tc, int reg, Addr va, int context) 414{ 415 DPRINTF(TLB, "TLB: Writing Tag Access: va: %#X ctx: %#X value: %#X\n", 416 va, context, mbits(va, 63,13) | mbits(context,12,0)); 417 418 tc->setMiscRegWithEffect(reg, mbits(va, 63,13) | mbits(context,12,0)); 419} 420 421void 422ITB::writeSfsr(ThreadContext *tc, bool write, ContextType ct, 423 bool se, FaultTypes ft, int asi) 424{ 425 DPRINTF(TLB, "TLB: ITB Fault: w=%d ct=%d ft=%d asi=%d\n", 426 (int)write, ct, ft, asi); 427 TLB::writeSfsr(tc, MISCREG_MMU_ITLB_SFSR, write, ct, se, ft, asi); 428} 429 430void 431ITB::writeTagAccess(ThreadContext *tc, Addr va, int context) 432{ 433 TLB::writeTagAccess(tc, MISCREG_MMU_ITLB_TAG_ACCESS, va, context); 434} 435 436void 437DTB::writeSfr(ThreadContext *tc, Addr a, bool write, ContextType ct, 438 bool se, FaultTypes ft, int asi) 439{ 440 DPRINTF(TLB, "TLB: DTB Fault: A=%#x w=%d ct=%d ft=%d asi=%d\n", 441 a, (int)write, ct, ft, asi); 442 TLB::writeSfsr(tc, MISCREG_MMU_DTLB_SFSR, write, ct, se, ft, asi); 443 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR, a); 444} 445 446void 447DTB::writeTagAccess(ThreadContext *tc, Addr va, int context) 448{ 449 TLB::writeTagAccess(tc, MISCREG_MMU_DTLB_TAG_ACCESS, va, context); 450} 451 452 453 454Fault 455ITB::translate(RequestPtr &req, ThreadContext *tc) 456{ 457 uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 458 459 Addr vaddr = req->getVaddr(); 460 TlbEntry *e; 461 462 assert(req->getAsi() == ASI_IMPLICIT); 463 464 DPRINTF(TLB, "TLB: ITB Request to translate va=%#x size=%d\n", 465 vaddr, req->getSize()); 466 467 // Be fast if we can! 468 if (cacheValid && cacheState == tlbdata) { 469 if (cacheEntry) { 470 if (cacheEntry->range.va < vaddr + sizeof(MachInst) && 471 cacheEntry->range.va + cacheEntry->range.size >= vaddr) { 472 req->setPaddr(cacheEntry->pte.paddr() & ~(cacheEntry->pte.size()-1) | 473 vaddr & cacheEntry->pte.size()-1 ); 474 return NoFault; 475 } 476 } else { 477 req->setPaddr(vaddr & PAddrImplMask); 478 return NoFault; 479 } 480 } 481 482 bool hpriv = bits(tlbdata,0,0); 483 bool red = bits(tlbdata,1,1); 484 bool priv = bits(tlbdata,2,2); 485 bool addr_mask = bits(tlbdata,3,3); 486 bool lsu_im = bits(tlbdata,4,4); 487 488 int part_id = bits(tlbdata,15,8); 489 int tl = bits(tlbdata,18,16); 490 int pri_context = bits(tlbdata,47,32); 491 int context; 492 ContextType ct; 493 int asi; 494 bool real = false; 495 496 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsuim:%d part_id: %#X\n", 497 priv, hpriv, red, lsu_im, part_id); 498 499 if (tl > 0) { 500 asi = ASI_N; 501 ct = Nucleus; 502 context = 0; 503 } else { 504 asi = ASI_P; 505 ct = Primary; 506 context = pri_context; 507 } 508 509 if ( hpriv || red ) { 510 cacheValid = true; 511 cacheState = tlbdata; 512 cacheEntry = NULL; 513 req->setPaddr(vaddr & PAddrImplMask); 514 return NoFault; 515 } 516 517 // If the access is unaligned trap 518 if (vaddr & 0x3) { 519 writeSfsr(tc, false, ct, false, OtherFault, asi); 520 return new MemAddressNotAligned; 521 } 522 523 if (addr_mask) 524 vaddr = vaddr & VAddrAMask; 525 526 if (!validVirtualAddress(vaddr, addr_mask)) { 527 writeSfsr(tc, false, ct, false, VaOutOfRange, asi); 528 return new InstructionAccessException; 529 } 530 531 if (!lsu_im) { 532 e = lookup(vaddr, part_id, true); 533 real = true; 534 context = 0; 535 } else { 536 e = lookup(vaddr, part_id, false, context); 537 } 538 539 if (e == NULL || !e->valid) { 540 writeTagAccess(tc, vaddr, context); 541 if (real) 542 return new InstructionRealTranslationMiss; 543 else 544 return new FastInstructionAccessMMUMiss; 545 } 546 547 // were not priviledged accesing priv page 548 if (!priv && e->pte.priv()) { 549 writeTagAccess(tc, vaddr, context); 550 writeSfsr(tc, false, ct, false, PrivViolation, asi); 551 return new InstructionAccessException; 552 } 553 554 // cache translation date for next translation 555 cacheValid = true; 556 cacheState = tlbdata; 557 cacheEntry = e; 558 559 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 560 vaddr & e->pte.size()-1 ); 561 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 562 return NoFault; 563} 564 565 566 567Fault 568DTB::translate(RequestPtr &req, ThreadContext *tc, bool write) 569{ 570 /* @todo this could really use some profiling and fixing to make it faster! */ 571 uint64_t tlbdata = tc->readMiscReg(MISCREG_TLB_DATA); 572 Addr vaddr = req->getVaddr(); 573 Addr size = req->getSize(); 574 ASI asi; 575 asi = (ASI)req->getAsi(); 576 bool implicit = false; 577 bool hpriv = bits(tlbdata,0,0); 578 579 DPRINTF(TLB, "TLB: DTB Request to translate va=%#x size=%d asi=%#x\n", 580 vaddr, size, asi); 581 582 if (lookupTable.size() != 64 - freeList.size()) 583 panic("Lookup table size: %d tlb size: %d\n", lookupTable.size(), 584 freeList.size()); 585 if (asi == ASI_IMPLICIT) 586 implicit = true; 587 588 if (hpriv && implicit) { 589 req->setPaddr(vaddr & PAddrImplMask); 590 return NoFault; 591 } 592 593 // Be fast if we can! 594 if (cacheValid && cacheState == tlbdata) { 595 if (cacheEntry[0] && cacheAsi[0] == asi && cacheEntry[0]->range.va < vaddr + size && 596 cacheEntry[0]->range.va + cacheEntry[0]->range.size > vaddr && 597 (!write || cacheEntry[0]->pte.writable())) { 598 req->setPaddr(cacheEntry[0]->pte.paddr() & ~(cacheEntry[0]->pte.size()-1) | 599 vaddr & cacheEntry[0]->pte.size()-1 ); 600 return NoFault; 601 } 602 if (cacheEntry[1] && cacheAsi[1] == asi && cacheEntry[1]->range.va < vaddr + size && 603 cacheEntry[1]->range.va + cacheEntry[1]->range.size > vaddr && 604 (!write || cacheEntry[1]->pte.writable())) { 605 req->setPaddr(cacheEntry[1]->pte.paddr() & ~(cacheEntry[1]->pte.size()-1) | 606 vaddr & cacheEntry[1]->pte.size()-1 ); 607 return NoFault; 608 } 609 } 610 611 bool red = bits(tlbdata,1,1); 612 bool priv = bits(tlbdata,2,2); 613 bool addr_mask = bits(tlbdata,3,3); 614 bool lsu_dm = bits(tlbdata,5,5); 615 616 int part_id = bits(tlbdata,15,8); 617 int tl = bits(tlbdata,18,16); 618 int pri_context = bits(tlbdata,47,32); 619 int sec_context = bits(tlbdata,63,48); 620 621 bool real = false; 622 ContextType ct = Primary; 623 int context = 0; 624 625 TlbEntry *e; 626 627 DPRINTF(TLB, "TLB: priv:%d hpriv:%d red:%d lsudm:%d part_id: %#X\n", 628 priv, hpriv, red, lsu_dm, part_id); 629 630 if (implicit) { 631 if (tl > 0) { 632 asi = ASI_N; 633 ct = Nucleus; 634 context = 0; 635 } else { 636 asi = ASI_P; 637 ct = Primary; 638 context = pri_context; 639 } 640 } else { 641 // We need to check for priv level/asi priv 642 if (!priv && !hpriv && !AsiIsUnPriv(asi)) { 643 // It appears that context should be Nucleus in these cases? 644 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 645 return new PrivilegedAction; 646 } 647 648 if (!hpriv && AsiIsHPriv(asi)) { 649 writeSfr(tc, vaddr, write, Nucleus, false, IllegalAsi, asi); 650 return new DataAccessException; 651 } 652 653 if (AsiIsPrimary(asi)) { 654 context = pri_context; 655 ct = Primary; 656 } else if (AsiIsSecondary(asi)) { 657 context = sec_context; 658 ct = Secondary; 659 } else if (AsiIsNucleus(asi)) { 660 ct = Nucleus; 661 context = 0; 662 } else { // ???? 663 ct = Primary; 664 context = pri_context; 665 } 666 } 667 668 if (!implicit && asi != ASI_P && asi != ASI_S) { 669 if (AsiIsLittle(asi)) 670 panic("Little Endian ASIs not supported\n"); 671 if (AsiIsNoFault(asi)) 672 panic("No Fault ASIs not supported\n"); 673 674 if (AsiIsPartialStore(asi)) 675 panic("Partial Store ASIs not supported\n"); 676 if (AsiIsInterrupt(asi)) 677 panic("Interrupt ASIs not supported\n"); 678 679 if (AsiIsMmu(asi)) 680 goto handleMmuRegAccess; 681 if (AsiIsScratchPad(asi)) 682 goto handleScratchRegAccess; 683 if (AsiIsQueue(asi)) 684 goto handleQueueRegAccess; 685 if (AsiIsSparcError(asi)) 686 goto handleSparcErrorRegAccess; 687 688 if (!AsiIsReal(asi) && !AsiIsNucleus(asi) && !AsiIsAsIfUser(asi) && 689 !AsiIsTwin(asi) && !AsiIsBlock(asi)) 690 panic("Accessing ASI %#X. Should we?\n", asi); 691 } 692 693 // If the asi is unaligned trap 694 if (vaddr & size-1) { 695 writeSfr(tc, vaddr, false, ct, false, OtherFault, asi); 696 return new MemAddressNotAligned; 697 } 698 699 if (addr_mask) 700 vaddr = vaddr & VAddrAMask; 701 702 if (!validVirtualAddress(vaddr, addr_mask)) { 703 writeSfr(tc, vaddr, false, ct, true, VaOutOfRange, asi); 704 return new DataAccessException; 705 } 706 707 708 if ((!lsu_dm && !hpriv && !red) || AsiIsReal(asi)) { 709 real = true; 710 context = 0; 711 }; 712 713 if (hpriv && (implicit || (!AsiIsAsIfUser(asi) && !AsiIsReal(asi)))) { 714 req->setPaddr(vaddr & PAddrImplMask); 715 return NoFault; 716 } 717 718 e = lookup(vaddr, part_id, real, context); 719 720 if (e == NULL || !e->valid) { 721 writeTagAccess(tc, vaddr, context); 722 DPRINTF(TLB, "TLB: DTB Failed to find matching TLB entry\n"); 723 if (real) 724 return new DataRealTranslationMiss; 725 else 726 return new FastDataAccessMMUMiss; 727 728 } 729 730 if (!priv && e->pte.priv()) { 731 writeTagAccess(tc, vaddr, context); 732 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), PrivViolation, asi); 733 return new DataAccessException; 734 } 735 736 if (write && !e->pte.writable()) { 737 writeTagAccess(tc, vaddr, context); 738 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), OtherFault, asi); 739 return new FastDataAccessProtection; 740 } 741 742 if (e->pte.nofault() && !AsiIsNoFault(asi)) { 743 writeTagAccess(tc, vaddr, context); 744 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), LoadFromNfo, asi); 745 return new DataAccessException; 746 } 747 748 if (e->pte.sideffect() && AsiIsNoFault(asi)) { 749 writeTagAccess(tc, vaddr, context); 750 writeSfr(tc, vaddr, write, ct, e->pte.sideffect(), SideEffect, asi); 751 return new DataAccessException; 752 } 753 754 755 if (e->pte.sideffect()) 756 req->setFlags(req->getFlags() | UNCACHEABLE); 757 758 // cache translation date for next translation 759 cacheState = tlbdata; 760 if (!cacheValid) { 761 cacheEntry[1] = NULL; 762 cacheEntry[0] = NULL; 763 } 764 765 if (cacheEntry[0] != e && cacheEntry[1] != e) { 766 cacheEntry[1] = cacheEntry[0]; 767 cacheEntry[0] = e; 768 cacheAsi[1] = cacheAsi[0]; 769 cacheAsi[0] = asi; 770 if (implicit) 771 cacheAsi[0] = (ASI)0; 772 } 773 cacheValid = true; 774 req->setPaddr(e->pte.paddr() & ~(e->pte.size()-1) | 775 vaddr & e->pte.size()-1); 776 DPRINTF(TLB, "TLB: %#X -> %#X\n", vaddr, req->getPaddr()); 777 return NoFault; 778 /** Normal flow ends here. */ 779 780handleScratchRegAccess: 781 if (vaddr > 0x38 || (vaddr >= 0x20 && vaddr < 0x30 && !hpriv)) { 782 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 783 return new DataAccessException; 784 } 785 goto regAccessOk; 786 787handleQueueRegAccess: 788 if (!priv && !hpriv) { 789 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 790 return new PrivilegedAction; 791 } 792 if (!hpriv && vaddr & 0xF || vaddr > 0x3f8 || vaddr < 0x3c0) { 793 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 794 return new DataAccessException; 795 } 796 goto regAccessOk; 797 798handleSparcErrorRegAccess: 799 if (!hpriv) { 800 if (priv) { 801 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 802 return new DataAccessException; 803 } else { 804 writeSfr(tc, vaddr, write, Primary, true, IllegalAsi, asi); 805 return new PrivilegedAction; 806 } 807 } 808 goto regAccessOk; 809 810 811regAccessOk: 812handleMmuRegAccess: 813 DPRINTF(TLB, "TLB: DTB Translating MM IPR access\n"); 814 req->setMmapedIpr(true); 815 req->setPaddr(req->getVaddr()); 816 return NoFault; 817}; 818 819Tick 820DTB::doMmuRegRead(ThreadContext *tc, Packet *pkt) 821{ 822 Addr va = pkt->getAddr(); 823 ASI asi = (ASI)pkt->req->getAsi(); 824 uint64_t temp, data; 825 uint64_t tsbtemp, cnftemp; 826 827 DPRINTF(IPR, "Memory Mapped IPR Read: asi=%#X a=%#x\n", 828 (uint32_t)pkt->req->getAsi(), pkt->getAddr()); 829 830 switch (asi) { 831 case ASI_LSU_CONTROL_REG: 832 assert(va == 0); 833 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_LSU_CTRL)); 834 break; 835 case ASI_MMU: 836 switch (va) { 837 case 0x8: 838 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT)); 839 break; 840 case 0x10: 841 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT)); 842 break; 843 default: 844 goto doMmuReadError; 845 } 846 break; 847 case ASI_QUEUE: 848 pkt->set(tc->readMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 849 (va >> 4) - 0x3c)); 850 break; 851 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 852 assert(va == 0); 853 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0)); 854 break; 855 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 856 assert(va == 0); 857 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1)); 858 break; 859 case ASI_DMMU_CTXT_ZERO_CONFIG: 860 assert(va == 0); 861 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG)); 862 break; 863 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 864 assert(va == 0); 865 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0)); 866 break; 867 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 868 assert(va == 0); 869 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1)); 870 break; 871 case ASI_IMMU_CTXT_ZERO_CONFIG: 872 assert(va == 0); 873 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG)); 874 break; 875 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 876 assert(va == 0); 877 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0)); 878 break; 879 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 880 assert(va == 0); 881 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1)); 882 break; 883 case ASI_DMMU_CTXT_NONZERO_CONFIG: 884 assert(va == 0); 885 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG)); 886 break; 887 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 888 assert(va == 0); 889 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0)); 890 break; 891 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 892 assert(va == 0); 893 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1)); 894 break; 895 case ASI_IMMU_CTXT_NONZERO_CONFIG: 896 assert(va == 0); 897 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG)); 898 break; 899 case ASI_SPARC_ERROR_STATUS_REG: 900 pkt->set((uint64_t)0); 901 break; 902 case ASI_HYP_SCRATCHPAD: 903 case ASI_SCRATCHPAD: 904 pkt->set(tc->readMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3))); 905 break; 906 case ASI_IMMU: 907 switch (va) { 908 case 0x0: 909 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 910 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 911 break; 912 case 0x18: 913 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR)); 914 break; 915 case 0x30: 916 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS)); 917 break; 918 default: 919 goto doMmuReadError; 920 } 921 break; 922 case ASI_DMMU: 923 switch (va) { 924 case 0x0: 925 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 926 pkt->set(bits(temp,63,22) | bits(temp,12,0) << 48); 927 break; 928 case 0x18: 929 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR)); 930 break; 931 case 0x20: 932 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_SFAR)); 933 break; 934 case 0x30: 935 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS)); 936 break; 937 case 0x80: 938 pkt->set(tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID)); 939 break; 940 default: 941 goto doMmuReadError; 942 } 943 break; 944 case ASI_DMMU_TSB_PS0_PTR_REG: 945 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 946 if (bits(temp,12,0) == 0) { 947 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0); 948 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG); 949 } else { 950 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0); 951 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG); 952 } 953 data = mbits(tsbtemp,63,13); 954 data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 955 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 956 pkt->set(data); 957 break; 958 case ASI_DMMU_TSB_PS1_PTR_REG: 959 temp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 960 if (bits(temp,12,0) == 0) { 961 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1); 962 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG); 963 } else { 964 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1); 965 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG); 966 } 967 data = mbits(tsbtemp,63,13); 968 if (bits(tsbtemp,12,12)) 969 data |= ULL(1) << (13+bits(tsbtemp,3,0)); 970 data |= temp >> (9 + bits(cnftemp,10,8) * 3) & 971 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 972 pkt->set(data); 973 break; 974 case ASI_IMMU_TSB_PS0_PTR_REG: 975 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 976 if (bits(temp,12,0) == 0) { 977 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0); 978 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG); 979 } else { 980 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0); 981 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG); 982 } 983 data = mbits(tsbtemp,63,13); 984 data |= temp >> (9 + bits(cnftemp,2,0) * 3) & 985 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 986 pkt->set(data); 987 break; 988 case ASI_IMMU_TSB_PS1_PTR_REG: 989 temp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 990 if (bits(temp,12,0) == 0) { 991 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1); 992 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG); 993 } else { 994 tsbtemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1); 995 cnftemp = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG); 996 } 997 data = mbits(tsbtemp,63,13); 998 if (bits(tsbtemp,12,12)) 999 data |= ULL(1) << (13+bits(tsbtemp,3,0)); 1000 data |= temp >> (9 + bits(cnftemp,10,8) * 3) & 1001 mbits((uint64_t)-1ll,12+bits(tsbtemp,3,0), 4); 1002 pkt->set(data); 1003 break; 1004 1005 default: 1006doMmuReadError: 1007 panic("need to impl DTB::doMmuRegRead() got asi=%#x, va=%#x\n", 1008 (uint32_t)asi, va); 1009 } 1010 pkt->result = Packet::Success; 1011 return tc->getCpuPtr()->cycles(1); 1012} 1013 1014Tick 1015DTB::doMmuRegWrite(ThreadContext *tc, Packet *pkt) 1016{ 1017 uint64_t data = gtoh(pkt->get<uint64_t>()); 1018 Addr va = pkt->getAddr(); 1019 ASI asi = (ASI)pkt->req->getAsi(); 1020 1021 Addr ta_insert; 1022 Addr va_insert; 1023 Addr ct_insert; 1024 int part_insert; 1025 int entry_insert = -1; 1026 bool real_insert; 1027 bool ignore; 1028 int part_id; 1029 int ctx_id; 1030 PageTableEntry pte; 1031 1032 DPRINTF(IPR, "Memory Mapped IPR Write: asi=%#X a=%#x d=%#X\n", 1033 (uint32_t)asi, va, data); 1034 1035 switch (asi) { 1036 case ASI_LSU_CONTROL_REG: 1037 assert(va == 0); 1038 tc->setMiscRegWithEffect(MISCREG_MMU_LSU_CTRL, data); 1039 break; 1040 case ASI_MMU: 1041 switch (va) { 1042 case 0x8: 1043 tc->setMiscRegWithEffect(MISCREG_MMU_P_CONTEXT, data); 1044 break; 1045 case 0x10: 1046 tc->setMiscRegWithEffect(MISCREG_MMU_S_CONTEXT, data); 1047 break; 1048 default: 1049 goto doMmuWriteError; 1050 } 1051 break; 1052 case ASI_QUEUE: 1053 assert(mbits(data,13,6) == data); 1054 tc->setMiscRegWithEffect(MISCREG_QUEUE_CPU_MONDO_HEAD + 1055 (va >> 4) - 0x3c, data); 1056 break; 1057 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS0: 1058 assert(va == 0); 1059 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS0, data); 1060 break; 1061 case ASI_DMMU_CTXT_ZERO_TSB_BASE_PS1: 1062 assert(va == 0); 1063 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_TSB_PS1, data); 1064 break; 1065 case ASI_DMMU_CTXT_ZERO_CONFIG: 1066 assert(va == 0); 1067 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_C0_CONFIG, data); 1068 break; 1069 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS0: 1070 assert(va == 0); 1071 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS0, data); 1072 break; 1073 case ASI_IMMU_CTXT_ZERO_TSB_BASE_PS1: 1074 assert(va == 0); 1075 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_TSB_PS1, data); 1076 break; 1077 case ASI_IMMU_CTXT_ZERO_CONFIG: 1078 assert(va == 0); 1079 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_C0_CONFIG, data); 1080 break; 1081 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS0: 1082 assert(va == 0); 1083 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS0, data); 1084 break; 1085 case ASI_DMMU_CTXT_NONZERO_TSB_BASE_PS1: 1086 assert(va == 0); 1087 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_TSB_PS1, data); 1088 break; 1089 case ASI_DMMU_CTXT_NONZERO_CONFIG: 1090 assert(va == 0); 1091 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_CX_CONFIG, data); 1092 break; 1093 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS0: 1094 assert(va == 0); 1095 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS0, data); 1096 break; 1097 case ASI_IMMU_CTXT_NONZERO_TSB_BASE_PS1: 1098 assert(va == 0); 1099 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_TSB_PS1, data); 1100 break; 1101 case ASI_IMMU_CTXT_NONZERO_CONFIG: 1102 assert(va == 0); 1103 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_CX_CONFIG, data); 1104 break; 1105 case ASI_SPARC_ERROR_EN_REG: 1106 case ASI_SPARC_ERROR_STATUS_REG: 1107 warn("Ignoring write to SPARC ERROR regsiter\n"); 1108 break; 1109 case ASI_HYP_SCRATCHPAD: 1110 case ASI_SCRATCHPAD: 1111 tc->setMiscRegWithEffect(MISCREG_SCRATCHPAD_R0 + (va >> 3), data); 1112 break; 1113 case ASI_IMMU: 1114 switch (va) { 1115 case 0x18: 1116 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_SFSR, data); 1117 break; 1118 case 0x30: 1119 sext<59>(bits(data, 59,0)); 1120 tc->setMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS, data); 1121 break; 1122 default: 1123 goto doMmuWriteError; 1124 } 1125 break; 1126 case ASI_ITLB_DATA_ACCESS_REG: 1127 entry_insert = bits(va, 8,3); 1128 case ASI_ITLB_DATA_IN_REG: 1129 assert(entry_insert != -1 || mbits(va,10,9) == va); 1130 ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_ITLB_TAG_ACCESS); 1131 va_insert = mbits(ta_insert, 63,13); 1132 ct_insert = mbits(ta_insert, 12,0); 1133 part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 1134 real_insert = bits(va, 9,9); 1135 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 1136 PageTableEntry::sun4u); 1137 tc->getITBPtr()->insert(va_insert, part_insert, ct_insert, real_insert, 1138 pte, entry_insert); 1139 break; 1140 case ASI_DTLB_DATA_ACCESS_REG: 1141 entry_insert = bits(va, 8,3); 1142 case ASI_DTLB_DATA_IN_REG: 1143 assert(entry_insert != -1 || mbits(va,10,9) == va); 1144 ta_insert = tc->readMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS); 1145 va_insert = mbits(ta_insert, 63,13); 1146 ct_insert = mbits(ta_insert, 12,0); 1147 part_insert = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 1148 real_insert = bits(va, 9,9); 1149 pte.populate(data, bits(va,10,10) ? PageTableEntry::sun4v : 1150 PageTableEntry::sun4u); 1151 insert(va_insert, part_insert, ct_insert, real_insert, pte, entry_insert); 1152 break; 1153 case ASI_IMMU_DEMAP: 1154 ignore = false; 1155 ctx_id = -1; 1156 part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 1157 switch (bits(va,5,4)) { 1158 case 0: 1159 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT); 1160 break; 1161 case 1: 1162 ignore = true; 1163 break; 1164 case 3: 1165 ctx_id = 0; 1166 break; 1167 default: 1168 ignore = true; 1169 } 1170 1171 switch(bits(va,7,6)) { 1172 case 0: // demap page 1173 if (!ignore) 1174 tc->getITBPtr()->demapPage(mbits(va,63,13), part_id, 1175 bits(va,9,9), ctx_id); 1176 break; 1177 case 1: //demap context 1178 if (!ignore) 1179 tc->getITBPtr()->demapContext(part_id, ctx_id); 1180 break; 1181 case 2: 1182 tc->getITBPtr()->demapAll(part_id); 1183 break; 1184 default: 1185 panic("Invalid type for IMMU demap\n"); 1186 } 1187 break; 1188 case ASI_DMMU: 1189 switch (va) { 1190 case 0x18: 1191 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_SFSR, data); 1192 break; 1193 case 0x30: 1194 sext<59>(bits(data, 59,0)); 1195 tc->setMiscRegWithEffect(MISCREG_MMU_DTLB_TAG_ACCESS, data); 1196 break; 1197 case 0x80: 1198 tc->setMiscRegWithEffect(MISCREG_MMU_PART_ID, data); 1199 break; 1200 default: 1201 goto doMmuWriteError; 1202 } 1203 break; 1204 case ASI_DMMU_DEMAP: 1205 ignore = false; 1206 ctx_id = -1; 1207 part_id = tc->readMiscRegWithEffect(MISCREG_MMU_PART_ID); 1208 switch (bits(va,5,4)) { 1209 case 0: 1210 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_P_CONTEXT); 1211 break; 1212 case 1: 1213 ctx_id = tc->readMiscRegWithEffect(MISCREG_MMU_S_CONTEXT); 1214 break; 1215 case 3: 1216 ctx_id = 0; 1217 break; 1218 default: 1219 ignore = true; 1220 } 1221 1222 switch(bits(va,7,6)) { 1223 case 0: // demap page 1224 if (!ignore) 1225 demapPage(mbits(va,63,13), part_id, bits(va,9,9), ctx_id); 1226 break; 1227 case 1: //demap context 1228 if (!ignore) 1229 demapContext(part_id, ctx_id); 1230 break; 1231 case 2: 1232 demapAll(part_id); 1233 break; 1234 default: 1235 panic("Invalid type for IMMU demap\n"); 1236 } 1237 break; 1238 default: 1239doMmuWriteError: 1240 panic("need to impl DTB::doMmuRegWrite() got asi=%#x, va=%#x d=%#x\n", 1241 (uint32_t)pkt->req->getAsi(), pkt->getAddr(), data); 1242 } 1243 pkt->result = Packet::Success; 1244 return tc->getCpuPtr()->cycles(1); 1245} 1246 1247void 1248TLB::serialize(std::ostream &os) 1249{ 1250 SERIALIZE_SCALAR(size); 1251 SERIALIZE_SCALAR(usedEntries); 1252 SERIALIZE_SCALAR(lastReplaced); 1253 1254 // convert the pointer based free list into an index based one 1255 int *free_list = (int*)malloc(sizeof(int) * size); 1256 int cntr = 0; 1257 std::list<TlbEntry*>::iterator i; 1258 i = freeList.begin(); 1259 while (i != freeList.end()) { 1260 free_list[cntr++] = ((size_t)*i - (size_t)tlb)/ sizeof(TlbEntry); 1261 i++; 1262 } 1263 SERIALIZE_SCALAR(cntr); 1264 SERIALIZE_ARRAY(free_list, cntr); 1265 1266 for (int x = 0; x < size; x++) { 1267 nameOut(os, csprintf("%s.PTE%d", name(), x)); 1268 tlb[x].serialize(os); 1269 } 1270} 1271 1272void 1273TLB::unserialize(Checkpoint *cp, const std::string §ion) 1274{ 1275 int oldSize; 1276 1277 paramIn(cp, section, "size", oldSize); 1278 if (oldSize != size) 1279 panic("Don't support unserializing different sized TLBs\n"); 1280 UNSERIALIZE_SCALAR(usedEntries); 1281 UNSERIALIZE_SCALAR(lastReplaced); 1282 1283 int cntr; 1284 UNSERIALIZE_SCALAR(cntr); 1285 1286 int *free_list = (int*)malloc(sizeof(int) * cntr); 1287 freeList.clear(); 1288 UNSERIALIZE_ARRAY(free_list, cntr); 1289 for (int x = 0; x < cntr; x++) 1290 freeList.push_back(&tlb[free_list[x]]); 1291 1292 lookupTable.clear(); 1293 for (int x = 0; x < size; x++) { 1294 tlb[x].unserialize(cp, csprintf("%s.PTE%d", section, x)); 1295 if (tlb[x].valid) 1296 lookupTable.insert(tlb[x].range, &tlb[x]); 1297 1298 } 1299} 1300 1301 1302DEFINE_SIM_OBJECT_CLASS_NAME("SparcTLB", TLB) 1303 1304BEGIN_DECLARE_SIM_OBJECT_PARAMS(ITB) 1305 1306 Param<int> size; 1307 1308END_DECLARE_SIM_OBJECT_PARAMS(ITB) 1309 1310BEGIN_INIT_SIM_OBJECT_PARAMS(ITB) 1311 1312 INIT_PARAM_DFLT(size, "TLB size", 48) 1313 1314END_INIT_SIM_OBJECT_PARAMS(ITB) 1315 1316 1317CREATE_SIM_OBJECT(ITB) 1318{ 1319 return new ITB(getInstanceName(), size); 1320} 1321 1322REGISTER_SIM_OBJECT("SparcITB", ITB) 1323 1324BEGIN_DECLARE_SIM_OBJECT_PARAMS(DTB) 1325 1326 Param<int> size; 1327 1328END_DECLARE_SIM_OBJECT_PARAMS(DTB) 1329 1330BEGIN_INIT_SIM_OBJECT_PARAMS(DTB) 1331 1332 INIT_PARAM_DFLT(size, "TLB size", 64) 1333 1334END_INIT_SIM_OBJECT_PARAMS(DTB) 1335 1336 1337CREATE_SIM_OBJECT(DTB) 1338{ 1339 return new DTB(getInstanceName(), size); 1340} 1341 1342REGISTER_SIM_OBJECT("SparcDTB", DTB) 1343} 1344