/gem5/src/arch/arm/ |
H A D | types.hh | 88 // Bitfields to select mode. 471 // stay in the current mode, so we'll do that. 478 // Perform an interworking branch in ARM mode, a regular branch 670 opModeIs64(OperatingMode mode) argument 672 return ((OperatingMode64)(uint8_t)mode).width == 0; 676 opModeIsH(OperatingMode mode) argument 678 return (mode == MODE_EL1H || mode == MODE_EL2H || mode == MODE_EL3H); 682 opModeIsT(OperatingMode mode) argument 689 opModeToEL(OperatingMode mode) argument 718 unknownMode(OperatingMode mode) argument 744 unknownMode32(OperatingMode mode) argument [all...] |
H A D | tlb.cc | 137 ThreadContext *tc, Mode mode) const 264 // if we're currently in hyp mode 565 TLB::translateSe(const RequestPtr &req, ThreadContext *tc, Mode mode, argument 577 bool is_fetch = (mode == Execute); 578 bool is_write = (mode == Write); 584 // LPAE is always disabled in SE mode 601 return finalizePhysical(req, tc, mode); 605 TLB::checkPermissions(TlbEntry *te, const RequestPtr &req, Mode mode) argument 615 bool is_fetch = (mode == Execute); 616 bool is_write = (mode 783 checkPermissions64(TlbEntry *te, const RequestPtr &req, Mode mode, ThreadContext *tc) argument 1016 checkPAN(ThreadContext *tc, uint8_t ap, const RequestPtr &req, Mode mode) argument 1036 translateFs(const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool &delay, bool timing, TLB::ArmTranslationType tranType, bool functional) argument 1200 translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode, TLB::ArmTranslationType tranType) argument 1221 translateFunctional(const RequestPtr &req, ThreadContext *tc, Mode mode, TLB::ArmTranslationType tranType) argument 1242 translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, TLB::ArmTranslationType tranType) argument 1259 translateComplete(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, TLB::ArmTranslationType tranType, bool callFromS2) argument 1452 getTE(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, bool is_secure, TLB::ArmTranslationType tranType) argument 1519 getResultTe(TlbEntry **te, const RequestPtr &req, ThreadContext *tc, Mode mode, Translation *translation, bool timing, bool functional, TlbEntry *mergeTe) argument 1603 testTranslation(const RequestPtr &req, Mode mode, TlbEntry::DomainType domain) argument 1615 testWalk(Addr pa, Addr size, Addr va, bool is_secure, Mode mode, TlbEntry::DomainType domain, LookupLevel lookup_level) argument [all...] |
H A D | utility.hh | 123 return cpsr.mode == MODE_USER || cpsr.mode == MODE_EL0T; 150 return (OperatingMode) (uint8_t) cpsr.mode; 162 return opModeToEL((OperatingMode) (uint8_t)cpsr.mode); 196 * badMode is checking if the execution mode provided as an argument is 200 * @param mode OperatingMode to check 201 * @return false if mode is valid and implemented, true otherwise 203 bool badMode32(ThreadContext *tc, OperatingMode mode); 206 * badMode is checking if the execution mode provided as an argument is 210 * @param mode OperatingMod [all...] |
H A D | semihosting.hh | 61 * general syscall emulation mode. 119 : parent(_parent), _name(name), mode(_mode) {} 127 const char *mode); 202 std::string mode; member in class:ArmSemihosting::FileBase 210 const char *name, const char *mode); 225 File(ArmSemihosting &_parent, const char *name, const char *mode); 292 * @param aarch64 True if in aarc64 mode, false otherwise. 349 const std::string &name, const char *mode);
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/gem5/tests/ |
H A D | run.py | 101 def require_file(path, fatal=False, mode=os.F_OK): 114 if os.access(path, mode): 138 require_file(kvm_dev, fatal=fatal, mode=os.R_OK | os.W_OK) 150 # Since we're in batch mode, dont allow tcp socket connections 154 (category, mode, name, isa, opsys, config) = sys.argv[1].split('/')[-6:] 221 sys.path.append(joinpath(tests_root, category, mode, name)) 223 open(joinpath(tests_root, category, mode, name, 'test.py')).read(), \ 224 joinpath(tests_root, category, mode, name, 'test.py'), 'exec'))
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/gem5/src/arch/x86/ |
H A D | tlb.cc | 194 // TODO If CPL > IOPL or in virtual mode, check the I/O permission 228 ThreadContext *tc, Mode mode) const 271 Mode mode, bool &delayedResponse, bool timing) 290 // If protected mode has been enabled... 292 DPRINTF(TLB, "In protected mode.\n"); 293 // If we're not in 64-bit mode, do protection/limit checks 294 if (m5Reg.mode != LongMode) { 295 DPRINTF(TLB, "Not in long mode. Checking segment protection.\n"); 304 if (!attr.writable && (mode == Write || storeCheck)) 306 if (!attr.readable && mode 269 translate(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode, bool &delayedResponse, bool timing) argument 430 translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) argument 437 translateTiming(const RequestPtr &req, ThreadContext *tc, Translation *translation, Mode mode) argument [all...] |
H A D | intmessage.hh | 71 isReserved(int mode) argument 73 return mode == 3;
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/gem5/src/dev/ |
H A D | intel_8254_timer.cc | 69 counter[sel]->setMode(data.mode); 103 initial_count(0), latched_count(0), period(0), mode(0), 129 if (mode == RateGen || mode == SquareWave) 186 if (mode == RateGen || mode == SquareWave) 213 panic("PIT mode %#x is not implemented: \n", mode_val); 215 mode = mode_val; 237 paramOut(cp, base + ".mode", mode); [all...] |
/gem5/util/ |
H A D | find_copyrights.py | 9 mode_line = re.compile('(-\*- *mode:.* *-\*-)') 49 mode = None 54 if mode == 'C': 59 mode = None 69 if mode is None: 70 mode = 'CPP' 78 elif mode == 'CPP': 83 mode = None 88 assert mode is None, 'on line %d' % (i + 1) 89 mode [all...] |
/gem5/src/arch/mips/ |
H A D | tlb.hh | 116 const RequestPtr &req, ThreadContext *tc, Mode mode) override; 119 Translation *translation, Mode mode) override; 122 ThreadContext *tc, Mode mode) const override;
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H A D | tlb.cc | 315 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) 317 if (mode == Execute) 320 return translateData(req, tc, mode == Write); 325 Translation *translation, Mode mode) 328 translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 333 ThreadContext *tc, Mode mode) const
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H A D | dsp.hh | 158 int32_t dspMuleu(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl); 159 int32_t dspMuleq(int32_t a, int32_t b, int32_t mode, uint32_t *dspctl); 161 int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode, 164 int32_t infmt, int32_t outfmt, int32_t postsat, int32_t mode, 167 int32_t sign, int32_t mode); 169 int32_t sign, int32_t mode); 171 int32_t fmt, int32_t mode, int32_t saturate, uint32_t *dspctl); 181 int32_t outsign, int32_t mode);
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/gem5/src/arch/riscv/ |
H A D | tlb.hh | 115 const RequestPtr &req, ThreadContext *tc, Mode mode) override; 118 Translation *translation, Mode mode) override; 121 ThreadContext *tc, Mode mode) const override;
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/gem5/src/gpu-compute/ |
H A D | cl_driver.hh | 56 int open(ThreadContext *tc, int mode, int flags);
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/gem5/src/sim/ |
H A D | emul_driver.hh | 43 * EmulatedDriver is an abstract base class for fake SE-mode device drivers. 77 virtual int open(ThreadContext *tc, int mode, int flags) = 0;
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/gem5/tests/testing/ |
H A D | tests.py | 51 "mode", 60 # (typically SE mode tests). In both cases, the configuration name 270 ct.category, ct.mode, ct.workload, 326 isa, cat, mode = _filter 332 mode = all_modes if mode in wildcards else (mode, ) 334 return isa, cat, mode 364 for mode in modes: 365 mode_dir = os.path.join(_test_base, cat, mode) [all...] |
/gem5/src/base/ |
H A D | output.cc | 85 std::ios_base::openmode mode, 88 _mode(mode), _recreateable(recreateable), 212 const ios_base::openmode mode( 216 return open(name, mode, recreateable, no_gz); 221 ios_base::openmode mode, 229 // correct mode for gzofstream as this used directly to set the file 230 // mode. 231 mode |= std::ios::out; 232 os = new OutputFile<gzofstream>(*this, name, mode, recreateable); 234 os = new OutputFile<ofstream>(*this, name, mode, recreateabl 83 OutputFile(const OutputDirectory &dir, const std::string &name, std::ios_base::openmode mode, bool recreateable) argument 220 open(const std::string &name, ios_base::openmode mode, bool recreateable, bool no_gz) argument [all...] |
/gem5/ext/pybind11/tests/ |
H A D | test_enum.cpp | 58 static EMode test_function(EMode mode) { argument 59 return mode;
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/gem5/src/arch/power/ |
H A D | tlb.cc | 313 TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode) 316 fatal("translate atomic not yet implemented in full system mode.\n"); 318 if (mode == Execute) 321 return translateData(req, tc, mode == Write); 326 Translation *translation, Mode mode) 329 translation->finish(translateAtomic(req, tc, mode), req, tc, mode); 334 ThreadContext *tc, Mode mode) const
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H A D | tlb.hh | 166 const RequestPtr &req, ThreadContext *tc, Mode mode) override; 169 Translation *translation, Mode mode) override; 172 ThreadContext *tc, Mode mode) const override;
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/gem5/util/style/ |
H A D | file_types.py | 175 mode = 'r+' 177 mode = 'r' 178 src = file(src, mode)
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/gem5/src/arch/alpha/ |
H A D | tlb.hh | 145 const RequestPtr &req, ThreadContext *tc, Mode mode) override; 148 Translation *translation, Mode mode) override; 151 Mode mode) const override;
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/gem5/tests/test-progs/asmtest/src/riscv/isa/rv64mi/ |
H A D | mcsr.S | 7 # Test various M-mode CSRs.
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H A D | breakpoint.S | 16 # Set up breakpoint to trap on M-mode fetches. 48 # Set up breakpoint to trap on M-mode reads. 68 # Set up breakpoint to trap on M-mode stores.
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/gem5/src/arch/arm/insts/ |
H A D | mem.cc | 84 switch (mode) { 109 switch (mode) {
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