1/*
2 * Copyright (c) 2001-2005 The Regents of The University of Michigan
3 * Copyright (c) 2007 MIPS Technologies, Inc.
4 * Copyright (c) 2007-2008 The Florida State University
5 * Copyright (c) 2009 The University of Edinburgh
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions are
10 * met: redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer;
12 * redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution;
15 * neither the name of the copyright holders nor the names of its
16 * contributors may be used to endorse or promote products derived from
17 * this software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
20 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
21 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
22 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
23 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
24 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
25 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
29 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 *
31 * Authors: Nathan Binkert
32 *          Steve Reinhardt
33 *          Jaidev Patwardhan
34 *          Stephen Hines
35 *          Timothy M. Jones
36 */
37
38#include "arch/power/tlb.hh"
39
40#include <string>
41#include <vector>
42
43#include "arch/power/faults.hh"
44#include "arch/power/pagetable.hh"
45#include "arch/power/utility.hh"
46#include "base/inifile.hh"
47#include "base/str.hh"
48#include "base/trace.hh"
49#include "cpu/thread_context.hh"
50#include "debug/Power.hh"
51#include "debug/TLB.hh"
52#include "mem/page_table.hh"
53#include "params/PowerTLB.hh"
54#include "sim/full_system.hh"
55#include "sim/process.hh"
56
57using namespace std;
58using namespace PowerISA;
59
60///////////////////////////////////////////////////////////////////////
61//
62//  POWER TLB
63//
64
65#define MODE2MASK(X) (1 << (X))
66
67TLB::TLB(const Params *p)
68    : BaseTLB(p), size(p->size), nlu(0)
69{
70    table = new PowerISA::PTE[size];
71    memset(table, 0, sizeof(PowerISA::PTE[size]));
72    smallPages = 0;
73}
74
75TLB::~TLB()
76{
77    if (table)
78        delete [] table;
79}
80
81// look up an entry in the TLB
82PowerISA::PTE *
83TLB::lookup(Addr vpn, uint8_t asn) const
84{
85    // assume not found...
86    PowerISA::PTE *retval = NULL;
87    PageTable::const_iterator i = lookupTable.find(vpn);
88    if (i != lookupTable.end()) {
89        while (i->first == vpn) {
90            int index = i->second;
91            PowerISA::PTE *pte = &table[index];
92            Addr Mask = pte->Mask;
93            Addr InvMask = ~Mask;
94            Addr VPN  = pte->VPN;
95            if (((vpn & InvMask) == (VPN & InvMask))
96               && (pte->G  || (asn == pte->asid))) {
97
98                // We have a VPN + ASID Match
99                retval = pte;
100                break;
101            }
102            ++i;
103        }
104    }
105
106    DPRINTF(TLB, "lookup %#x, asn %#x -> %s ppn %#x\n", vpn, (int)asn,
107            retval ? "hit" : "miss", retval ? retval->PFN1 : 0);
108    return retval;
109}
110
111PowerISA::PTE*
112TLB::getEntry(unsigned Index) const
113{
114    // Make sure that Index is valid
115    assert(Index<size);
116    return &table[Index];
117}
118
119int
120TLB::probeEntry(Addr vpn,uint8_t asn) const
121{
122    // assume not found...
123    int Ind = -1;
124    PageTable::const_iterator i = lookupTable.find(vpn);
125    if (i != lookupTable.end()) {
126        while (i->first == vpn) {
127            int index = i->second;
128            PowerISA::PTE *pte = &table[index];
129            Addr Mask = pte->Mask;
130            Addr InvMask = ~Mask;
131            Addr VPN  = pte->VPN;
132            if (((vpn & InvMask) == (VPN & InvMask))
133                && (pte->G  || (asn == pte->asid))) {
134
135                // We have a VPN + ASID Match
136                Ind = index;
137                break;
138            }
139            ++i;
140        }
141    }
142
143    DPRINTF(Power, "VPN: %x, asid: %d, Result of TLBP: %d\n", vpn, asn, Ind);
144    return Ind;
145}
146
147inline Fault
148TLB::checkCacheability(const RequestPtr &req)
149{
150    Addr VAddrUncacheable = 0xA0000000;
151    if ((req->getVaddr() & VAddrUncacheable) == VAddrUncacheable) {
152
153        // mark request as uncacheable
154        req->setFlags(Request::UNCACHEABLE | Request::STRICT_ORDER);
155    }
156    return NoFault;
157}
158
159void
160TLB::insertAt(PowerISA::PTE &pte, unsigned Index, int _smallPages)
161{
162    smallPages=_smallPages;
163    if (Index > size){
164        warn("Attempted to write at index (%d) beyond TLB size (%d)",
165             Index, size);
166    } else {
167
168        // Update TLB
169        if (table[Index].V0 || table[Index].V1) {
170
171            // Previous entry is valid
172            PageTable::iterator i = lookupTable.find(table[Index].VPN);
173            lookupTable.erase(i);
174        }
175        table[Index]=pte;
176
177        // Update fast lookup table
178        lookupTable.insert(make_pair(table[Index].VPN, Index));
179    }
180}
181
182// insert a new TLB entry
183void
184TLB::insert(Addr addr, PowerISA::PTE &pte)
185{
186    fatal("TLB Insert not yet implemented\n");
187}
188
189void
190TLB::flushAll()
191{
192    DPRINTF(TLB, "flushAll\n");
193    memset(table, 0, sizeof(PowerISA::PTE[size]));
194    lookupTable.clear();
195    nlu = 0;
196}
197
198void
199TLB::serialize(CheckpointOut &cp) const
200{
201    SERIALIZE_SCALAR(size);
202    SERIALIZE_SCALAR(nlu);
203
204    for (int i = 0; i < size; i++) {
205        ScopedCheckpointSection sec(cp, csprintf("PTE%d", i));
206        table[i].serialize(cp);
207    }
208}
209
210void
211TLB::unserialize(CheckpointIn &cp)
212{
213    UNSERIALIZE_SCALAR(size);
214    UNSERIALIZE_SCALAR(nlu);
215
216    for (int i = 0; i < size; i++) {
217        ScopedCheckpointSection sec(cp, csprintf("PTE%d", i));
218        if (table[i].V0 || table[i].V1) {
219            lookupTable.insert(make_pair(table[i].VPN, i));
220        }
221    }
222}
223
224void
225TLB::regStats()
226{
227    BaseTLB::regStats();
228
229    read_hits
230        .name(name() + ".read_hits")
231        .desc("DTB read hits")
232        ;
233
234    read_misses
235        .name(name() + ".read_misses")
236        .desc("DTB read misses")
237        ;
238
239
240    read_accesses
241        .name(name() + ".read_accesses")
242        .desc("DTB read accesses")
243        ;
244
245    write_hits
246        .name(name() + ".write_hits")
247        .desc("DTB write hits")
248        ;
249
250    write_misses
251        .name(name() + ".write_misses")
252        .desc("DTB write misses")
253        ;
254
255
256    write_accesses
257        .name(name() + ".write_accesses")
258        .desc("DTB write accesses")
259        ;
260
261    hits
262        .name(name() + ".hits")
263        .desc("DTB hits")
264        ;
265
266    misses
267        .name(name() + ".misses")
268        .desc("DTB misses")
269        ;
270
271    accesses
272        .name(name() + ".accesses")
273        .desc("DTB accesses")
274        ;
275
276    hits = read_hits + write_hits;
277    misses = read_misses + write_misses;
278    accesses = read_accesses + write_accesses;
279}
280
281Fault
282TLB::translateInst(const RequestPtr &req, ThreadContext *tc)
283{
284    // Instruction accesses must be word-aligned
285    if (req->getVaddr() & 0x3) {
286        DPRINTF(TLB, "Alignment Fault on %#x, size = %d\n", req->getVaddr(),
287                req->getSize());
288        return std::make_shared<AlignmentFault>();
289    }
290
291     Process * p = tc->getProcessPtr();
292
293     Fault fault = p->pTable->translate(req);
294    if (fault != NoFault)
295        return fault;
296
297    return NoFault;
298}
299
300Fault
301TLB::translateData(const RequestPtr &req, ThreadContext *tc, bool write)
302{
303    Process * p = tc->getProcessPtr();
304
305    Fault fault = p->pTable->translate(req);
306    if (fault != NoFault)
307        return fault;
308
309    return NoFault;
310}
311
312Fault
313TLB::translateAtomic(const RequestPtr &req, ThreadContext *tc, Mode mode)
314{
315    if (FullSystem)
316        fatal("translate atomic not yet implemented in full system mode.\n");
317
318    if (mode == Execute)
319        return translateInst(req, tc);
320    else
321        return translateData(req, tc, mode == Write);
322}
323
324void
325TLB::translateTiming(const RequestPtr &req, ThreadContext *tc,
326                     Translation *translation, Mode mode)
327{
328    assert(translation);
329    translation->finish(translateAtomic(req, tc, mode), req, tc, mode);
330}
331
332Fault
333TLB::finalizePhysical(const RequestPtr &req,
334                      ThreadContext *tc, Mode mode) const
335{
336    return NoFault;
337}
338
339PowerISA::PTE &
340TLB::index(bool advance)
341{
342    PowerISA::PTE *pte = &table[nlu];
343
344    if (advance)
345        nextnlu();
346
347    return *pte;
348}
349
350PowerISA::TLB *
351PowerTLBParams::create()
352{
353    return new PowerISA::TLB(this);
354}
355