1/*
2 * Copyright (c) 2010, 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42
43#include "arch/arm/insts/mem.hh"
44
45#include "base/loader/symtab.hh"
46
47using namespace std;
48
49namespace ArmISA
50{
51
52void
53MemoryReg::printOffset(std::ostream &os) const
54{
55    if (!add)
56        os << "-";
57    printIntReg(os, index);
58    if (shiftType != LSL || shiftAmt != 0) {
59        switch (shiftType) {
60          case LSL:
61            ccprintf(os, " LSL #%d", shiftAmt);
62            break;
63          case LSR:
64            ccprintf(os, " LSR #%d", (shiftAmt == 0) ? 32 : shiftAmt);
65            break;
66          case ASR:
67            ccprintf(os, " ASR #%d", (shiftAmt == 0) ? 32 : shiftAmt);
68            break;
69          case ROR:
70            if (shiftAmt == 0) {
71                ccprintf(os, " RRX");
72            } else {
73                ccprintf(os, " ROR #%d", shiftAmt);
74            }
75            break;
76        }
77    }
78}
79
80string
81RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
82{
83    stringstream ss;
84    switch (mode) {
85      case DecrementAfter:
86        printMnemonic(ss, "da");
87        break;
88      case DecrementBefore:
89        printMnemonic(ss, "db");
90        break;
91      case IncrementAfter:
92        printMnemonic(ss, "ia");
93        break;
94      case IncrementBefore:
95        printMnemonic(ss, "ib");
96        break;
97    }
98    printIntReg(ss, base);
99    if (wb) {
100        ss << "!";
101    }
102    return ss.str();
103}
104
105string
106SrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
107{
108    stringstream ss;
109    switch (mode) {
110      case DecrementAfter:
111        printMnemonic(ss, "da");
112        break;
113      case DecrementBefore:
114        printMnemonic(ss, "db");
115        break;
116      case IncrementAfter:
117        printMnemonic(ss, "ia");
118        break;
119      case IncrementBefore:
120        printMnemonic(ss, "ib");
121        break;
122    }
123    printIntReg(ss, INTREG_SP);
124    if (wb) {
125        ss << "!";
126    }
127    ss << ", #";
128    switch (regMode) {
129      case MODE_USER:
130        ss << "user";
131        break;
132      case MODE_FIQ:
133        ss << "fiq";
134        break;
135      case MODE_IRQ:
136        ss << "irq";
137        break;
138      case MODE_SVC:
139        ss << "supervisor";
140        break;
141      case MODE_MON:
142        ss << "monitor";
143        break;
144      case MODE_ABORT:
145        ss << "abort";
146        break;
147      case MODE_HYP:
148        ss << "hyp";
149        break;
150      case MODE_UNDEFINED:
151        ss << "undefined";
152        break;
153      case MODE_SYSTEM:
154        ss << "system";
155        break;
156      default:
157        ss << "unrecognized";
158        break;
159    }
160    return ss.str();
161}
162
163void
164Memory::printInst(std::ostream &os, AddrMode addrMode) const
165{
166    printMnemonic(os);
167    printDest(os);
168    os << ", [";
169    printIntReg(os, base);
170    if (addrMode != AddrMd_PostIndex) {
171        os << ", ";
172        printOffset(os);
173        os << "]";
174        if (addrMode == AddrMd_PreIndex) {
175            os << "!";
176        }
177    } else {
178        os << "] ";
179        printOffset(os);
180
181    }
182}
183
184}
185