arch-arm: Remove SWP and SWPB instructions

The SWP and SWPB instructions have been removed from AArch32. It was
previously (ARMv7) possible to enable them with the ID_ISAR0.Swap bits,
which are now hardcoded to 0b0000 (SWP and SWPB not implemented)

Change-Id: Ic32b534454a7e0f7494a6f0b5e11182c65b3fe24
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/15815
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch, cpu: Architectural Register structural indexing

Replace the unified register mapping with a structure associating
a class and an index. It is now much easier to know which class of
register the index is referring to. Also, when adding a new class
there is no need to modify existing ones.

Change-Id: I55b3ac80763702aa2cd3ed2cbff0a75ef7620373
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
[ Fix RISCV build issues ]
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/2700

style: [patch 1/22] use /r/3648/ to reorganize includes

arm: Add support for ARMv8 (AArch64 & AArch32)

Note: AArch64 and AArch32 interworking is not supported. If you use an AArch64
kernel you are restricted to AArch64 user-mode binaries. This will be addressed
in a later patch.

Note: Virtualization is only supported in AArch32 mode. This will also be fixed
in a later patch.

Contributors:
Giacomo Gabrielli (TrustZone, LPAE, system-level AArch64, AArch64 NEON, validation)
Thomas Grocutt (AArch32 Virtualization, AArch64 FP, validation)
Mbou Eyole (AArch64 NEON, validation)
Ali Saidi (AArch64 Linux support, code integration, validation)
Edmund Grimley-Evans (AArch64 FP)
William Wang (AArch64 Linux support)
Rene De Jong (AArch64 Linux support, performance opt.)
Matt Horsnell (AArch64 MP, validation)
Matt Evans (device models, code integration, validation)
Chris Adeniyi-Jones (AArch64 syscall-emulation)
Prakash Ramrakhyani (validation)
Dam Sunwoo (validation)
Chander Sudanthi (validation)
Stephan Diestelhorst (validation)
Andreas Hansson (code integration, performance opt.)
Eric Van Hensbergen (performance opt.)
Gabe Black

ARM: Make some of the trace code more compact

ARM: Move the longer MemoryReg::printoffset function in mem.hh into the cc file.

ARM: Implement the SRS instruction.

ARM: Add a base class for SRS.

ARM: Add a base class for the RFE instruction.

ARM: Explicitly keep track of the second destination for double loads/stores.

ARM: Implement the swp and swpb instructions.

ARM: Remove the special naming for the new memory instructions.
These are the only memory instructions now.

ARM: Eliminate the old memory formats which are no longer used.

ARM: Implement a new set of base classes for non macro memory instructions.

ARM: Improve memory instruction disassembly.

ARM: Write a function for printing mnemonics and predicates.

ARM: Simplify the ISA desc by pulling some classes out of it.