mem.cc revision 7429:af0e80844b14
112097Sandreas.sandberg@arm.com/* 212097Sandreas.sandberg@arm.com * Copyright (c) 2010 ARM Limited 312097Sandreas.sandberg@arm.com * All rights reserved 412097Sandreas.sandberg@arm.com * 512097Sandreas.sandberg@arm.com * The license below extends only to copyright in the software and shall 612097Sandreas.sandberg@arm.com * not be construed as granting a license to any other intellectual 712097Sandreas.sandberg@arm.com * property including but not limited to intellectual property relating 812097Sandreas.sandberg@arm.com * to a hardware implementation of the functionality of the software 912097Sandreas.sandberg@arm.com * licensed hereunder. You may use the software subject to the license 1012097Sandreas.sandberg@arm.com * terms below provided that you ensure that this notice is replicated 1112097Sandreas.sandberg@arm.com * unmodified and in its entirety in all distributions of the software, 1212097Sandreas.sandberg@arm.com * modified or unmodified, in source code or in binary form. 1312097Sandreas.sandberg@arm.com * 1412097Sandreas.sandberg@arm.com * Copyright (c) 2007-2008 The Florida State University 1512097Sandreas.sandberg@arm.com * All rights reserved. 1612097Sandreas.sandberg@arm.com * 1712097Sandreas.sandberg@arm.com * Redistribution and use in source and binary forms, with or without 1812097Sandreas.sandberg@arm.com * modification, are permitted provided that the following conditions are 1912097Sandreas.sandberg@arm.com * met: redistributions of source code must retain the above copyright 2012097Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer; 2112097Sandreas.sandberg@arm.com * redistributions in binary form must reproduce the above copyright 2212097Sandreas.sandberg@arm.com * notice, this list of conditions and the following disclaimer in the 2312097Sandreas.sandberg@arm.com * documentation and/or other materials provided with the distribution; 2412097Sandreas.sandberg@arm.com * neither the name of the copyright holders nor the names of its 2512097Sandreas.sandberg@arm.com * contributors may be used to endorse or promote products derived from 2612097Sandreas.sandberg@arm.com * this software without specific prior written permission. 2712097Sandreas.sandberg@arm.com * 2812097Sandreas.sandberg@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2912097Sandreas.sandberg@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3012097Sandreas.sandberg@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3112097Sandreas.sandberg@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3212097Sandreas.sandberg@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3312097Sandreas.sandberg@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3412097Sandreas.sandberg@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3512097Sandreas.sandberg@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3612097Sandreas.sandberg@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3713774Sandreas.sandberg@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3813774Sandreas.sandberg@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3913774Sandreas.sandberg@arm.com * 40 * Authors: Stephen Hines 41 */ 42 43#include "arch/arm/insts/mem.hh" 44#include "base/loader/symtab.hh" 45 46using namespace std; 47 48namespace ArmISA 49{ 50 51void 52MemoryReg::printOffset(std::ostream &os) const 53{ 54 if (!add) 55 os << "-"; 56 printReg(os, index); 57 if (shiftType != LSL || shiftAmt != 0) { 58 switch (shiftType) { 59 case LSL: 60 ccprintf(os, " LSL #%d", shiftAmt); 61 break; 62 case LSR: 63 ccprintf(os, " LSR #%d", (shiftAmt == 0) ? 32 : shiftAmt); 64 break; 65 case ASR: 66 ccprintf(os, " ASR #%d", (shiftAmt == 0) ? 32 : shiftAmt); 67 break; 68 case ROR: 69 if (shiftAmt == 0) { 70 ccprintf(os, " RRX"); 71 } else { 72 ccprintf(os, " ROR #%d", shiftAmt); 73 } 74 break; 75 } 76 } 77} 78 79string 80Swap::generateDisassembly(Addr pc, const SymbolTable *symtab) const 81{ 82 stringstream ss; 83 printMnemonic(ss); 84 printReg(ss, dest); 85 ss << ", "; 86 printReg(ss, op1); 87 ss << ", ["; 88 printReg(ss, base); 89 ss << "]"; 90 return ss.str(); 91} 92 93string 94RfeOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 95{ 96 stringstream ss; 97 switch (mode) { 98 case DecrementAfter: 99 printMnemonic(ss, "da"); 100 break; 101 case DecrementBefore: 102 printMnemonic(ss, "db"); 103 break; 104 case IncrementAfter: 105 printMnemonic(ss, "ia"); 106 break; 107 case IncrementBefore: 108 printMnemonic(ss, "ib"); 109 break; 110 } 111 printReg(ss, base); 112 if (wb) { 113 ss << "!"; 114 } 115 return ss.str(); 116} 117 118string 119SrsOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 120{ 121 stringstream ss; 122 switch (mode) { 123 case DecrementAfter: 124 printMnemonic(ss, "da"); 125 break; 126 case DecrementBefore: 127 printMnemonic(ss, "db"); 128 break; 129 case IncrementAfter: 130 printMnemonic(ss, "ia"); 131 break; 132 case IncrementBefore: 133 printMnemonic(ss, "ib"); 134 break; 135 } 136 printReg(ss, INTREG_SP); 137 if (wb) { 138 ss << "!"; 139 } 140 ss << ", #"; 141 switch (regMode) { 142 case MODE_USER: 143 ss << "user"; 144 break; 145 case MODE_FIQ: 146 ss << "fiq"; 147 break; 148 case MODE_IRQ: 149 ss << "irq"; 150 break; 151 case MODE_SVC: 152 ss << "supervisor"; 153 break; 154 case MODE_MON: 155 ss << "monitor"; 156 break; 157 case MODE_ABORT: 158 ss << "abort"; 159 break; 160 case MODE_UNDEFINED: 161 ss << "undefined"; 162 break; 163 case MODE_SYSTEM: 164 ss << "system"; 165 break; 166 default: 167 ss << "unrecognized"; 168 break; 169 } 170 return ss.str(); 171} 172 173void 174Memory::printInst(std::ostream &os, AddrMode addrMode) const 175{ 176 printMnemonic(os); 177 printDest(os); 178 os << ", ["; 179 printReg(os, base); 180 if (addrMode != AddrMd_PostIndex) { 181 os << ", "; 182 printOffset(os); 183 os << "]"; 184 if (addrMode == AddrMd_PreIndex) { 185 os << "!"; 186 } 187 } else { 188 os << "] "; 189 printOffset(os); 190 191 } 192} 193 194} 195