| /gem5/tests/gem5/memory/ |
| H A D | simple-run.py | 70 clk_domain = SrcClockDomain(clock = '1GHz', variable
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| /gem5/configs/example/ |
| H A D | fs.py | 115 test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
144 test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
156 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
167 cpu.clk_domain = test_sys.cpu_clk_domain
259 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
270 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
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| H A D | ruby_gpu_random_test.py | 135 system.clk_domain = SrcClockDomain(clock=options.sys_clock,
141 system.ruby.clk_domain = SrcClockDomain(clock=options.ruby_clock,
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| H A D | garnet_synth_traffic.py | 123 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
129 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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| H A D | se.py | 188 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
207 cpu.clk_domain = system.cpu_clk_domain
253 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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| H A D | apu_se.py | 204 clk_domain = SrcClockDomain( variable
317 clk_domain = SrcClockDomain( variable
334 clk_domain = SrcClockDomain( variable
343 clk_domain = SrcClockDomain( variable
428 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
448 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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| H A D | hmctest.py | 59 system.clk_domain = SrcClockDomain(clock=clk, voltage_domain=vd)
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| H A D | memtest.py | 231 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
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| H A D | memcheck.py | 226 system.clk_domain = SrcClockDomain(clock = options.sys_clock,
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| /gem5/configs/common/ |
| H A D | GPUTLBConfig.py | 52 clk_domain = SrcClockDomain(\
64 clk_domain = SrcClockDomain(\
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| H A D | Simulation.py | 473 switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain
516 repeat_switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain
545 switch_cpus[i].clk_domain = testsys.cpu[i].clk_domain
546 switch_cpus_1[i].clk_domain = testsys.cpu[i].clk_domain
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| H A D | CacheConfig.py | 101 system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
105 system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
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| H A D | HMC.py | 312 system.membus.clk_domain = cd
356 system.hmc_host.seriallink[i].clk_domain = scd
416 system.hmc_dev.xbar[i].clk_domain = scd
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| /gem5/configs/example/arm/ |
| H A D | starter_se.py | 99 self.clk_domain = SrcClockDomain(clock="1GHz",
122 self.cpu_cluster.addL2(self.cpu_cluster.clk_domain)
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| /gem5/util/tlm/conf/ |
| H A D | tlm_elastic_slave.py | 80 system.clk_domain = SrcClockDomain(clock = '1GHz',
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| /gem5/util/tlm/examples/ |
| H A D | tlm_elastic_slave_with_l2.py | 87 system.clk_domain = SrcClockDomain(clock = '1GHz',
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| /gem5/tests/configs/ |
| H A D | gpu-ruby.py | 174 clk_domain = SrcClockDomain( variable
268 system.clk_domain = SrcClockDomain(clock = '1GHz',
273 system.cpu[0].clk_domain = SrcClockDomain(clock = '2GHz',
286 system.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
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| /gem5/src/sim/ |
| H A D | clocked_object.cc | 47 SimObject(p), Clocked(*p->clk_domain),
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| /gem5/configs/dram/ |
| H A D | sweep.py | 97 system.clk_domain = SrcClockDomain(clock = '2.0GHz',
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| H A D | low_power_sweep.py | 93 system.clk_domain = SrcClockDomain(clock = '2.0GHz',
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| H A D | lat_mem_rd.py | 105 system.clk_domain = SrcClockDomain(clock = '2.0GHz',
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| /gem5/src/gpu-compute/ |
| H A D | shader.cc | 54 : ClockedObject(p), clock(p->clk_domain->clockPeriod()),
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| H A D | tlb_coalescer.cc | 46 clock(p->clk_domain->clockPeriod()),
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| H A D | compute_unit.cc | 77 req_tick_latency(p->mem_req_latency * p->clk_domain->clockPeriod()),
78 resp_tick_latency(p->mem_resp_latency * p->clk_domain->clockPeriod()),
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| /gem5/src/cpu/ |
| H A D | BaseCPU.py | 328 freq = int(self.clk_domain.unproxy(self).clock[0].frequency)
|