Searched refs:BaseTLB (Results 51 - 75 of 75) sorted by relevance

123

/gem5/src/cpu/o3/
H A D	thread_context.hh	82 BaseTLB *getITBPtr() override { return cpu->itb; } 85 BaseTLB *getDTBPtr() override { return cpu->dtb; }
H A D	lsq.hh	232 class LSQRequest : public BaseTLB::Translation 732 ThreadContext* tc, BaseTLB::Mode mode); 804 ThreadContext* tc, BaseTLB::Mode mode);
H A D	cpu.hh	127 BaseTLB *itb; 128 BaseTLB *dtb;
H A D	lsq_impl.hh	774 ThreadContext* tc, BaseTLB::Mode mode) 807 ThreadContext* tc, BaseTLB::Mode mode) 981 this->isLoad() ? BaseTLB::Read : BaseTLB::Write);
H A D	lsq_unit.hh	384 BaseTLB* dTLB() { return cpu->dtb; }
H A D	fetch_impl.hh	648 trans, BaseTLB::Execute);
/gem5/src/gpu-compute/
H A D	gpu_tlb.cc	740 if (!attr.writable && (mode == BaseTLB::Write || 744 if (!attr.readable && mode == BaseTLB::Read) 802 if (!pte && mode != BaseTLB::Execute) { 843 if ((inUser && !entry->user) || (mode == BaseTLB::Write && 856 BaseTLB::Write, 1139 (mode == BaseTLB::Write && badWrite)) { 1329 if (!pte && sender_state->tlbMode != BaseTLB::Execute && 1533 if (!pte && sender_state->tlbMode != BaseTLB::Execute &&
H A D	tlb_coalescer.cc	122 BaseTLB::Mode incoming_mode = incoming_state->tlbMode; 123 BaseTLB::Mode coalesced_mode = coalesced_state->tlbMode;
H A D	compute_unit.cc	756 BaseTLB::Mode TLB_mode; 760 // since atomic operations should use BaseTLB::Write 762 TLB_mode = BaseTLB::Write; 764 TLB_mode = BaseTLB::Read; 1105 BaseTLB::Mode TLB_mode = translation_state->tlbMode;
/gem5/src/cpu/
H A D	BaseCPU.py	183 dtb = Param.BaseTLB(ArchDTB(), "Data TLB") 184 itb = Param.BaseTLB(ArchITB(), "Instruction TLB")
H A D	base.hh	642 void mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb);
H A D	base.cc	316 BaseCPU::mwaitAtomic(ThreadID tid, ThreadContext *tc, BaseTLB *dtb) 337 Fault fault = dtb->translateAtomic(req, tc, BaseTLB::Read);
/gem5/src/cpu/minor/
H A D	lsq.cc	264 ThreadContext *tc, BaseTLB::Mode mode) 310 request, thread, this, (isLoad ? BaseTLB::Read : BaseTLB::Write)); 328 ThreadContext *tc, BaseTLB::Mode mode) 716 BaseTLB::Read : BaseTLB::Write));
H A D	fetch1.cc	192 request, BaseTLB::Execute); 241 ThreadContext *tc, BaseTLB::Mode mode)
/gem5/src/arch/x86/
H A D	tlb.cc	63 : BaseTLB(p), configAddress(0), size(p->size), 460 BaseTLB::regStats();
/gem5/src/cpu/checker/
H A D	thread_context.hh	117 BaseTLB *getITBPtr() override { return actualTC->getITBPtr(); } 119 BaseTLB *getDTBPtr() override { return actualTC->getDTBPtr(); }
H A D	cpu_impl.hh	257 mem_req, tc, BaseTLB::Execute);
/gem5/src/mem/cache/prefetch/
H A D	base.cc	259 BasePrefetcher::addTLB(BaseTLB *t)
/gem5/src/arch/alpha/
H A D	tlb.cc	67 : BaseTLB(p), table(p->size), nlu(0) 79 BaseTLB::regStats();
/gem5/src/cpu/kvm/
H A D	base.cc	1128 BaseTLB::Mode tlb_mode(write ? BaseTLB::Write : BaseTLB::Read);
/gem5/src/arch/arm/
H A D	tlb.cc	77 : BaseTLB(p), table(new TlbEntry[p->size]), size(p->size), 384 TLB::takeOverFrom(BaseTLB *_otlb) 444 BaseTLB::regStats();
H A D	table_walker.hh	783 BaseTLB::Mode mode;
H A D	table_walker.cc	140 mode(BaseTLB::Read), tranType(TLB::NormalTran), l2Desc(l1Desc),
/gem5/src/arch/arm/tracers/
H A D	tarmac_parser.cc	1060 Fault fault = dtb->translateAtomic(req, thread, BaseTLB::Read);
/gem5/src/arch/sparc/
H A D	tlb.cc	56 : BaseTLB(p), size(p->size), usedEntries(0), lastReplaced(0),

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Indexes created Thu Sep 26 06:36:22 EDT 2019