Searched refs:BaseCPU (Results 51 - 73 of 73) sorted by relevance

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/gem5/src/cpu/
H A Dsimple_thread.hh71 class BaseCPU;
138 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
142 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system,
191 BaseCPU *getCpuPtr() override { return baseCpu; }
H A DBaseCPU.py113 class BaseCPU(ClockedObject): class in inherits:ClockedObject
114 type = 'BaseCPU'
166 checker = Param.BaseCPU(NULL, "checker CPU")
H A Dbase_dyn_inst.hh159 BaseCPU *getCpuPtr() { return cpu; }
/gem5/src/cpu/minor/
H A Dpipeline.cc57 Ticked(cpu_, &(cpu_.BaseCPU::numCycles)),
H A Dfetch2.cc332 (line_in->pc.instAddr() & BaseCPU::PCMask) -
H A Dexec_context.hh443 BaseCPU *getCpuPtr() { return &cpu; }
/gem5/src/cpu/trace/
H A Dtrace_cpu.hh71 * The TraceCPU inherits from BaseCPU so some virtual methods need to be
144 class TraceCPU : public BaseCPU
154 * This is a pure virtual function in BaseCPU. As we don't know how many
182 /* Pure virtual function in BaseCPU. Do nothing. */
191 * BaseCPU. It unbinds the ports of the old CPU and binds the ports of the
194 void takeOverFrom(BaseCPU *oldCPU);
H A Dtrace_cpu.cc50 : BaseCPU(params),
106 TraceCPU::takeOverFrom(BaseCPU *oldCPU)
121 BaseCPU::init();
220 BaseCPU::regStats();
/gem5/src/arch/mips/
H A Disa.cc519 ISA::scheduleCP0Update(BaseCPU *cpu, Cycles delay)
533 ISA::updateCPU(BaseCPU *cpu)
562 ISA::processCP0Event(BaseCPU *cpu, CP0EventType cp0EventType)
/gem5/src/cpu/o3/
H A Dcpu.hh83 class BaseO3CPU : public BaseCPU
309 void takeOverFrom(BaseCPU *oldCPU) override;
H A Dfetch_impl.hh1184 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1272 fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1364 fetchAddr = thisPC.instAddr() & BaseCPU::PCMask;
1409 fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
1613 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
H A Dthread_context.hh102 BaseCPU *getCpuPtr() override { return cpu; }
/gem5/src/arch/arm/linux/
H A Dsystem.cc255 if (pid != BaseCPU::invldPid) {
/gem5/src/cpu/checker/
H A Dcpu.cc69 : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
H A Dthread_context.hh93 BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); }
H A Dcpu_impl.hh453 Checker<Impl>::takeOverFrom(BaseCPU *oldCPU)
/gem5/src/cpu/simple/
H A Dtiming.hh278 void takeOverFrom(BaseCPU *oldCPU) override;
/gem5/src/arch/sparc/
H A Disa.cc685 BaseCPU *cpu = NULL;
771 BaseCPU *cpu = NULL;
/gem5/src/gpu-compute/
H A Dshader.cc132 Shader::hostWakeUp(BaseCPU *cpu) {
H A Ddispatcher.cc355 GpuDispatcher::accessUserVar(BaseCPU *cpu, uint64_t addr, int val, int off)
/gem5/src/python/m5/util/
H A Ddot_writer.py202 # NULL ISA has no BaseCPU or PioDevice, so check if these names
204 elif 'BaseCPU' in dir(m5.objects) and \
205 isinstance(simNode, m5.objects.BaseCPU):
/gem5/src/sim/
H A Dsystem.cc270 BaseCPU *cpu = tc->getCpuPtr();
/gem5/src/arch/x86/
H A Dinterrupts.cc275 X86ISA::Interrupts::setCPU(BaseCPU * newCPU)

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