Searched refs:BaseCPU (Results 51 - 73 of 73) sorted by relevance
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/gem5/src/cpu/ |
H A D | simple_thread.hh | 71 class BaseCPU; 138 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 142 SimpleThread(BaseCPU *_cpu, int _thread_num, System *_system, 191 BaseCPU *getCpuPtr() override { return baseCpu; }
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H A D | BaseCPU.py | 113 class BaseCPU(ClockedObject): class in inherits:ClockedObject 114 type = 'BaseCPU' 166 checker = Param.BaseCPU(NULL, "checker CPU")
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H A D | base_dyn_inst.hh | 159 BaseCPU *getCpuPtr() { return cpu; }
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/gem5/src/cpu/minor/ |
H A D | pipeline.cc | 57 Ticked(cpu_, &(cpu_.BaseCPU::numCycles)),
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H A D | fetch2.cc | 332 (line_in->pc.instAddr() & BaseCPU::PCMask) -
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H A D | exec_context.hh | 443 BaseCPU *getCpuPtr() { return &cpu; }
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/gem5/src/cpu/trace/ |
H A D | trace_cpu.hh | 71 * The TraceCPU inherits from BaseCPU so some virtual methods need to be 144 class TraceCPU : public BaseCPU 154 * This is a pure virtual function in BaseCPU. As we don't know how many 182 /* Pure virtual function in BaseCPU. Do nothing. */ 191 * BaseCPU. It unbinds the ports of the old CPU and binds the ports of the 194 void takeOverFrom(BaseCPU *oldCPU);
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H A D | trace_cpu.cc | 50 : BaseCPU(params), 106 TraceCPU::takeOverFrom(BaseCPU *oldCPU) 121 BaseCPU::init(); 220 BaseCPU::regStats();
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/gem5/src/arch/mips/ |
H A D | isa.cc | 519 ISA::scheduleCP0Update(BaseCPU *cpu, Cycles delay) 533 ISA::updateCPU(BaseCPU *cpu) 562 ISA::processCP0Event(BaseCPU *cpu, CP0EventType cp0EventType)
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/gem5/src/cpu/o3/ |
H A D | cpu.hh | 83 class BaseO3CPU : public BaseCPU 309 void takeOverFrom(BaseCPU *oldCPU) override;
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H A D | fetch_impl.hh | 1184 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1272 fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1364 fetchAddr = thisPC.instAddr() & BaseCPU::PCMask; 1409 fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask; 1613 Addr fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
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H A D | thread_context.hh | 102 BaseCPU *getCpuPtr() override { return cpu; }
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/gem5/src/arch/arm/linux/ |
H A D | system.cc | 255 if (pid != BaseCPU::invldPid) {
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/gem5/src/cpu/checker/ |
H A D | cpu.cc | 69 : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
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H A D | thread_context.hh | 93 BaseCPU *getCpuPtr() override { return actualTC->getCpuPtr(); }
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H A D | cpu_impl.hh | 453 Checker<Impl>::takeOverFrom(BaseCPU *oldCPU)
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/gem5/src/cpu/simple/ |
H A D | timing.hh | 278 void takeOverFrom(BaseCPU *oldCPU) override;
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/gem5/src/arch/sparc/ |
H A D | isa.cc | 685 BaseCPU *cpu = NULL; 771 BaseCPU *cpu = NULL;
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/gem5/src/gpu-compute/ |
H A D | shader.cc | 132 Shader::hostWakeUp(BaseCPU *cpu) {
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H A D | dispatcher.cc | 355 GpuDispatcher::accessUserVar(BaseCPU *cpu, uint64_t addr, int val, int off)
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/gem5/src/python/m5/util/ |
H A D | dot_writer.py | 202 # NULL ISA has no BaseCPU or PioDevice, so check if these names 204 elif 'BaseCPU' in dir(m5.objects) and \ 205 isinstance(simNode, m5.objects.BaseCPU):
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/gem5/src/sim/ |
H A D | system.cc | 270 BaseCPU *cpu = tc->getCpuPtr();
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/gem5/src/arch/x86/ |
H A D | interrupts.cc | 275 X86ISA::Interrupts::setCPU(BaseCPU * newCPU)
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