Searched hist:56 (Results 276 - 300 of 501) sorted by relevance
| /gem5/tests/long/fs/10.linux-boot/ref/arm/linux/realview-o3-dual/ | ||
| H A D | config.ini | diff 11957:90bb43dfc028 Wed Mar 29 21:50:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update ARM FS stats. The change below changed the behavior of interrupts on ARM and changed the stats for the 10.linux-boot regression. commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b Author: Sudhanshu Jha <sudhanshu.jha@arm.com> Date: Mon Feb 27 10:29:56 2017 +0000 arm, kmi: Clear interrupts in KMI devices Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a Reviewed-on: https://gem5-review.googlesource.com/2653 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
| H A D | simout | diff 11957:90bb43dfc028 Wed Mar 29 21:50:00 EDT 2017 Gabe Black <gabeblack@google.com> stats: Update ARM FS stats. The change below changed the behavior of interrupts on ARM and changed the stats for the 10.linux-boot regression. commit 746e2f3c27ad83c36b7bc3b8bd3c92004fcf995b Author: Sudhanshu Jha <sudhanshu.jha@arm.com> Date: Mon Feb 27 10:29:56 2017 +0000 arm, kmi: Clear interrupts in KMI devices Change-Id: Ie1cfc26777f6ed2d3fd4340175941fda1fdb5b6a Reviewed-on: https://gem5-review.googlesource.com/2653 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
| /gem5/src/cpu/o3/ | ||
| H A D | scoreboard.hh | diff 10104:ff709c429b7b Fri Mar 07 15:56:00 EST 2014 Mitch Hayenga <mitch.hayenga@arm.com> scons: Fixes uninitialized warnings issued by clang Small fixes to appease recent clang versions. |
| /gem5/src/dev/arm/ | ||
| H A D | hdlcd.hh | diff 11091:62e1504b9c64 Fri Sep 11 10:56:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Add an underrun statistic to the HDLCD controller Add a stat that counts buffer underruns in the HDLCD controller. The stat counts at most one underrun per frame since the controller aborts the current frame if it underruns. |
| H A D | hdlcd.cc | diff 11091:62e1504b9c64 Fri Sep 11 10:56:00 EDT 2015 Andreas Sandberg <andreas.sandberg@arm.com> dev: Add an underrun statistic to the HDLCD controller Add a stat that counts buffer underruns in the HDLCD controller. The stat counts at most one underrun per frame since the controller aborts the current frame if it underruns. |
| H A D | pl011.cc | diff 9806:3f262c18ad5d Thu Jul 11 22:56:00 EDT 2013 Steve Reinhardt <stever@gmail.com> dev/arm: get rid of AmbaDev namespace It was confusing having an AmbaDev namespace along with an AmbaDevice class. The namespace stuff is now moved in to a new base AmbaDevice class, which is a mixin for classes AmbaPioDevice (the former AmbaDevice) and AmbaDmaDevice to provide the readId function as an inherited member function. Committed by: Nilay Vaish <nilay@cs.wisc.edu> |
| /gem5/src/arch/x86/ | ||
| H A D | faults.hh | diff 6049:595b5016f6d5 Sun Apr 19 05:56:00 EDT 2009 Gabe Black <gblack@eecs.umich.edu> X86: Implement the STARTUP IPI. |
| H A D | isa.hh | diff 9553:2e1e5364dae3 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for overloaded virtual functions Fix the ISA startup warnings |
| /gem5/src/systemc/core/ | ||
| H A D | sc_time.cc | diff 13410:a03275d35b40 Wed Nov 07 20:56:00 EST 2018 Gabe Black <gabeblack@google.com> systemc: Stop using python to set/manage the global time resolution. Now that that's managed in c++, we can do that directly without having to depend on the python code being available, the code which lets us call from c++ to python, or for the embedded python interpretter to have started running and have loaded the appropriate modules. Change-Id: Ied110d8f22181095f8c0c645636a9bd67964263e Reviewed-on: https://gem5-review.googlesource.com/c/14056 Maintainer: Gabe Black <gabeblack@google.com> Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> |
| /gem5/src/arch/alpha/ | ||
| H A D | locked_mem.hh | diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. |
| H A D | isa.hh | diff 9553:2e1e5364dae3 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for overloaded virtual functions Fix the ISA startup warnings |
| H A D | process.hh | diff 9552:460cf901acba Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for overloaded virtual functions A derived function with a different signature than a base class function will result in the base class function of the same name being hidden. The parameter list and return type for the member function in the derived class must match those of the member function in the base class, otherwise the function in the derived class will hide the function in the base class and no polymorphic behaviour will occur. This patch addresses these warnings by ensuring a unique function name to avoid (unintentionally) hiding any functions. |
| /gem5/src/arch/arm/isa/formats/ | ||
| H A D | misc.isa | diff 9554:406fbcf60223 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for missing declarations This patch enables warnings for missing declarations. To avoid issues with SWIG-generated code, the warning is only applied to non-SWIG code. |
| /gem5/src/arch/mips/ | ||
| H A D | locked_mem.hh | diff 5712:199d31b47f7b Sun Nov 02 21:56:00 EST 2008 Lisa Hsu <hsul@eecs.umich.edu> make BaseCPU the provider of _cpuId, and cpuId() instead of being scattered across the subclasses. generally make it so that member data is _cpuId and accessor functions are cpuId(). The ID val comes from the python (default -1 if none provided), and if it is -1, the index of cpuList will be given. this has passed util/regress quick and se.py -n4 and fs.py -n4 as well as standard switch. |
| H A D | isa.hh | diff 9553:2e1e5364dae3 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for overloaded virtual functions Fix the ISA startup warnings |
| /gem5/src/base/ | ||
| H A D | compiler.hh | diff 10104:ff709c429b7b Fri Mar 07 15:56:00 EST 2014 Mitch Hayenga <mitch.hayenga@arm.com> scons: Fixes uninitialized warnings issued by clang Small fixes to appease recent clang versions. |
| H A D | addr_range.hh | diff 9541:e476d01bc6a4 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> base: Fix a bug in the address interleaving This patch fixes a minor (but important) typo in the matching of an address to an interleaved range. |
| /gem5/src/dev/ | ||
| H A D | isa_fake.cc | diff 8461:7d0669201f80 Sun Jul 10 01:56:00 EDT 2011 Ali Saidi <Ali.Saidi@ARM.com> IO: Handle case where ISA Fake device is being used as a fake memory. |
| /gem5/src/mem/cache/ | ||
| H A D | mshr_queue.hh | diff 12727:56c23b54bcb1 Wed May 02 19:14:00 EDT 2018 Nikos Nikoleris <nikos.nikoleris@arm.com> mem-cache: Fix include directives in the cache related classes Change-Id: I111b0f662897c43974aadb08da1ed85c7542585c Reviewed-on: https://gem5-review.googlesource.com/10433 Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br> Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com> |
| /gem5/src/arch/mips/isa/formats/ | ||
| H A D | control.isa | diff 9554:406fbcf60223 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for missing declarations This patch enables warnings for missing declarations. To avoid issues with SWIG-generated code, the warning is only applied to non-SWIG code. |
| H A D | mt.isa | diff 9554:406fbcf60223 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for missing declarations This patch enables warnings for missing declarations. To avoid issues with SWIG-generated code, the warning is only applied to non-SWIG code. |
| /gem5/src/arch/sparc/ | ||
| H A D | isa.hh | diff 9553:2e1e5364dae3 Tue Feb 19 05:56:00 EST 2013 Andreas Hansson <andreas.hansson@arm.com> scons: Add warning for overloaded virtual functions Fix the ISA startup warnings |
| /gem5/src/cpu/pred/ | ||
| H A D | ltage.cc | diff 13455:56e25a5f9603 Thu Nov 22 08:48:00 EST 2018 Pau Cabre <pau.cabre@metempsy.com> cpu: Added new stats to TAGE and LTAGE branch predictors They are basically used to tell wich component of the predictor is providing the prediction and whether it is correct or wrong Change-Id: I7b3db66535f159091f1b37d70c2d942d50b20fb2 Signed-off-by: Pau Cabre <pau.cabre@metempsy.com> Reviewed-on: https://gem5-review.googlesource.com/c/14535 Reviewed-by: Jason Lowe-Power <jason@lowepower.com> Maintainer: Jason Lowe-Power <jason@lowepower.com> |
| /gem5/src/kern/linux/ | ||
| H A D | linux.hh | diff 5795:72ce7502dc71 Sat Jan 17 18:56:00 EST 2009 Ali Saidi <saidi@eecs.umich.edu> Fix issue 326: glibc non-deterministic because it reads /proc |
| /gem5/src/systemc/ext/core/ | ||
| H A D | sc_module.hh | diff 12901:72bc9ff65802 Fri Jun 15 17:56:00 EDT 2018 Gabe Black <gabeblack@google.com> systemc: Add the nonstandard macro SC_NEW. This is in the Accellera implementation and in the regression tests. The implementation here is a bit different than theirs in that it uses std::unique_ptrs. Change-Id: Id3d1ad82482b94a5d99f27e02d1e447ca1944797 Reviewed-on: https://gem5-review.googlesource.com/11255 Reviewed-by: Gabe Black <gabeblack@google.com> Maintainer: Gabe Black <gabeblack@google.com> |
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