17584SAli.Saidi@arm.com/* 210718SAndreas.Sandberg@ARM.com * Copyright (c) 2010, 2015 ARM Limited 37584SAli.Saidi@arm.com * All rights reserved 47584SAli.Saidi@arm.com * 57584SAli.Saidi@arm.com * The license below extends only to copyright in the software and shall 67584SAli.Saidi@arm.com * not be construed as granting a license to any other intellectual 77584SAli.Saidi@arm.com * property including but not limited to intellectual property relating 87584SAli.Saidi@arm.com * to a hardware implementation of the functionality of the software 97584SAli.Saidi@arm.com * licensed hereunder. You may use the software subject to the license 107584SAli.Saidi@arm.com * terms below provided that you ensure that this notice is replicated 117584SAli.Saidi@arm.com * unmodified and in its entirety in all distributions of the software, 127584SAli.Saidi@arm.com * modified or unmodified, in source code or in binary form. 137584SAli.Saidi@arm.com * 147584SAli.Saidi@arm.com * Copyright (c) 2005 The Regents of The University of Michigan 157584SAli.Saidi@arm.com * All rights reserved. 167584SAli.Saidi@arm.com * 177584SAli.Saidi@arm.com * Redistribution and use in source and binary forms, with or without 187584SAli.Saidi@arm.com * modification, are permitted provided that the following conditions are 197584SAli.Saidi@arm.com * met: redistributions of source code must retain the above copyright 207584SAli.Saidi@arm.com * notice, this list of conditions and the following disclaimer; 217584SAli.Saidi@arm.com * redistributions in binary form must reproduce the above copyright 227584SAli.Saidi@arm.com * notice, this list of conditions and the following disclaimer in the 237584SAli.Saidi@arm.com * documentation and/or other materials provided with the distribution; 247584SAli.Saidi@arm.com * neither the name of the copyright holders nor the names of its 257584SAli.Saidi@arm.com * contributors may be used to endorse or promote products derived from 267584SAli.Saidi@arm.com * this software without specific prior written permission. 277584SAli.Saidi@arm.com * 287584SAli.Saidi@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 297584SAli.Saidi@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307584SAli.Saidi@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 317584SAli.Saidi@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 327584SAli.Saidi@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 337584SAli.Saidi@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 347584SAli.Saidi@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 357584SAli.Saidi@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367584SAli.Saidi@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377584SAli.Saidi@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387584SAli.Saidi@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 397584SAli.Saidi@arm.com * 407584SAli.Saidi@arm.com * Authors: Ali Saidi 4110718SAndreas.Sandberg@ARM.com * Andreas Sandberg 427584SAli.Saidi@arm.com */ 437584SAli.Saidi@arm.com 4410718SAndreas.Sandberg@ARM.com#include "dev/arm/pl011.hh" 4510718SAndreas.Sandberg@ARM.com 467584SAli.Saidi@arm.com#include "base/trace.hh" 478245Snate@binkert.org#include "debug/Checkpoint.hh" 488245Snate@binkert.org#include "debug/Uart.hh" 497587SAli.Saidi@arm.com#include "dev/arm/amba_device.hh" 509525SAndreas.Sandberg@ARM.com#include "dev/arm/base_gic.hh" 517584SAli.Saidi@arm.com#include "mem/packet.hh" 527584SAli.Saidi@arm.com#include "mem/packet_access.hh" 5311793Sbrandon.potter@amd.com#include "params/Pl011.hh" 547584SAli.Saidi@arm.com#include "sim/sim_exit.hh" 557584SAli.Saidi@arm.com 5610718SAndreas.Sandberg@ARM.comPl011::Pl011(const Pl011Params *p) 5712772Snikos.nikoleris@arm.com : Uart(p, 0x1000), 5812086Sspwilson2@wisc.edu intEvent([this]{ generateInterrupt(); }, name()), 5910718SAndreas.Sandberg@ARM.com control(0x300), fbrd(0), ibrd(0), lcrh(0), ifls(0x12), 6010718SAndreas.Sandberg@ARM.com imsc(0), rawInt(0), 6110718SAndreas.Sandberg@ARM.com gic(p->gic), endOnEOT(p->end_on_eot), intNum(p->int_num), 6210718SAndreas.Sandberg@ARM.com intDelay(p->int_delay) 637584SAli.Saidi@arm.com{ 647584SAli.Saidi@arm.com} 657584SAli.Saidi@arm.com 667584SAli.Saidi@arm.comTick 677584SAli.Saidi@arm.comPl011::read(PacketPtr pkt) 687584SAli.Saidi@arm.com{ 697584SAli.Saidi@arm.com assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 707584SAli.Saidi@arm.com 717584SAli.Saidi@arm.com Addr daddr = pkt->getAddr() - pioAddr; 727584SAli.Saidi@arm.com 737584SAli.Saidi@arm.com DPRINTF(Uart, " read register %#x size=%d\n", daddr, pkt->getSize()); 747584SAli.Saidi@arm.com 757584SAli.Saidi@arm.com // use a temporary data since the uart registers are read/written with 767584SAli.Saidi@arm.com // different size operations 777584SAli.Saidi@arm.com // 787584SAli.Saidi@arm.com uint32_t data = 0; 797584SAli.Saidi@arm.com 807584SAli.Saidi@arm.com switch(daddr) { 817584SAli.Saidi@arm.com case UART_DR: 827584SAli.Saidi@arm.com data = 0; 8312237Sandreas.sandberg@arm.com if (device->dataAvailable()) { 8412237Sandreas.sandberg@arm.com data = device->readData(); 8510718SAndreas.Sandberg@ARM.com // Since we don't simulate a FIFO for incoming data, we 8610718SAndreas.Sandberg@ARM.com // assume it's empty and clear RXINTR and RTINTR. 8710718SAndreas.Sandberg@ARM.com clearInterrupts(UART_RXINTR | UART_RTINTR); 8812237Sandreas.sandberg@arm.com if (device->dataAvailable()) { 8911685Sbaz21@cam.ac.uk DPRINTF(Uart, "Re-raising interrupt due to more data " 9011685Sbaz21@cam.ac.uk "after UART_DR read\n"); 9111685Sbaz21@cam.ac.uk dataAvailable(); 9211685Sbaz21@cam.ac.uk } 9310718SAndreas.Sandberg@ARM.com } 947584SAli.Saidi@arm.com break; 9513024Smadnaurice@googlemail.com case UART_RSR: 9613024Smadnaurice@googlemail.com data = 0x0; // We never have errors 9713024Smadnaurice@googlemail.com break; 987584SAli.Saidi@arm.com case UART_FR: 9910718SAndreas.Sandberg@ARM.com data = 10010718SAndreas.Sandberg@ARM.com UART_FR_CTS | // Clear To Send 10111480Sbaz21@cam.ac.uk // Given we do not simulate a FIFO we are either empty or full. 10212237Sandreas.sandberg@arm.com (!device->dataAvailable() ? UART_FR_RXFE : UART_FR_RXFF) | 10310718SAndreas.Sandberg@ARM.com UART_FR_TXFE; // TX FIFO empty 10410718SAndreas.Sandberg@ARM.com 10510718SAndreas.Sandberg@ARM.com DPRINTF(Uart, 10610718SAndreas.Sandberg@ARM.com "Reading FR register as %#x rawInt=0x%x " 10710718SAndreas.Sandberg@ARM.com "imsc=0x%x maskInt=0x%x\n", 10810718SAndreas.Sandberg@ARM.com data, rawInt, imsc, maskInt()); 1097584SAli.Saidi@arm.com break; 1107584SAli.Saidi@arm.com case UART_CR: 1117584SAli.Saidi@arm.com data = control; 1127584SAli.Saidi@arm.com break; 1137584SAli.Saidi@arm.com case UART_IBRD: 1147584SAli.Saidi@arm.com data = ibrd; 1157584SAli.Saidi@arm.com break; 1167584SAli.Saidi@arm.com case UART_FBRD: 1177584SAli.Saidi@arm.com data = fbrd; 1187584SAli.Saidi@arm.com break; 1197584SAli.Saidi@arm.com case UART_LCRH: 1207584SAli.Saidi@arm.com data = lcrh; 1217584SAli.Saidi@arm.com break; 1227584SAli.Saidi@arm.com case UART_IFLS: 1237584SAli.Saidi@arm.com data = ifls; 1247584SAli.Saidi@arm.com break; 1257584SAli.Saidi@arm.com case UART_IMSC: 1267584SAli.Saidi@arm.com data = imsc; 1277584SAli.Saidi@arm.com break; 1287584SAli.Saidi@arm.com case UART_RIS: 1297584SAli.Saidi@arm.com data = rawInt; 1307584SAli.Saidi@arm.com DPRINTF(Uart, "Reading Raw Int status as 0x%x\n", rawInt); 1317584SAli.Saidi@arm.com break; 1327584SAli.Saidi@arm.com case UART_MIS: 13310718SAndreas.Sandberg@ARM.com DPRINTF(Uart, "Reading Masked Int status as 0x%x\n", maskInt()); 13410718SAndreas.Sandberg@ARM.com data = maskInt(); 1357584SAli.Saidi@arm.com break; 13613507Sjan-peter.larsson@arm.com case UART_DMACR: 13713507Sjan-peter.larsson@arm.com warn("PL011: DMA not supported\n"); 13813507Sjan-peter.larsson@arm.com data = 0x0; // DMA never enabled 13913507Sjan-peter.larsson@arm.com break; 1407584SAli.Saidi@arm.com default: 1419806Sstever@gmail.com if (readId(pkt, AMBA_ID, pioAddr)) { 1427587SAli.Saidi@arm.com // Hack for variable size accesses 14313230Sgabeblack@google.com data = pkt->getLE<uint32_t>(); 1447584SAli.Saidi@arm.com break; 1457584SAli.Saidi@arm.com } 1467587SAli.Saidi@arm.com 1477584SAli.Saidi@arm.com panic("Tried to read PL011 at offset %#x that doesn't exist\n", daddr); 1487584SAli.Saidi@arm.com break; 1497584SAli.Saidi@arm.com } 1507584SAli.Saidi@arm.com 1517584SAli.Saidi@arm.com switch(pkt->getSize()) { 1527584SAli.Saidi@arm.com case 1: 15313230Sgabeblack@google.com pkt->setLE<uint8_t>(data); 1547584SAli.Saidi@arm.com break; 1557584SAli.Saidi@arm.com case 2: 15613230Sgabeblack@google.com pkt->setLE<uint16_t>(data); 1577584SAli.Saidi@arm.com break; 1587584SAli.Saidi@arm.com case 4: 15913230Sgabeblack@google.com pkt->setLE<uint32_t>(data); 1607584SAli.Saidi@arm.com break; 1617584SAli.Saidi@arm.com default: 1627584SAli.Saidi@arm.com panic("Uart read size too big?\n"); 1637584SAli.Saidi@arm.com break; 1647584SAli.Saidi@arm.com } 1657584SAli.Saidi@arm.com 1667584SAli.Saidi@arm.com 1677584SAli.Saidi@arm.com pkt->makeAtomicResponse(); 1687584SAli.Saidi@arm.com return pioDelay; 1697584SAli.Saidi@arm.com} 1707584SAli.Saidi@arm.com 1717584SAli.Saidi@arm.comTick 1727584SAli.Saidi@arm.comPl011::write(PacketPtr pkt) 1737584SAli.Saidi@arm.com{ 1747584SAli.Saidi@arm.com 1757584SAli.Saidi@arm.com assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); 1767584SAli.Saidi@arm.com 1777584SAli.Saidi@arm.com Addr daddr = pkt->getAddr() - pioAddr; 1787584SAli.Saidi@arm.com 1797584SAli.Saidi@arm.com DPRINTF(Uart, " write register %#x value %#x size=%d\n", daddr, 18013230Sgabeblack@google.com pkt->getLE<uint8_t>(), pkt->getSize()); 1817584SAli.Saidi@arm.com 1827584SAli.Saidi@arm.com // use a temporary data since the uart registers are read/written with 1837584SAli.Saidi@arm.com // different size operations 1847584SAli.Saidi@arm.com // 1857584SAli.Saidi@arm.com uint32_t data = 0; 1867584SAli.Saidi@arm.com 1877584SAli.Saidi@arm.com switch(pkt->getSize()) { 1887584SAli.Saidi@arm.com case 1: 18913230Sgabeblack@google.com data = pkt->getLE<uint8_t>(); 1907584SAli.Saidi@arm.com break; 1917584SAli.Saidi@arm.com case 2: 19213230Sgabeblack@google.com data = pkt->getLE<uint16_t>(); 1937584SAli.Saidi@arm.com break; 1947584SAli.Saidi@arm.com case 4: 19513230Sgabeblack@google.com data = pkt->getLE<uint32_t>(); 1967584SAli.Saidi@arm.com break; 1977584SAli.Saidi@arm.com default: 1987584SAli.Saidi@arm.com panic("Uart write size too big?\n"); 1997584SAli.Saidi@arm.com break; 2007584SAli.Saidi@arm.com } 2017584SAli.Saidi@arm.com 2027584SAli.Saidi@arm.com 2037584SAli.Saidi@arm.com switch (daddr) { 2047584SAli.Saidi@arm.com case UART_DR: 2057584SAli.Saidi@arm.com if ((data & 0xFF) == 0x04 && endOnEOT) 2067584SAli.Saidi@arm.com exitSimLoop("UART received EOT", 0); 2077584SAli.Saidi@arm.com 20812237Sandreas.sandberg@arm.com device->writeData(data & 0xFF); 20910718SAndreas.Sandberg@ARM.com // We're supposed to clear TXINTR when this register is 21010718SAndreas.Sandberg@ARM.com // written to, however. since we're also infinitely fast, we 21110718SAndreas.Sandberg@ARM.com // need to immediately raise it again. 21210718SAndreas.Sandberg@ARM.com clearInterrupts(UART_TXINTR); 21310718SAndreas.Sandberg@ARM.com raiseInterrupts(UART_TXINTR); 2147584SAli.Saidi@arm.com break; 21513024Smadnaurice@googlemail.com case UART_ECR: // clears errors, ignore 21613024Smadnaurice@googlemail.com break; 2177584SAli.Saidi@arm.com case UART_CR: 2187584SAli.Saidi@arm.com control = data; 2197584SAli.Saidi@arm.com break; 2207584SAli.Saidi@arm.com case UART_IBRD: 2217584SAli.Saidi@arm.com ibrd = data; 2227584SAli.Saidi@arm.com break; 2237584SAli.Saidi@arm.com case UART_FBRD: 2247584SAli.Saidi@arm.com fbrd = data; 2257584SAli.Saidi@arm.com break; 2267584SAli.Saidi@arm.com case UART_LCRH: 2277584SAli.Saidi@arm.com lcrh = data; 2287584SAli.Saidi@arm.com break; 2297584SAli.Saidi@arm.com case UART_IFLS: 2307584SAli.Saidi@arm.com ifls = data; 2317584SAli.Saidi@arm.com break; 2327584SAli.Saidi@arm.com case UART_IMSC: 23310718SAndreas.Sandberg@ARM.com DPRINTF(Uart, "Setting interrupt mask 0x%x\n", data); 23410718SAndreas.Sandberg@ARM.com setInterruptMask(data); 2357584SAli.Saidi@arm.com break; 2367584SAli.Saidi@arm.com 2377584SAli.Saidi@arm.com case UART_ICR: 2387584SAli.Saidi@arm.com DPRINTF(Uart, "Clearing interrupts 0x%x\n", data); 23910718SAndreas.Sandberg@ARM.com clearInterrupts(data); 24012237Sandreas.sandberg@arm.com if (device->dataAvailable()) { 24111685Sbaz21@cam.ac.uk DPRINTF(Uart, "Re-raising interrupt due to more data after " 24211685Sbaz21@cam.ac.uk "UART_ICR write\n"); 24311685Sbaz21@cam.ac.uk dataAvailable(); 24411685Sbaz21@cam.ac.uk } 2457584SAli.Saidi@arm.com break; 24613507Sjan-peter.larsson@arm.com case UART_DMACR: 24713507Sjan-peter.larsson@arm.com // DMA is not supported, so panic if anyome tries to enable it. 24813507Sjan-peter.larsson@arm.com // Bits 0, 1, 2 enables DMA on RX, TX, ERR respectively, others res0. 24913507Sjan-peter.larsson@arm.com if (data & 0x7) { 25013507Sjan-peter.larsson@arm.com panic("Tried to enable DMA on PL011\n"); 25113507Sjan-peter.larsson@arm.com } 25213507Sjan-peter.larsson@arm.com warn("PL011: DMA not supported\n"); 25313507Sjan-peter.larsson@arm.com break; 2547584SAli.Saidi@arm.com default: 2557584SAli.Saidi@arm.com panic("Tried to write PL011 at offset %#x that doesn't exist\n", daddr); 2567584SAli.Saidi@arm.com break; 2577584SAli.Saidi@arm.com } 2587584SAli.Saidi@arm.com pkt->makeAtomicResponse(); 2597584SAli.Saidi@arm.com return pioDelay; 2607584SAli.Saidi@arm.com} 2617584SAli.Saidi@arm.com 2627584SAli.Saidi@arm.comvoid 2637584SAli.Saidi@arm.comPl011::dataAvailable() 2647584SAli.Saidi@arm.com{ 2657584SAli.Saidi@arm.com /*@todo ignore the fifo, just say we have data now 2667584SAli.Saidi@arm.com * We might want to fix this, or we might not care */ 2677584SAli.Saidi@arm.com DPRINTF(Uart, "Data available, scheduling interrupt\n"); 26810718SAndreas.Sandberg@ARM.com raiseInterrupts(UART_RXINTR | UART_RTINTR); 2697584SAli.Saidi@arm.com} 2707584SAli.Saidi@arm.com 2717584SAli.Saidi@arm.comvoid 2727584SAli.Saidi@arm.comPl011::generateInterrupt() 2737584SAli.Saidi@arm.com{ 2747584SAli.Saidi@arm.com DPRINTF(Uart, "Generate Interrupt: imsc=0x%x rawInt=0x%x maskInt=0x%x\n", 27510718SAndreas.Sandberg@ARM.com imsc, rawInt, maskInt()); 2767584SAli.Saidi@arm.com 27710718SAndreas.Sandberg@ARM.com if (maskInt()) { 2787584SAli.Saidi@arm.com gic->sendInt(intNum); 2797584SAli.Saidi@arm.com DPRINTF(Uart, " -- Generated\n"); 2807584SAli.Saidi@arm.com } 28110718SAndreas.Sandberg@ARM.com} 2827584SAli.Saidi@arm.com 28310718SAndreas.Sandberg@ARM.comvoid 28410718SAndreas.Sandberg@ARM.comPl011::setInterrupts(uint16_t ints, uint16_t mask) 28510718SAndreas.Sandberg@ARM.com{ 28610718SAndreas.Sandberg@ARM.com const bool old_ints(!!maskInt()); 28710718SAndreas.Sandberg@ARM.com 28810718SAndreas.Sandberg@ARM.com imsc = mask; 28910718SAndreas.Sandberg@ARM.com rawInt = ints; 29010718SAndreas.Sandberg@ARM.com 29110718SAndreas.Sandberg@ARM.com if (!old_ints && maskInt()) { 29210718SAndreas.Sandberg@ARM.com if (!intEvent.scheduled()) 29310718SAndreas.Sandberg@ARM.com schedule(intEvent, curTick() + intDelay); 29410718SAndreas.Sandberg@ARM.com } else if (old_ints && !maskInt()) { 29510718SAndreas.Sandberg@ARM.com gic->clearInt(intNum); 29610718SAndreas.Sandberg@ARM.com } 2977584SAli.Saidi@arm.com} 2987584SAli.Saidi@arm.com 2997584SAli.Saidi@arm.com 3007584SAli.Saidi@arm.com 3017584SAli.Saidi@arm.comvoid 30210905Sandreas.sandberg@arm.comPl011::serialize(CheckpointOut &cp) const 3037584SAli.Saidi@arm.com{ 3047733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Serializing Arm PL011\n"); 3057733SAli.Saidi@ARM.com SERIALIZE_SCALAR(control); 3067733SAli.Saidi@ARM.com SERIALIZE_SCALAR(fbrd); 3077733SAli.Saidi@ARM.com SERIALIZE_SCALAR(ibrd); 3087733SAli.Saidi@ARM.com SERIALIZE_SCALAR(lcrh); 3097733SAli.Saidi@ARM.com SERIALIZE_SCALAR(ifls); 3107733SAli.Saidi@ARM.com 31110718SAndreas.Sandberg@ARM.com // Preserve backwards compatibility by giving these silly names. 31210905Sandreas.sandberg@arm.com paramOut(cp, "imsc_serial", imsc); 31310905Sandreas.sandberg@arm.com paramOut(cp, "rawInt_serial", rawInt); 3147584SAli.Saidi@arm.com} 3157584SAli.Saidi@arm.com 3167584SAli.Saidi@arm.comvoid 31710905Sandreas.sandberg@arm.comPl011::unserialize(CheckpointIn &cp) 3187584SAli.Saidi@arm.com{ 3197733SAli.Saidi@ARM.com DPRINTF(Checkpoint, "Unserializing Arm PL011\n"); 3207733SAli.Saidi@ARM.com 3217733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(control); 3227733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(fbrd); 3237733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(ibrd); 3247733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(lcrh); 3257733SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(ifls); 3267733SAli.Saidi@ARM.com 32710718SAndreas.Sandberg@ARM.com // Preserve backwards compatibility by giving these silly names. 32810905Sandreas.sandberg@arm.com paramIn(cp, "imsc_serial", imsc); 32910905Sandreas.sandberg@arm.com paramIn(cp, "rawInt_serial", rawInt); 3307584SAli.Saidi@arm.com} 3317584SAli.Saidi@arm.com 3327584SAli.Saidi@arm.comPl011 * 3337584SAli.Saidi@arm.comPl011Params::create() 3347584SAli.Saidi@arm.com{ 3357584SAli.Saidi@arm.com return new Pl011(this); 3367584SAli.Saidi@arm.com} 337